rockchip: clk: rk3188: Allow configuration of the armclk
The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole startup take a lot of time. We therefore want to at least move to the safe 600MHz value we can use with default pmic settings. This is also the freqency the proprietary sdram-init leaves the cpu at. For boards that have pmic control later in u-boot, we also add the option to set the maximum frequency of 1.6GHz, if they so desire. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
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@ -9,6 +9,7 @@
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#define OSC_HZ (24 * 1000 * 1000)
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#define APLL_HZ (1608 * 1000000)
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#define APLL_SAFE_HZ (600 * 1000000)
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#define GPLL_HZ (594 * 1000000)
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#define CPLL_HZ (384 * 1000000)
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@ -168,6 +168,65 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf,
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return 0;
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}
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static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf,
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unsigned int hz, bool has_bwadj)
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{
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static const struct pll_div apll_cfg[] = {
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{.nf = 50, .nr = 1, .no = 2},
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{.nf = 67, .nr = 1, .no = 1},
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};
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int div_core_peri, div_aclk_core, cfg;
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/*
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* We support two possible frequencies, the safe 600MHz
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* which will work with default pmic settings and will
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* be set in SPL to get away from the 24MHz default and
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* the maximum of 1.6Ghz, which boards can set if they
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* were able to get pmic support for it.
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*/
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switch (hz) {
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case APLL_SAFE_HZ:
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cfg = 0;
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div_core_peri = 1;
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div_aclk_core = 3;
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break;
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case APLL_HZ:
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cfg = 1;
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div_core_peri = 2;
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div_aclk_core = 3;
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break;
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default:
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debug("Unsupported ARMCLK frequency");
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return -EINVAL;
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}
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/* pll enter slow-mode */
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rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
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APLL_MODE_SLOW << APLL_MODE_SHIFT);
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rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj);
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/* waiting for pll lock */
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while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK))
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udelay(1);
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/* Set divider for peripherals attached to the cpu core. */
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rk_clrsetreg(&cru->cru_clksel_con[0],
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CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT,
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div_core_peri << CORE_PERI_DIV_SHIFT);
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/* set up dependent divisor for aclk_core */
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rk_clrsetreg(&cru->cru_clksel_con[1],
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CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT,
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div_aclk_core << CORE_ACLK_DIV_SHIFT);
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/* PLL enter normal-mode */
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rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
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APLL_MODE_NORMAL << APLL_MODE_SHIFT);
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return hz;
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}
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/* Get pll rate by id */
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static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru,
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enum rk_clk_id clk_id)
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@ -435,6 +494,10 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
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ulong new_rate;
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switch (clk->id) {
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case PLL_APLL:
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new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate,
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priv->has_bwadj);
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break;
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case CLK_DDR:
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new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate,
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priv->has_bwadj);
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