armv8: layerscape: move spin table into own module
Move it out of lowlevel.S into spintable.S. On layerscape, the secondary CPUs are brought up in main u-boot. This will make it possible to only compile the spin table code for the main u-boot and omit it in SPL. This saves about 720 bytes in the SPL. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Michael Walle
Priyanka Jain
parent
3d3fe8b12d
commit
f6c62f1c9e
@ -6,7 +6,7 @@ obj-y += cpu.o
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obj-y += lowlevel.o
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obj-y += soc.o
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ifndef CONFIG_SPL_BUILD
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obj-$(CONFIG_MP) += mp.o
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obj-$(CONFIG_MP) += mp.o spintable.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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endif
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obj-$(CONFIG_SPL) += spl.o
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@ -11,14 +11,16 @@
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#include <asm/gic.h>
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#include <asm/macro.h>
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#include <asm/arch-fsl-layerscape/soc.h>
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#ifdef CONFIG_MP
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#include <asm/arch/mp.h>
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#endif
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#ifdef CONFIG_FSL_LSCH3
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#include <asm/arch-fsl-layerscape/immap_lsch3.h>
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#endif
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#include <asm/u-boot.h>
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.align 3
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.weak secondary_boot_addr
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secondary_boot_addr:
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.quad 0
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/* Get GIC offset
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* For LS1043a rev1.0, GIC base address align with 4k.
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* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
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@ -424,149 +426,3 @@ ENTRY(__asm_flush_l3_dcache)
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ret
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ENDPROC(__asm_flush_l3_dcache)
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#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
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#ifdef CONFIG_MP
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.align 3
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.global secondary_boot_addr
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secondary_boot_addr:
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.quad secondary_boot_func
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/* Keep literals not used by the secondary boot code outside it */
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.ltorg
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/* Using 64 bit alignment since the spin table is accessed as data */
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.align 4
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.global secondary_boot_code
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/* Secondary Boot Code starts here */
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secondary_boot_code:
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.global __spin_table
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__spin_table:
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.space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
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.align 2
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ENTRY(secondary_boot_func)
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/*
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* MPIDR_EL1 Fields:
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* MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
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* MPIDR[7:2] = AFF0_RES
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* MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
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* MPIDR[23:16] = AFF2_CLUSTERID
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* MPIDR[24] = MT
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* MPIDR[29:25] = RES0
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* MPIDR[30] = U
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* MPIDR[31] = ME
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* MPIDR[39:32] = AFF3
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*
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* Linear Processor ID (LPID) calculation from MPIDR_EL1:
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* (We only use AFF0_CPUID and AFF1_CLUSTERID for now
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* until AFF2_CLUSTERID and AFF3 have non-zero values)
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*
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* LPID = MPIDR[15:8] | MPIDR[1:0]
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*/
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mrs x0, mpidr_el1
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ubfm x1, x0, #8, #15
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ubfm x2, x0, #0, #1
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orr x10, x2, x1, lsl #2 /* x10 has LPID */
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ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
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/*
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* offset of the spin table element for this core from start of spin
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* table (each elem is padded to 64 bytes)
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*/
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lsl x1, x10, #6
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ldr x0, =__spin_table
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/* physical address of this cpus spin table element */
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add x11, x1, x0
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ldr x0, =__real_cntfrq
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ldr x0, [x0]
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msr cntfrq_el0, x0 /* set with real frequency */
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str x9, [x11, #16] /* LPID */
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mov x4, #1
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str x4, [x11, #8] /* STATUS */
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dsb sy
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slave_cpu:
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wfe
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ldr x0, [x11]
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cbz x0, slave_cpu
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#ifndef CONFIG_ARMV8_SWITCH_TO_EL1
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mrs x1, sctlr_el2
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#else
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mrs x1, sctlr_el1
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#endif
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tbz x1, #25, cpu_is_le
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rev x0, x0 /* BE to LE conversion */
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cpu_is_le:
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ldr x5, [x11, #24]
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cbz x5, 1f
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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adr x4, secondary_switch_to_el1
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ldr x5, =ES_TO_AARCH64
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#else
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ldr x4, [x11]
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ldr x5, =ES_TO_AARCH32
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#endif
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bl secondary_switch_to_el2
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1:
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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adr x4, secondary_switch_to_el1
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#else
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ldr x4, [x11]
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#endif
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ldr x5, =ES_TO_AARCH64
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bl secondary_switch_to_el2
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ENDPROC(secondary_boot_func)
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ENTRY(secondary_switch_to_el2)
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switch_el x6, 1f, 0f, 0f
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0: ret
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1: armv8_switch_to_el2_m x4, x5, x6
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ENDPROC(secondary_switch_to_el2)
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ENTRY(secondary_switch_to_el1)
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mrs x0, mpidr_el1
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ubfm x1, x0, #8, #15
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ubfm x2, x0, #0, #1
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orr x10, x2, x1, lsl #2 /* x10 has LPID */
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lsl x1, x10, #6
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ldr x0, =__spin_table
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/* physical address of this cpus spin table element */
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add x11, x1, x0
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ldr x4, [x11]
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ldr x5, [x11, #24]
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cbz x5, 2f
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ldr x5, =ES_TO_AARCH32
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bl switch_to_el1
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2: ldr x5, =ES_TO_AARCH64
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switch_to_el1:
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switch_el x6, 0f, 1f, 0f
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0: ret
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1: armv8_switch_to_el1_m x4, x5, x6
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ENDPROC(secondary_switch_to_el1)
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/* Ensure that the literals used by the secondary boot code are
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* assembled within it (this is required so that we can protect
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* this area with a single memreserve region
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*/
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.ltorg
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/* 64 bit alignment for elements accessed as data */
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.align 4
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.global __real_cntfrq
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__real_cntfrq:
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.quad COUNTER_FREQUENCY
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.globl __secondary_boot_code_size
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.type __secondary_boot_code_size, %object
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/* Secondary Boot Code ends here */
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__secondary_boot_code_size:
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.quad .-secondary_boot_code
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#endif
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155
arch/arm/cpu/armv8/fsl-layerscape/spintable.S
Normal file
155
arch/arm/cpu/armv8/fsl-layerscape/spintable.S
Normal file
@ -0,0 +1,155 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2014-2015 Freescale Semiconductor
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* Copyright 2019 NXP
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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#include <asm/system.h>
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#include <asm/arch/mp.h>
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.align 3
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.global secondary_boot_addr
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secondary_boot_addr:
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.quad secondary_boot_func
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/* Keep literals not used by the secondary boot code outside it */
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.ltorg
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/* Using 64 bit alignment since the spin table is accessed as data */
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.align 4
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.global secondary_boot_code
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/* Secondary Boot Code starts here */
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secondary_boot_code:
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.global __spin_table
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__spin_table:
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.space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
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.align 2
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ENTRY(secondary_boot_func)
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/*
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* MPIDR_EL1 Fields:
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* MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
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* MPIDR[7:2] = AFF0_RES
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* MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
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* MPIDR[23:16] = AFF2_CLUSTERID
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* MPIDR[24] = MT
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* MPIDR[29:25] = RES0
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* MPIDR[30] = U
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* MPIDR[31] = ME
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* MPIDR[39:32] = AFF3
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*
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* Linear Processor ID (LPID) calculation from MPIDR_EL1:
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* (We only use AFF0_CPUID and AFF1_CLUSTERID for now
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* until AFF2_CLUSTERID and AFF3 have non-zero values)
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*
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* LPID = MPIDR[15:8] | MPIDR[1:0]
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*/
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mrs x0, mpidr_el1
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ubfm x1, x0, #8, #15
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ubfm x2, x0, #0, #1
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orr x10, x2, x1, lsl #2 /* x10 has LPID */
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ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
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/*
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* offset of the spin table element for this core from start of spin
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* table (each elem is padded to 64 bytes)
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*/
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lsl x1, x10, #6
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ldr x0, =__spin_table
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/* physical address of this cpus spin table element */
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add x11, x1, x0
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ldr x0, =__real_cntfrq
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ldr x0, [x0]
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msr cntfrq_el0, x0 /* set with real frequency */
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str x9, [x11, #16] /* LPID */
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mov x4, #1
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str x4, [x11, #8] /* STATUS */
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dsb sy
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slave_cpu:
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wfe
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ldr x0, [x11]
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cbz x0, slave_cpu
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#ifndef CONFIG_ARMV8_SWITCH_TO_EL1
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mrs x1, sctlr_el2
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#else
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mrs x1, sctlr_el1
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#endif
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tbz x1, #25, cpu_is_le
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rev x0, x0 /* BE to LE conversion */
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cpu_is_le:
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ldr x5, [x11, #24]
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cbz x5, 1f
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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adr x4, secondary_switch_to_el1
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ldr x5, =ES_TO_AARCH64
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#else
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ldr x4, [x11]
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ldr x5, =ES_TO_AARCH32
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#endif
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bl secondary_switch_to_el2
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1:
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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adr x4, secondary_switch_to_el1
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#else
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ldr x4, [x11]
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#endif
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ldr x5, =ES_TO_AARCH64
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bl secondary_switch_to_el2
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ENDPROC(secondary_boot_func)
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ENTRY(secondary_switch_to_el2)
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switch_el x6, 1f, 0f, 0f
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0: ret
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1: armv8_switch_to_el2_m x4, x5, x6
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ENDPROC(secondary_switch_to_el2)
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ENTRY(secondary_switch_to_el1)
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mrs x0, mpidr_el1
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ubfm x1, x0, #8, #15
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ubfm x2, x0, #0, #1
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orr x10, x2, x1, lsl #2 /* x10 has LPID */
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lsl x1, x10, #6
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ldr x0, =__spin_table
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/* physical address of this cpus spin table element */
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add x11, x1, x0
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ldr x4, [x11]
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ldr x5, [x11, #24]
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cbz x5, 2f
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ldr x5, =ES_TO_AARCH32
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bl switch_to_el1
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2: ldr x5, =ES_TO_AARCH64
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switch_to_el1:
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switch_el x6, 0f, 1f, 0f
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0: ret
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1: armv8_switch_to_el1_m x4, x5, x6
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ENDPROC(secondary_switch_to_el1)
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/* Ensure that the literals used by the secondary boot code are
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* assembled within it (this is required so that we can protect
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* this area with a single memreserve region
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*/
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.ltorg
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/* 64 bit alignment for elements accessed as data */
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.align 4
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.global __real_cntfrq
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__real_cntfrq:
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.quad COUNTER_FREQUENCY
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.globl __secondary_boot_code_size
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.type __secondary_boot_code_size, %object
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/* Secondary Boot Code ends here */
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__secondary_boot_code_size:
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.quad .-secondary_boot_code
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