leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'master' of /home/stefan/git/u-boot/u-boot

Browse Source
This commit is contained in:
Stefan Roese 2008-10-21 11:43:08 +02:00
commit f61f1e150c
2094 changed files with 57954 additions and 54028 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

116
CHANGELOG
View File

@ -1,3 +1,119 @@
commit f7a35a60cf45491871a5c28e9ad24db005487857
Author: Heiko Schocher <hs@denx.de>
Date: Fri Oct 17 18:24:06 2008 +0200
mgcoge: add redundant environment sector
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit c2537ee85954af9d036b18b644f3e18d837bf4a5
Author: Heiko Schocher <hs@denx.de>
Date: Fri Oct 17 18:23:27 2008 +0200
mgsuvd: update size of environment
Signed-off-by: Heiko Schocher <hs@denx.de>
commit fa7b1c07e9371aea8f87ee6d3c2ea5564bd8cc8d
Author: Lepcha Suchit <Suchit.Lepcha@freescale.com>
Date: Thu Oct 16 13:38:00 2008 -0500
83xx NAND boot: wait for LTESR[CC]
At least some revisions of the 8313, and possibly other chips, do not
wait for all pages of the initial 4K NAND region to be loaded before
beginning execution; thus, we wait for it before branching out of the
first NAND page.
This fixes warm reset problems when booting from NAND on 8313erdb.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
commit bf29e0ea0af03d593c64614136acc723a7a022a2
Author: Yuri Tikhonov <yur@emcraft.com>
Date: Fri Oct 17 12:54:18 2008 +0200
ppc4xx: PPC44x MQ initialization
Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
Previously the appropriate initialization had been made in Linux, by the
ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
registers after normal operation has begun is not supported and could
have unpredictable results.
Comment from Stefan: This patch doesn't change the resulting value of the
MQ registers. It explicitly sets/clears all bits to the desired state which
better documents the resulting register value instead of relying on pre-set
default values.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Stefan Roese <sr@denx.de>
commit f7d190b1c0b3ab7fc53074ad2862f7de99de37ff
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Thu Oct 16 21:58:50 2008 -0500
85xx: Using proper I2C source clock divider for MPC8544
The MPC8544 RM incorrect shows the SEC_CFG bit in PORDEVSR2 as being
bit 26, instead it should be bit 28. This caused in incorrect
interpretation of the i2c_clk which is the same as the SEC clk on
MPC8544. The SEC clk is controlled by cfg_sec_freq that is reported
in PORDEVSR2.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 42653b826adb319a1df06e24ef26096b2a5d9d2a
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Thu Oct 16 21:58:49 2008 -0500
Revert "85xx: Using proper I2C source clock divider for MPC8544"
This reverts commit dffd2446fb041f38ef034b0fcf41e51e5e489159.
The fix introduced by this patch is not correct. The problem is
that the documentation is not correct for the MPC8544 with regards
to which bit in PORDEVSR2 is for the SEC_CFG.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 2179c4766bffeece98e5e92040629a96c97e230c
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Wed Oct 15 10:19:41 2008 -0500
85xx: Fix compile warning
mpc8536ds.c: In function 'is_sata_supported':
mpc8536ds.c:614: warning: unused variable 'devdisr'
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 9029b68f3f81b3013044f167ea025e836e6c8c0e
Author: Jason Jin <Jason.jin@freescale.com>
Date: Wed Oct 15 10:40:24 2008 +0800
Fix the function conflict in x86emu when DEBUG is on
The function parse_line() in common/main.c was exposed globally by commit
6636b62a6efc7f14e6e788788631ae7a7fca4537, Result in conflict with the same
name funciton in drivers/bios_emulator/x86emu/debug.c when define the DEBUG.
This patch fix this by renaming the function in the debug.c file.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
commit b4dbacf69a669a17487054552fc2761149dd6767
Author: Wolfgang Denk <wd@denx.de>
Date: Wed Oct 15 15:50:45 2008 +0200
Coding Style cleanup, update CHANGELOG, prepare 2008.10-rc3
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 374b9038293d01d8744a46af9b7854a6fd99b228
Author: Heiko Schocher <hs@denx.de>
Date: Wed Oct 15 09:51:19 2008 +0200

60
Makefile
View File

@ -24,7 +24,7 @@
VERSION = 2008
PATCHLEVEL = 10
SUBLEVEL =
EXTRAVERSION = -rc3
EXTRAVERSION =
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
@ -243,9 +243,11 @@ endif
ifeq ($(CPU),mpc85xx)
LIBS += drivers/qe/qe.a
LIBS += cpu/mpc8xxx/ddr/libddr.a
TAG_SUBDIRS += cpu/mpc8xxx
endif
ifeq ($(CPU),mpc86xx)
LIBS += cpu/mpc8xxx/ddr/libddr.a
TAG_SUBDIRS += cpu/mpc8xxx
endif
LIBS += drivers/rtc/librtc.a
LIBS += drivers/serial/libserial.a
@ -922,7 +924,7 @@ MBX860T_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx mbx8xx
mgsuvd_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx mgsuvd
@$(MKCONFIG) $(@:_config=) ppc mpc8xx mgsuvd keymile
MHPC_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx mhpc eltec
@ -1701,12 +1703,12 @@ ISPAN_config \
ISPAN_REVB_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _REVB_,$@)" ] ; then \
echo "#define CFG_REV_B" > $(obj)include/config.h ; \
echo "#define CONFIG_SYS_REV_B" > $(obj)include/config.h ; \
fi
@$(MKCONFIG) -a ISPAN ppc mpc8260 ispan
mgcoge_config : unconfig
@$(MKCONFIG) mgcoge ppc mpc8260 mgcoge
@$(MKCONFIG) mgcoge ppc mpc8260 mgcoge keymile
MPC8260ADS_config \
MPC8260ADS_lowboot_config \
@ -1728,8 +1730,8 @@ PQ2FADS-ZU_66MHz_lowboot_config \
@mkdir -p $(obj)include
@mkdir -p $(obj)board/freescale/mpc8260ads
$(if $(findstring PQ2FADS,$@), \
@echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > $(obj)include/config.h, \
@echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h)
@echo "#define CONFIG_ADSTYPE CONFIG_SYS_PQ2FADS" > $(obj)include/config.h, \
@echo "#define CONFIG_ADSTYPE CONFIG_SYS_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h)
$(if $(findstring MHz,$@), \
@echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> $(obj)include/config.h, \
$(if $(findstring VR,$@), \
@ -1981,19 +1983,19 @@ M54451EVB_stmicro_config : unconfig
M54451EVB_stmicro_config) FLASH=STMICRO;; \
esac; \
if [ "$${FLASH}" = "SPANSION" ] ; then \
echo "#define CFG_SPANSION_BOOT" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_SPANSION_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \
cp $(obj)board/freescale/m54451evb/u-boot.spa $(obj)board/freescale/m54451evb/u-boot.lds ; \
$(XECHO) "... with SPANSION boot..." ; \
fi; \
if [ "$${FLASH}" = "STMICRO" ] ; then \
echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
echo "#define CFG_STMICRO_BOOT" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x47E00000" > $(obj)board/freescale/m54451evb/config.tmp ; \
cp $(obj)board/freescale/m54451evb/u-boot.stm $(obj)board/freescale/m54451evb/u-boot.lds ; \
$(XECHO) "... with ST Micro boot..." ; \
fi; \
echo "#define CFG_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ;
echo "#define CONFIG_SYS_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ;
@$(MKCONFIG) -a M54451EVB m68k mcf5445x m54451evb freescale
M54455EVB_config \
@ -2015,25 +2017,25 @@ M54455EVB_stm33_config : unconfig
M54455EVB_stm33_config) FLASH=STMICRO; FREQ=33333333;; \
esac; \
if [ "$${FLASH}" = "INTEL" ] ; then \
echo "#define CFG_INTEL_BOOT" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_INTEL_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \
$(XECHO) "... with INTEL boot..." ; \
fi; \
if [ "$${FLASH}" = "ATMEL" ] ; then \
echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \
$(XECHO) "... with ATMEL boot..." ; \
fi; \
if [ "$${FLASH}" = "STMICRO" ] ; then \
echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
echo "#define CFG_STMICRO_BOOT" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x4FE00000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.stm $(obj)board/freescale/m54455evb/u-boot.lds ; \
$(XECHO) "... with ST Micro boot..." ; \
fi; \
echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
$(XECHO) "... with $${FREQ}Hz input clock"
@$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale
@ -2053,20 +2055,20 @@ M5475GFE_config : unconfig
M5475FFE_config) BOOT=2;CODE=32;VID=1;USB=1;RAM=64;RAM1=64;; \
M5475GFE_config) BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
esac; \
echo "#define CFG_BUSCLK 133333333" > $(obj)include/config.h ; \
echo "#define CFG_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \
echo "#define CFG_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_BUSCLK 133333333" > $(obj)include/config.h ; \
echo "#define CONFIG_SYS_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \
if [ "$${RAM1}" != "0" ] ; then \
echo "#define CFG_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \
fi; \
if [ "$${CODE}" != "0" ] ; then \
echo "#define CFG_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \
fi; \
if [ "$${VID}" == "1" ] ; then \
echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_VIDEO" >> $(obj)include/config.h ; \
fi; \
if [ "$${USB}" == "1" ] ; then \
echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_USBCTRL" >> $(obj)include/config.h ; \
fi
@$(MKCONFIG) -a M5475EVB m68k mcf547x_8x m547xevb freescale
@ -2088,20 +2090,20 @@ M5485HFE_config : unconfig
M5485GFE_config) BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
M5485HFE_config) BOOT=2;CODE=16;VID=1;USB=0;RAM=64;RAM1=0;; \
esac; \
echo "#define CFG_BUSCLK 100000000" > $(obj)include/config.h ; \
echo "#define CFG_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \
echo "#define CFG_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_BUSCLK 100000000" > $(obj)include/config.h ; \
echo "#define CONFIG_SYS_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \
if [ "$${RAM1}" != "0" ] ; then \
echo "#define CFG_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \
fi; \
if [ "$${CODE}" != "0" ] ; then \
echo "#define CFG_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \
fi; \
if [ "$${VID}" == "1" ] ; then \
echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_VIDEO" >> $(obj)include/config.h ; \
fi; \
if [ "$${USB}" == "1" ] ; then \
echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_USBCTRL" >> $(obj)include/config.h ; \
fi
@$(MKCONFIG) -a M5485EVB m68k mcf547x_8x m548xevb freescale
@ -2120,11 +2122,11 @@ MPC8313ERDB_NAND_66_config: unconfig
@mkdir -p $(obj)board/freescale/mpc8313erdb
@if [ "$(findstring _33_,$@)" ] ; then \
$(XECHO) -n "...33M ..." ; \
echo "#define CFG_33MHZ" >>$(obj)include/config.h ; \
echo "#define CONFIG_SYS_33MHZ" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _66_,$@)" ] ; then \
$(XECHO) -n "...66M..." ; \
echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \
echo "#define CONFIG_SYS_66MHZ" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _NAND_,$@)" ] ; then \
$(XECHO) -n "...NAND..." ; \

398
README
View File

@ -210,7 +210,7 @@ There are two classes of configuration variables:
* Configuration _SETTINGS_:
These depend on the hardware etc. and should not be meddled with if
you don't know what you're doing; they have names beginning with
"CFG_".
"CONFIG_SYS_".
Later we will add a configuration tool - probably similar to or even
identical to what's used for the Linux kernel. Right now, we have to
@ -284,10 +284,10 @@ The following options need to be configured:
- Board flavour: (if CONFIG_MPC8260ADS is defined)
CONFIG_ADSTYPE
Possible values are:
CFG_8260ADS - original MPC8260ADS
CFG_8266ADS - MPC8266ADS
CFG_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR
CFG_8272ADS - MPC8272ADS
CONFIG_SYS_8260ADS - original MPC8260ADS
CONFIG_SYS_8266ADS - MPC8266ADS
CONFIG_SYS_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR
CONFIG_SYS_8272ADS - MPC8272ADS
- MPC824X Family Member (if CONFIG_MPC824X is defined)
Define exactly one of
@ -302,28 +302,28 @@ The following options need to be configured:
or XTAL/EXTAL)
- 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU):
CFG_8xx_CPUCLK_MIN
CFG_8xx_CPUCLK_MAX
CONFIG_SYS_8xx_CPUCLK_MIN
CONFIG_SYS_8xx_CPUCLK_MAX
CONFIG_8xx_CPUCLK_DEFAULT
See doc/README.MPC866
CFG_MEASURE_CPUCLK
CONFIG_SYS_MEASURE_CPUCLK
Define this to measure the actual CPU clock instead
of relying on the correctness of the configured
values. Mostly useful for board bringup to make sure
the PLL is locked at the intended frequency. Note
that this requires a (stable) reference clock (32 kHz
RTC clock or CFG_8XX_XIN)
RTC clock or CONFIG_SYS_8XX_XIN)
- Intel Monahans options:
CFG_MONAHANS_RUN_MODE_OSC_RATIO
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
Defines the Monahans run mode to oscillator
ratio. Valid values are 8, 16, 24, 31. The core
frequency is this value multiplied by 13 MHz.
CFG_MONAHANS_TURBO_RUN_MODE_RATIO
CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
Defines the Monahans turbo mode to oscillator
ratio. Valid values are 1 (default if undefined) and
@ -436,7 +436,7 @@ The following options need to be configured:
CONFIG_CONSOLE_CURSOR cursor drawing on/off
(requires blink timer
cf. i8042.c)
CFG_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c)
CONFIG_SYS_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c)
CONFIG_CONSOLE_TIME display time/date info in
upper right corner
(requires CONFIG_CMD_DATE)
@ -461,8 +461,8 @@ The following options need to be configured:
- Console Baudrate:
CONFIG_BAUDRATE - in bps
Select one of the baudrates listed in
CFG_BAUDRATE_TABLE, see below.
CFG_BRGCLK_PRESCALE, baudrate prescale
CONFIG_SYS_BAUDRATE_TABLE, see below.
CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale
- Interrupt driven serial port input:
CONFIG_SERIAL_SOFTWARE_FIFO
@ -546,7 +546,7 @@ The following options need to be configured:
- Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined)
CONFIG_KGDB_BAUDRATE
Select one of the baudrates listed in
CFG_BAUDRATE_TABLE, see below.
CONFIG_SYS_BAUDRATE_TABLE, see below.
- Monitor Functions:
Monitor commands can be included or excluded
@ -673,7 +673,7 @@ The following options need to be configured:
CONFIG_RTC_DS164x - use Dallas DS164x RTC
CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC
CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC
CFG_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337
CONFIG_SYS_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337
Note that if the RTC uses I2C, then the I2C interface
must also be configured. See I2C Support, below.
@ -687,7 +687,7 @@ The following options need to be configured:
- Partition Support:
CONFIG_MAC_PARTITION and/or CONFIG_DOS_PARTITION
and/or CONFIG_ISO_PARTITION
and/or CONFIG_ISO_PARTITION and/or CONFIG_EFI_PARTITION
If IDE or SCSI support is enabled (CONFIG_CMD_IDE or
CONFIG_CMD_SCSI) you must configure support for at
@ -711,11 +711,11 @@ The following options need to be configured:
CONFIG_LBA48
Set this to enable support for disks larger than 137GB
Also look at CFG_64BIT_LBA ,CFG_64BIT_VSPRINTF and CFG_64BIT_STRTOUL
Also look at CONFIG_SYS_64BIT_LBA ,CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
Whithout these , LBA48 support uses 32bit variables and will 'only'
support disks up to 2.1TB.
CFG_64BIT_LBA:
CONFIG_SYS_64BIT_LBA:
When enabled, makes the IDE subsystem use 64bit sector addresses.
Default is 32bit.
@ -724,12 +724,12 @@ The following options need to be configured:
SYM53C8XX SCSI controller; define
CONFIG_SCSI_SYM53C8XX to enable it.
CFG_SCSI_MAX_LUN [8], CFG_SCSI_MAX_SCSI_ID [7] and
CFG_SCSI_MAX_DEVICE [CFG_SCSI_MAX_SCSI_ID *
CFG_SCSI_MAX_LUN] can be adjusted to define the
CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and
CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID *
CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the
maximum numbers of LUNs, SCSI ID's and target
devices.
CFG_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
- NETWORK Support (PCI):
CONFIG_E1000
@ -811,7 +811,7 @@ The following options need to be configured:
CONFIG_USB_CONFIG
for differential drivers: 0x00001000
for single ended drivers: 0x00005000
CFG_USB_EVENT_POLL
CONFIG_SYS_USB_EVENT_POLL
May be defined to allow interrupt polling
instead of using asynchronous interrupts
@ -838,18 +838,18 @@ The following options need to be configured:
Define this to have a tty type of device available to
talk to the UDC device
CFG_CONSOLE_IS_IN_ENV
CONFIG_SYS_CONSOLE_IS_IN_ENV
Define this if you want stdin, stdout &/or stderr to
be set to usbtty.
mpc8xx:
CFG_USB_EXTC_CLK 0xBLAH
CONFIG_SYS_USB_EXTC_CLK 0xBLAH
Derive USB clock from external clock "blah"
- CFG_USB_EXTC_CLK 0x02
- CONFIG_SYS_USB_EXTC_CLK 0x02
CFG_USB_BRG_CLK 0xBLAH
CONFIG_SYS_USB_BRG_CLK 0xBLAH
Derive USB clock from brgclk
- CFG_USB_BRG_CLK 0x04
- CONFIG_SYS_USB_BRG_CLK 0x04
If you have a USB-IF assigned VendorID then you may wish to
define your own vendor specific values either in BoardName.h
@ -891,16 +891,16 @@ The following options need to be configured:
CONFIG_JFFS2_NAND_DEV
Define these for a default partition on a NAND device
CFG_JFFS2_FIRST_SECTOR,
CFG_JFFS2_FIRST_BANK, CFG_JFFS2_NUM_BANKS
CONFIG_SYS_JFFS2_FIRST_SECTOR,
CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
Define these for a default partition on a NOR device
CFG_JFFS_CUSTOM_PART
CONFIG_SYS_JFFS_CUSTOM_PART
Define this to create an own partition. You have to provide a
function struct part_info* jffs2_part_info(int part_num)
If you define only one JFFS2 partition you may also want to
#define CFG_JFFS_SINGLE_PART 1
#define CONFIG_SYS_JFFS_SINGLE_PART 1
to disable the command chpart. This is the default when you
have not defined a custom partition
@ -1014,7 +1014,7 @@ The following options need to be configured:
320x240. Black & white.
Normally display is black on white background; define
CFG_WHITE_ON_BLACK to get it inverted.
CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
- Splash Screen Support: CONFIG_SPLASH_SCREEN
@ -1041,7 +1041,7 @@ The following options need to be configured:
compressed images are supported.
NOTE: the bzip2 algorithm requires a lot of RAM, so
the malloc area (as defined by CFG_MALLOC_LEN) should
the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should
be at least 4MB.
CONFIG_LZMA
@ -1065,7 +1065,7 @@ The following options need to be configured:
Use the lzmainfo tool to determinate the lc and lp values and
then calculate the amount of needed dynamic memory (ensuring
the appropriate CFG_MALLOC_LEN value).
the appropriate CONFIG_SYS_MALLOC_LEN value).
- MII/PHY support:
CONFIG_PHY_ADDR
@ -1095,8 +1095,11 @@ The following options need to be configured:
- Ethernet address:
CONFIG_ETHADDR
CONFIG_ETH1ADDR
CONFIG_ETH2ADDR
CONFIG_ETH3ADDR
CONFIG_ETH4ADDR
CONFIG_ETH5ADDR
Define a default value for Ethernet address to use
for the respective Ethernet interface, in case this
@ -1279,15 +1282,15 @@ The following options need to be configured:
There are several other quantities that must also be
defined when you define CONFIG_HARD_I2C or CONFIG_SOFT_I2C.
In both cases you will need to define CFG_I2C_SPEED
In both cases you will need to define CONFIG_SYS_I2C_SPEED
to be the frequency (in Hz) at which you wish your i2c bus
to run and CFG_I2C_SLAVE to be the address of this node (ie
to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
the CPU's i2c node address).
Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c)
sets the CPU up as a master node and so its address should
therefore be cleared to 0 (See, eg, MPC823e User's Manual
p.16-473). So, set CFG_I2C_SLAVE to 0.
p.16-473). So, set CONFIG_SYS_I2C_SLAVE to 0.
That's all that's required for CONFIG_HARD_I2C.
@ -1358,7 +1361,7 @@ The following options need to be configured:
#define I2C_DELAY udelay(2)
CFG_I2C_INIT_BOARD
CONFIG_SYS_I2C_INIT_BOARD
When a board is reset during an i2c bus transfer
chips might think that the current transfer is still
@ -1382,7 +1385,7 @@ The following options need to be configured:
active. To switch to a different bus, use the 'i2c dev' command.
Note that bus numbering is zero-based.
CFG_I2C_NOPROBES
CONFIG_SYS_I2C_NOPROBES
This option specifies a list of I2C devices that will be skipped
when the 'i2c probe' command is issued (or 'iprobe' using the legacy
@ -1391,31 +1394,31 @@ The following options need to be configured:
e.g.
#undef CONFIG_I2C_MULTI_BUS
#define CFG_I2C_NOPROBES {0x50,0x68}
#define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
will skip addresses 0x50 and 0x68 on a board with one I2C bus
#define CONFIG_I2C_MULTI_BUS
#define CFG_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
#define CONFIG_SYS_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
CFG_SPD_BUS_NUM
CONFIG_SYS_SPD_BUS_NUM
If defined, then this indicates the I2C bus number for DDR SPD.
If not defined, then U-Boot assumes that SPD is on I2C bus 0.
CFG_RTC_BUS_NUM
CONFIG_SYS_RTC_BUS_NUM
If defined, then this indicates the I2C bus number for the RTC.
If not defined, then U-Boot assumes that RTC is on I2C bus 0.
CFG_DTT_BUS_NUM
CONFIG_SYS_DTT_BUS_NUM
If defined, then this indicates the I2C bus number for the DTT.
If not defined, then U-Boot assumes that DTT is on I2C bus 0.
CFG_I2C_DTT_ADDR:
CONFIG_SYS_I2C_DTT_ADDR:
If defined, specifies the I2C address of the DTT device.
If not defined, then U-Boot uses predefined value for
@ -1426,6 +1429,53 @@ The following options need to be configured:
Define this option if you want to use Freescale's I2C driver in
drivers/i2c/fsl_i2c.c.
CONFIG_I2C_MUX
Define this option if you have I2C devices reached over 1 .. n
I2C Muxes like the pca9544a. This option addes a new I2C
Command "i2c bus [muxtype:muxaddr:muxchannel]" which adds a
new I2C Bus to the existing I2C Busses. If you select the
new Bus with "i2c dev", u-bbot sends first the commandos for
the muxes to activate this new "bus".
CONFIG_I2C_MULTI_BUS must be also defined, to use this
feature!
Example:
Adding a new I2C Bus reached over 2 pca9544a muxes
The First mux with address 70 and channel 6
The Second mux with address 71 and channel 4
=> i2c bus pca9544a:70:6:pca9544a:71:4
Use the "i2c bus" command without parameter, to get a list
of I2C Busses with muxes:
=> i2c bus
Busses reached over muxes:
Bus ID: 2
reached over Mux(es):
pca9544a@70 ch: 4
Bus ID: 3
reached over Mux(es):
pca9544a@70 ch: 6
pca9544a@71 ch: 4
=>
If you now switch to the new I2C Bus 3 with "i2c dev 3"
u-boot sends First the Commando to the mux@70 to enable
channel 6, and then the Commando to the mux@71 to enable
the channel 4.
After that, you can use the "normal" i2c commands as
usual, to communicate with your I2C devices behind
the 2 muxes.
This option is actually implemented for the bitbanging
algorithm in common/soft_i2c.c and for the Hardware I2C
Bus on the MPC8260. But it should be not so difficult
to add this option to other architectures.
- SPI Support: CONFIG_SPI
@ -1479,11 +1529,11 @@ The following options need to be configured:
Specify the number of FPGA devices to support.
CFG_FPGA_PROG_FEEDBACK
CONFIG_SYS_FPGA_PROG_FEEDBACK
Enable printing of hash marks during FPGA configuration.
CFG_FPGA_CHECK_BUSY
CONFIG_SYS_FPGA_CHECK_BUSY
Enable checks on FPGA configuration interface busy
status by the configuration function. This option
@ -1495,29 +1545,29 @@ The following options need to be configured:
If defined, a function that provides delays in the FPGA
configuration driver.
CFG_FPGA_CHECK_CTRLC
CONFIG_SYS_FPGA_CHECK_CTRLC
Allow Control-C to interrupt FPGA configuration
CFG_FPGA_CHECK_ERROR
CONFIG_SYS_FPGA_CHECK_ERROR
Check for configuration errors during FPGA bitfile
loading. For example, abort during Virtex II
configuration if the INIT_B line goes low (which
indicated a CRC error).
CFG_FPGA_WAIT_INIT
CONFIG_SYS_FPGA_WAIT_INIT
Maximum time to wait for the INIT_B line to deassert
after PROB_B has been deasserted during a Virtex II
FPGA configuration sequence. The default time is 500
ms.
CFG_FPGA_WAIT_BUSY
CONFIG_SYS_FPGA_WAIT_BUSY
Maximum time to wait for BUSY to deassert during
Virtex II FPGA configuration. The default is 5 ms.
CFG_FPGA_WAIT_CONFIG
CONFIG_SYS_FPGA_WAIT_CONFIG
Time to wait after FPGA configuration. The default is
200 ms.
@ -1615,7 +1665,7 @@ The following options need to be configured:
for the "hush" shell.
CFG_HUSH_PARSER
CONFIG_SYS_HUSH_PARSER
Define this variable to enable the "hush" shell (from
Busybox) as command line interpreter, thus enabling
@ -1627,7 +1677,7 @@ The following options need to be configured:
with a somewhat smaller memory footprint.
CFG_PROMPT_HUSH_PS2
CONFIG_SYS_PROMPT_HUSH_PS2
This defines the secondary prompt string, which is
printed when the command interpreter needs more input
@ -1699,10 +1749,10 @@ The following options need to be configured:
Adding this option adds support for Xilinx SystemACE
chips attached via some sort of local bus. The address
of the chip must also be defined in the
CFG_SYSTEMACE_BASE macro. For example:
CONFIG_SYS_SYSTEMACE_BASE macro. For example:
#define CONFIG_SYSTEMACE
#define CFG_SYSTEMACE_BASE 0xf0000000
#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
When SystemACE support is added, the "ace" device type
becomes available to the fat commands, i.e. fatls.
@ -1737,6 +1787,14 @@ The following options need to be configured:
example, some LED's) on your board. At the moment,
the following checkpoints are implemented:
- Automatic software updates via TFTP server
CONFIG_UPDATE_TFTP
CONFIG_UPDATE_TFTP_CNT_MAX
CONFIG_UPDATE_TFTP_MSEC_MAX
These options enable and control the auto-update feature;
for a more detailed description refer to doc/README.update.
Legacy uImage format:
Arg Where When
@ -1942,53 +2000,53 @@ Modem Support:
Configuration Settings:
-----------------------
- CFG_LONGHELP: Defined when you want long help messages included;
- CONFIG_SYS_LONGHELP: Defined when you want long help messages included;
undefine this when you're short of memory.
- CFG_PROMPT: This is what U-Boot prints on the console to
- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
prompt for user input.
- CFG_CBSIZE: Buffer size for input from the Console
- CONFIG_SYS_CBSIZE: Buffer size for input from the Console
- CFG_PBSIZE: Buffer size for Console output
- CONFIG_SYS_PBSIZE: Buffer size for Console output
- CFG_MAXARGS: max. Number of arguments accepted for monitor commands
- CONFIG_SYS_MAXARGS: max. Number of arguments accepted for monitor commands
- CFG_BARGSIZE: Buffer size for Boot Arguments which are passed to
- CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to
the application (usually a Linux kernel) when it is
booted
- CFG_BAUDRATE_TABLE:
- CONFIG_SYS_BAUDRATE_TABLE:
List of legal baudrate settings for this board.
- CFG_CONSOLE_INFO_QUIET
- CONFIG_SYS_CONSOLE_INFO_QUIET
Suppress display of console information at boot.
- CFG_CONSOLE_IS_IN_ENV
- CONFIG_SYS_CONSOLE_IS_IN_ENV
If the board specific function
extern int overwrite_console (void);
returns 1, the stdin, stderr and stdout are switched to the
serial port, else the settings in the environment are used.
- CFG_CONSOLE_OVERWRITE_ROUTINE
- CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
Enable the call to overwrite_console().
- CFG_CONSOLE_ENV_OVERWRITE
- CONFIG_SYS_CONSOLE_ENV_OVERWRITE
Enable overwrite of previous console environment settings.
- CFG_MEMTEST_START, CFG_MEMTEST_END:
- CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END:
Begin and End addresses of the area used by the
simple memory test.
- CFG_ALT_MEMTEST:
- CONFIG_SYS_ALT_MEMTEST:
Enable an alternate, more extensive memory test.
- CFG_MEMTEST_SCRATCH:
- CONFIG_SYS_MEMTEST_SCRATCH:
Scratch address used by the alternate memory test
You only need to set this if address zero isn't writeable
- CFG_MEM_TOP_HIDE (PPC only):
If CFG_MEM_TOP_HIDE is defined in the board config header,
- CONFIG_SYS_MEM_TOP_HIDE (PPC only):
If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header,
this specified memory area will get subtracted from the top
(end) of RAM and won't get "touched" at all by U-Boot. By
fixing up gd->ram_size the Linux kernel should gets passed
@ -2008,75 +2066,75 @@ Configuration Settings:
non page size aligned address and this could cause major
problems.
- CFG_TFTP_LOADADDR:
- CONFIG_SYS_TFTP_LOADADDR:
Default load address for network file downloads
- CFG_LOADS_BAUD_CHANGE:
- CONFIG_SYS_LOADS_BAUD_CHANGE:
Enable temporary baudrate change while serial download
- CFG_SDRAM_BASE:
- CONFIG_SYS_SDRAM_BASE:
Physical start address of SDRAM. _Must_ be 0 here.
- CFG_MBIO_BASE:
- CONFIG_SYS_MBIO_BASE:
Physical start address of Motherboard I/O (if using a
Cogent motherboard)
- CFG_FLASH_BASE:
- CONFIG_SYS_FLASH_BASE:
Physical start address of Flash memory.
- CFG_MONITOR_BASE:
- CONFIG_SYS_MONITOR_BASE:
Physical start address of boot monitor code (set by
make config files to be same as the text base address
(TEXT_BASE) used when linking) - same as
CFG_FLASH_BASE when booting from flash.
CONFIG_SYS_FLASH_BASE when booting from flash.
- CFG_MONITOR_LEN:
- CONFIG_SYS_MONITOR_LEN:
Size of memory reserved for monitor code, used to
determine _at_compile_time_ (!) if the environment is
embedded within the U-Boot image, or in a separate
flash sector.
- CFG_MALLOC_LEN:
- CONFIG_SYS_MALLOC_LEN:
Size of DRAM reserved for malloc() use.
- CFG_BOOTM_LEN:
- CONFIG_SYS_BOOTM_LEN:
Normally compressed uImages are limited to an
uncompressed size of 8 MBytes. If this is not enough,
you can define CFG_BOOTM_LEN in your board config file
you can define CONFIG_SYS_BOOTM_LEN in your board config file
to adjust this setting to your needs.
- CFG_BOOTMAPSZ:
- CONFIG_SYS_BOOTMAPSZ:
Maximum size of memory mapped by the startup code of
the Linux kernel; all data that must be processed by
the Linux kernel (bd_info, boot arguments, FDT blob if
used) must be put below this limit, unless "bootm_low"
enviroment variable is defined and non-zero. In such case
all data for the Linux kernel must be between "bootm_low"
and "bootm_low" + CFG_BOOTMAPSZ.
and "bootm_low" + CONFIG_SYS_BOOTMAPSZ.
- CFG_MAX_FLASH_BANKS:
- CONFIG_SYS_MAX_FLASH_BANKS:
Max number of Flash memory banks
- CFG_MAX_FLASH_SECT:
- CONFIG_SYS_MAX_FLASH_SECT:
Max number of sectors on a Flash chip
- CFG_FLASH_ERASE_TOUT:
- CONFIG_SYS_FLASH_ERASE_TOUT:
Timeout for Flash erase operations (in ms)
- CFG_FLASH_WRITE_TOUT:
- CONFIG_SYS_FLASH_WRITE_TOUT:
Timeout for Flash write operations (in ms)
- CFG_FLASH_LOCK_TOUT
- CONFIG_SYS_FLASH_LOCK_TOUT
Timeout for Flash set sector lock bit operation (in ms)
- CFG_FLASH_UNLOCK_TOUT
- CONFIG_SYS_FLASH_UNLOCK_TOUT
Timeout for Flash clear lock bits operation (in ms)
- CFG_FLASH_PROTECTION
- CONFIG_SYS_FLASH_PROTECTION
If defined, hardware flash sectors protection is used
instead of U-Boot software protection.
- CFG_DIRECT_FLASH_TFTP:
- CONFIG_SYS_DIRECT_FLASH_TFTP:
Enable TFTP transfers directly to flash memory;
without this option such a download has to be
@ -2089,7 +2147,7 @@ Configuration Settings:
too limited to allow for a temporary copy of the
downloaded image) this option may be very useful.
- CFG_FLASH_CFI:
- CONFIG_SYS_FLASH_CFI:
Define if the flash driver uses extra elements in the
common flash structure for storing flash geometry.
@ -2097,14 +2155,14 @@ Configuration Settings:
This option also enables the building of the cfi_flash driver
in the drivers directory
- CFG_FLASH_USE_BUFFER_WRITE
- CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Use buffered writes to flash.
- CONFIG_FLASH_SPANSION_S29WS_N
s29ws-n MirrorBit flash has non-standard addresses for buffered
write commands.
- CFG_FLASH_QUIET_TEST
- CONFIG_SYS_FLASH_QUIET_TEST
If this option is defined, the common CFI flash doesn't
print it's warning upon not recognized FLASH banks. This
is useful, if some of the configured banks are only
@ -2115,7 +2173,7 @@ Configuration Settings:
digits and dots. Recommended value: 45 (9..1) for 80
column displays, 15 (3..1) for 40 column displays.
- CFG_RX_ETH_BUFFER:
- CONFIG_SYS_RX_ETH_BUFFER:
Defines the number of Ethernet receive buffers. On some
Ethernet controllers it is recommended to set this value
to 8 or even higher (EEPRO100 or 405 EMAC), since all
@ -2150,7 +2208,7 @@ following configurations:
type flash chips the second sector can be used: the offset
for this sector is given here.
CONFIG_ENV_OFFSET is used relative to CFG_FLASH_BASE.
CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE.
- CONFIG_ENV_ADDR:
@ -2233,24 +2291,24 @@ to save the current settings.
These two #defines specify the offset and size of the
environment area within the total memory of your EEPROM.
- CFG_I2C_EEPROM_ADDR:
- CONFIG_SYS_I2C_EEPROM_ADDR:
If defined, specified the chip address of the EEPROM device.
The default address is zero.
- CFG_EEPROM_PAGE_WRITE_BITS:
- CONFIG_SYS_EEPROM_PAGE_WRITE_BITS:
If defined, the number of bits used to address bytes in a
single page in the EEPROM device. A 64 byte page, for example
would require six bits.
- CFG_EEPROM_PAGE_WRITE_DELAY_MS:
- CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS:
If defined, the number of milliseconds to delay between
page writes. The default is zero milliseconds.
- CFG_I2C_EEPROM_ADDR_LEN:
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN:
The length in bytes of the EEPROM memory array address. Note
that this is NOT the chip address length!
- CFG_I2C_EEPROM_ADDR_OVERFLOW:
- CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW:
EEPROM chips that implement "address overflow" are ones
like Catalyst 24WC04/08/16 which has 9/10/11 bits of
address and the extra bits end up in the "chip address" bit
@ -2261,7 +2319,7 @@ to save the current settings.
still be one byte because the extra address bits are hidden
in the chip address.
- CFG_EEPROM_SIZE:
- CONFIG_SYS_EEPROM_SIZE:
The size in bytes of the EEPROM device.
@ -2300,7 +2358,7 @@ to save the current settings.
to a block boundary, and CONFIG_ENV_SIZE must be a multiple of
the NAND devices block size.
- CFG_SPI_INIT_OFFSET
- CONFIG_SYS_SPI_INIT_OFFSET
Defines offset to the initial SPI buffer area in DPRAM. The
area is used at an early stage (ROM part) if the environment
@ -2326,29 +2384,29 @@ Note: once the monitor has been relocated, then it will complain if
the default environment is used; a new CRC is computed as soon as you
use the "saveenv" command to store a valid environment.
- CFG_FAULT_ECHO_LINK_DOWN:
- CONFIG_SYS_FAULT_ECHO_LINK_DOWN:
Echo the inverted Ethernet link state to the fault LED.
Note: If this option is active, then CFG_FAULT_MII_ADDR
Note: If this option is active, then CONFIG_SYS_FAULT_MII_ADDR
also needs to be defined.
- CFG_FAULT_MII_ADDR:
- CONFIG_SYS_FAULT_MII_ADDR:
MII address of the PHY to check for the Ethernet link state.
- CFG_64BIT_VSPRINTF:
- CONFIG_SYS_64BIT_VSPRINTF:
Makes vsprintf (and all *printf functions) support printing
of 64bit values by using the L quantifier
- CFG_64BIT_STRTOUL:
- CONFIG_SYS_64BIT_STRTOUL:
Adds simple_strtoull that returns a 64bit value
Low Level (hardware related) configuration options:
---------------------------------------------------
- CFG_CACHELINE_SIZE:
- CONFIG_SYS_CACHELINE_SIZE:
Cache Line Size of the CPU.
- CFG_DEFAULT_IMMR:
- CONFIG_SYS_DEFAULT_IMMR:
Default address of the IMMR after system reset.
Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
@ -2356,36 +2414,36 @@ Low Level (hardware related) configuration options:
the IMMR register after a reset.
- Floppy Disk Support:
CFG_FDC_DRIVE_NUMBER
CONFIG_SYS_FDC_DRIVE_NUMBER
the default drive number (default value 0)
CFG_ISA_IO_STRIDE
CONFIG_SYS_ISA_IO_STRIDE
defines the spacing between FDC chipset registers
(default value 1)
CFG_ISA_IO_OFFSET
CONFIG_SYS_ISA_IO_OFFSET
defines the offset of register from address. It
depends on which part of the data bus is connected to
the FDC chipset. (default value 0)
If CFG_ISA_IO_STRIDE CFG_ISA_IO_OFFSET and
CFG_FDC_DRIVE_NUMBER are undefined, they take their
If CONFIG_SYS_ISA_IO_STRIDE CONFIG_SYS_ISA_IO_OFFSET and
CONFIG_SYS_FDC_DRIVE_NUMBER are undefined, they take their
default value.
if CFG_FDC_HW_INIT is defined, then the function
if CONFIG_SYS_FDC_HW_INIT is defined, then the function
fdc_hw_init() is called at the beginning of the FDC
setup. fdc_hw_init() must be provided by the board
source code. It is used to make hardware dependant
initializations.
- CFG_IMMR: Physical address of the Internal Memory.
- CONFIG_SYS_IMMR: Physical address of the Internal Memory.
DO NOT CHANGE unless you know exactly what you're
doing! (11-4) [MPC8xx/82xx systems only]
- CFG_INIT_RAM_ADDR:
- CONFIG_SYS_INIT_RAM_ADDR:
Start address of memory area that can be used for
initial data and stack; please note that this must be
@ -2400,91 +2458,91 @@ Low Level (hardware related) configuration options:
- MPC824X: data cache
- PPC4xx: data cache
- CFG_GBL_DATA_OFFSET:
- CONFIG_SYS_GBL_DATA_OFFSET:
Offset of the initial data structure in the memory
area defined by CFG_INIT_RAM_ADDR. Usually
CFG_GBL_DATA_OFFSET is chosen such that the initial
area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
data is located at the end of the available space
(sometimes written as (CFG_INIT_RAM_END -
CFG_INIT_DATA_SIZE), and the initial stack is just
below that area (growing from (CFG_INIT_RAM_ADDR +
CFG_GBL_DATA_OFFSET) downward.
(sometimes written as (CONFIG_SYS_INIT_RAM_END -
CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
CONFIG_SYS_GBL_DATA_OFFSET) downward.
Note:
On the MPC824X (or other systems that use the data
cache for initial memory) the address chosen for
CFG_INIT_RAM_ADDR is basically arbitrary - it must
CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
point to an otherwise UNUSED address space between
the top of RAM and the start of the PCI space.
- CFG_SIUMCR: SIU Module Configuration (11-6)
- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6)
- CFG_SYPCR: System Protection Control (11-9)
- CONFIG_SYS_SYPCR: System Protection Control (11-9)
- CFG_TBSCR: Time Base Status and Control (11-26)
- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26)
- CFG_PISCR: Periodic Interrupt Status and Control (11-31)
- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31)
- CFG_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30)
- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30)
- CFG_SCCR: System Clock and reset Control Register (15-27)
- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
- CFG_OR_TIMING_SDRAM:
- CONFIG_SYS_OR_TIMING_SDRAM:
SDRAM timing
- CFG_MAMR_PTA:
- CONFIG_SYS_MAMR_PTA:
periodic timer for refresh
- CFG_DER: Debug Event Register (37-47)
- CONFIG_SYS_DER: Debug Event Register (37-47)
- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CFG_REMAP_OR_AM,
CFG_PRELIM_OR_AM, CFG_OR_TIMING_FLASH, CFG_OR0_REMAP,
CFG_OR0_PRELIM, CFG_BR0_PRELIM, CFG_OR1_REMAP, CFG_OR1_PRELIM,
CFG_BR1_PRELIM:
- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
CONFIG_SYS_BR1_PRELIM:
Memory Controller Definitions: BR0/1 and OR0/1 (FLASH)
- SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE,
CFG_OR_TIMING_SDRAM, CFG_OR2_PRELIM, CFG_BR2_PRELIM,
CFG_OR3_PRELIM, CFG_BR3_PRELIM:
CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM,
CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
- CFG_MAMR_PTA, CFG_MPTPR_2BK_4K, CFG_MPTPR_1BK_4K, CFG_MPTPR_2BK_8K,
CFG_MPTPR_1BK_8K, CFG_MAMR_8COL, CFG_MAMR_9COL:
- CONFIG_SYS_MAMR_PTA, CONFIG_SYS_MPTPR_2BK_4K, CONFIG_SYS_MPTPR_1BK_4K, CONFIG_SYS_MPTPR_2BK_8K,
CONFIG_SYS_MPTPR_1BK_8K, CONFIG_SYS_MAMR_8COL, CONFIG_SYS_MAMR_9COL:
Machine Mode Register and Memory Periodic Timer
Prescaler definitions (SDRAM timing)
- CFG_I2C_UCODE_PATCH, CFG_I2C_DPMEM_OFFSET [0x1FC0]:
- CONFIG_SYS_I2C_UCODE_PATCH, CONFIG_SYS_I2C_DPMEM_OFFSET [0x1FC0]:
enable I2C microcode relocation patch (MPC8xx);
define relocation offset in DPRAM [DSP2]
- CFG_SMC_UCODE_PATCH, CFG_SMC_DPMEM_OFFSET [0x1FC0]:
- CONFIG_SYS_SMC_UCODE_PATCH, CONFIG_SYS_SMC_DPMEM_OFFSET [0x1FC0]:
enable SMC microcode relocation patch (MPC8xx);
define relocation offset in DPRAM [SMC1]
- CFG_SPI_UCODE_PATCH, CFG_SPI_DPMEM_OFFSET [0x1FC0]:
- CONFIG_SYS_SPI_UCODE_PATCH, CONFIG_SYS_SPI_DPMEM_OFFSET [0x1FC0]:
enable SPI microcode relocation patch (MPC8xx);
define relocation offset in DPRAM [SCC4]
- CFG_USE_OSCCLK:
- CONFIG_SYS_USE_OSCCLK:
Use OSCM clock mode on MBX8xx board. Be careful,
wrong setting might damage your board. Read
doc/README.MBX before setting this variable!
- CFG_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
- CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
Offset of the bootmode word in DPRAM used by post
(Power On Self Tests). This definition overrides
#define'd default value in commproc.h resp.
cpm_8260.h.
- CFG_PCI_SLV_MEM_LOCAL, CFG_PCI_SLV_MEM_BUS, CFG_PICMR0_MASK_ATTRIB,
CFG_PCI_MSTR0_LOCAL, CFG_PCIMSK0_MASK, CFG_PCI_MSTR1_LOCAL,
CFG_PCIMSK1_MASK, CFG_PCI_MSTR_MEM_LOCAL, CFG_PCI_MSTR_MEM_BUS,
CFG_CPU_PCI_MEM_START, CFG_PCI_MSTR_MEM_SIZE, CFG_POCMR0_MASK_ATTRIB,
CFG_PCI_MSTR_MEMIO_LOCAL, CFG_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START,
CFG_PCI_MSTR_MEMIO_SIZE, CFG_POCMR1_MASK_ATTRIB, CFG_PCI_MSTR_IO_LOCAL,
CFG_PCI_MSTR_IO_BUS, CFG_CPU_PCI_IO_START, CFG_PCI_MSTR_IO_SIZE,
CFG_POCMR2_MASK_ATTRIB: (MPC826x only)
- CONFIG_SYS_PCI_SLV_MEM_LOCAL, CONFIG_SYS_PCI_SLV_MEM_BUS, CONFIG_SYS_PICMR0_MASK_ATTRIB,
CONFIG_SYS_PCI_MSTR0_LOCAL, CONFIG_SYS_PCIMSK0_MASK, CONFIG_SYS_PCI_MSTR1_LOCAL,
CONFIG_SYS_PCIMSK1_MASK, CONFIG_SYS_PCI_MSTR_MEM_LOCAL, CONFIG_SYS_PCI_MSTR_MEM_BUS,
CONFIG_SYS_CPU_PCI_MEM_START, CONFIG_SYS_PCI_MSTR_MEM_SIZE, CONFIG_SYS_POCMR0_MASK_ATTRIB,
CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL, CONFIG_SYS_PCI_MSTR_MEMIO_BUS, CPU_PCI_MEMIO_START,
CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
- CONFIG_SPD_EEPROM
@ -2494,16 +2552,16 @@ Low Level (hardware related) configuration options:
SPD_EEPROM_ADDRESS
I2C address of the SPD EEPROM
- CFG_SPD_BUS_NUM
- CONFIG_SYS_SPD_BUS_NUM
If SPD EEPROM is on an I2C bus other than the first
one, specify here. Note that the value must resolve
to something your driver can deal with.
- CFG_83XX_DDR_USES_CS0
- CONFIG_SYS_83XX_DDR_USES_CS0
Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.
- CFG_83XX_DDR_USES_CS0
- CONFIG_SYS_83XX_DDR_USES_CS0
Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.
@ -2803,7 +2861,7 @@ Some configuration options can be set using Environment Variables:
for use by the bootm command. See also "bootm_size"
environment variable. Address defined by "bootm_low" is
also the base of the initial memory mapping for the Linux
kernel -- see the description of CFG_BOOTMAPSZ.
kernel -- see the description of CONFIG_SYS_BOOTMAPSZ.
bootm_size - Memory range available for image processing in the bootm
command can be restricted. This variable is given as
@ -2811,6 +2869,10 @@ Some configuration options can be set using Environment Variables:
allowed for use by the bootm command. See also "bootm_low"
environment variable.
updatefile - Location of the software update file on a TFTP server, used
by the automatic software update feature. Please refer to
documentation in doc/README.update for more details.
autoload - if set to "no" (any string beginning with 'n'),
"bootp" will just load perform a lookup of the
configuration from the BOOTP server, but not try to
@ -2847,7 +2909,7 @@ Some configuration options can be set using Environment Variables:
is usually what you want since it allows for
maximum initrd size. If for some reason you want to
make sure that the initrd image is loaded below the
CFG_BOOTMAPSZ limit, you can set this environment
CONFIG_SYS_BOOTMAPSZ limit, you can set this environment
variable to a value of "no" or "off" or "0".
Alternatively, you can set it to a maximum upper
address to use (U-Boot will still check that it
@ -3121,7 +3183,7 @@ Just make sure your machine specific header file (for instance
include/asm-ppc/tqm8xx.h) includes the same definition of the Board
Information structure as we define in include/asm-<arch>/u-boot.h,
and make sure that your definition of IMAP_ADDR uses the same value
as your U-Boot configuration in CFG_IMMR.
as your U-Boot configuration in CONFIG_SYS_IMMR.
Configuring the Linux kernel:
@ -3668,7 +3730,7 @@ locked as (mis-) used as memory, etc.
cause you grief during the initial boot! It is frequently not
used.
CFG_INIT_RAM_ADDR should be somewhere that won't interfere
CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
with your processor/board/system design. The default value
you will find in any recent u-boot distribution in
walnut.h should work for you. I'd set it to a value larger
@ -3765,7 +3827,7 @@ U-Boot is installed in the first 128 kB of the first Flash bank (on
TQM8xxL modules this is the range 0x40000000 ... 0x4001FFFF). After
booting and sizing and initializing DRAM, the code relocates itself
to the upper end of DRAM. Immediately below the U-Boot code some
memory is reserved for use by malloc() [see CFG_MALLOC_LEN
memory is reserved for use by malloc() [see CONFIG_SYS_MALLOC_LEN
configuration setting]. Below that, a structure with global Board
Info data is placed, followed by the stack (growing downward).

140
README.nios_CONFIG_SYS_NIOS_CPU Normal file
View File

@ -0,0 +1,140 @@
===============================================================================
C F G _ N I O S _ C P U _ * v s . N I O S S D K
===============================================================================
When ever you have to make a new NIOS CPU configuration you can use this table
as a reference list to the original NIOS SDK symbols made by Alteras SOPC
Builder. Look into excalibur.h and excalibur.s in your SDK path cpu_sdk/inc.
Symbols beginning with a '[ptf]:' are coming from your SOPC sytem description
(PTF file) in sections WIZARD_SCRIPT_ARGUMENTS or SYSTEM_BUILDER_INFO.
C O R E N I O S S D K [1],[7]
-------------------------------------------------------------------------------
CONFIG_SYS_NIOS_CPU_CLK nasys_clock_freq
CONFIG_SYS_NIOS_CPU_ICACHE nasys_icache_size
CONFIG_SYS_NIOS_CPU_DCACHE nasys_dcache_size
CONFIG_SYS_NIOS_CPU_REG_NUMS nasys_nios_num_regs
CONFIG_SYS_NIOS_CPU_MUL __nios_use_multiply__
CONFIG_SYS_NIOS_CPU_MSTEP __nios_use_mstep__
CONFIG_SYS_NIOS_CPU_STACK nasys_stack_top
CONFIG_SYS_NIOS_CPU_VEC_BASE nasys_vector_table
CONFIG_SYS_NIOS_CPU_VEC_SIZE nasys_vector_table_size
CONFIG_SYS_NIOS_CPU_VEC_NUMS
CONFIG_SYS_NIOS_CPU_RST_VECT nasys_reset_address
CONFIG_SYS_NIOS_CPU_DBG_CORE nasys_debug_core
CONFIG_SYS_NIOS_CPU_RAM_BASE na_onchip_ram_64_kbytes
CONFIG_SYS_NIOS_CPU_RAM_SIZE na_onchip_ram_64_kbytes_size
CONFIG_SYS_NIOS_CPU_ROM_BASE na_boot_monitor_rom
CONFIG_SYS_NIOS_CPU_ROM_SIZE na_boot_monitor_rom_size
CONFIG_SYS_NIOS_CPU_OCI_BASE nasys_oci_core
CONFIG_SYS_NIOS_CPU_OCI_SIZE
CONFIG_SYS_NIOS_CPU_SRAM_BASE na_ext_ram nasys_program_mem
nasys_data_mem
CONFIG_SYS_NIOS_CPU_SRAM_SIZE na_ext_ram_size nasys_program_mem_size
nasys_data_mem_size
CONFIG_SYS_NIOS_CPU_SDRAM_BASE na_sdram
CONFIG_SYS_NIOS_CPU_SDRAM_SIZE na_sdram_size
CONFIG_SYS_NIOS_CPU_FLASH_BASE na_ext_flash nasys_main_flash
nasys_am29lv065d_flash_0
nasys_flash_0
CONFIG_SYS_NIOS_CPU_FLASH_SIZE na_ext_flash_size nasys_main_flash_size
T I M E R N I O S S D K [3]
-------------------------------------------------------------------------------
CONFIG_SYS_NIOS_CPU_TIMER_NUMS nasys_timer_count
CONFIG_SYS_NIOS_CPU_TIMER[0-9] nasys_timer_[0-9]
CONFIG_SYS_NIOS_CPU_TIMER[0-9]_IRQ nasys_timer_[0-9]_irq
CONFIG_SYS_NIOS_CPU_TIMER[0-9]_PER [ptf]:period
[ptf]:period_units
[ptf]:mult
CONFIG_SYS_NIOS_CPU_TIMER[0-9]_AR [ptf]:always_run
CONFIG_SYS_NIOS_CPU_TIMER[0-9]_FP [ptf]:fixed_period
CONFIG_SYS_NIOS_CPU_TIMER[0-9]_SS [ptf]:snapshot
U A R T N I O S S D K [2]
-------------------------------------------------------------------------------
CONFIG_SYS_NIOS_CPU_UART_NUMS nasys_uart_count
CONFIG_SYS_NIOS_CPU_UART[0-9] nasys_uart_[0-9]
CONFIG_SYS_NIOS_CPU_UART[0-9]_IRQ nasys_uart_[0-9]_irq
CONFIG_SYS_NIOS_CPU_UART[0-9]_BR [ptf]:baud
CONFIG_SYS_NIOS_CPU_UART[0-9]_DB [ptf]:data_bits
CONFIG_SYS_NIOS_CPU_UART[0-9]_SB [ptf]:stop_bits
CONFIG_SYS_NIOS_CPU_UART[0-9]_PA [ptf]:parity
CONFIG_SYS_NIOS_CPU_UART[0-9]_HS [ptf]:use_cts_rts
CONFIG_SYS_NIOS_CPU_UART[0-9]_EOP [ptf]:use_eop_register
P I O N I O S S D K [4]
-------------------------------------------------------------------------------
CONFIG_SYS_NIOS_CPU_PIO_NUMS nasys_pio_count
CONFIG_SYS_NIOS_CPU_PIO[0-9] nasys_pio_[0-9]
CONFIG_SYS_NIOS_CPU_PIO[0-9]_IRQ nasys_pio_[0-9]_irq
CONFIG_SYS_NIOS_CPU_PIO[0-9]_BITS [ptf]:Data_Width
CONFIG_SYS_NIOS_CPU_PIO[0-9]_TYPE [ptf]:has_tri
[ptf]:has_out
[ptf]:has_in
CONFIG_SYS_NIOS_CPU_PIO[0-9]_CAP [ptf]:capture
CONFIG_SYS_NIOS_CPU_PIO[0-9]_EDGE [ptf]:edge_type
CONFIG_SYS_NIOS_CPU_PIO[0-9]_ITYPE [ptf]:irq_type
S P I N I O S S D K [6]
-------------------------------------------------------------------------------
CONFIG_SYS_NIOS_CPU_SPI_NUMS nasys_spi_count
CONFIG_SYS_NIOS_CPU_SPI[0-9] nasys_spi_[0-9]
CONFIG_SYS_NIOS_CPU_SPI[0-9]_IRQ nasys_spi_[0-9]_irq
CONFIG_SYS_NIOS_CPU_SPI[0-9]_BITS [ptf]:databits
CONFIG_SYS_NIOS_CPU_SPI[0-9]_MA [ptf]:ismaster
CONFIG_SYS_NIOS_CPU_SPI[0-9]_SLN [ptf]:numslaves
CONFIG_SYS_NIOS_CPU_SPI[0-9]_TCLK [ptf]:targetclock
CONFIG_SYS_NIOS_CPU_SPI[0-9]_TDELAY [ptf]:targetdelay
CONFIG_SYS_NIOS_CPU_SPI[0-9]_* [ptf]:*
I D E N I O S S D K
-------------------------------------------------------------------------------
CONFIG_SYS_NIOS_CPU_IDE_NUMS nasys_usersocket_count
CONFIG_SYS_NIOS_CPU_IDE[0-9] nasys_usersocket_[0-9]
A S M I N I O S S D K [5]
-------------------------------------------------------------------------------
CONFIG_SYS_NIOS_CPU_ASMI_NUMS nasys_asmi_count
CONFIG_SYS_NIOS_CPU_ASMI[0-9] nasys_asmi_[0-9]
CONFIG_SYS_NIOS_CPU_ASMI[0-9]_IRQ nasys_asmi_[0-9]_irq
E t h e r n e t ( L A N ) N I O S S D K
-------------------------------------------------------------------------------
CONFIG_SYS_NIOS_CPU_LAN_NUMS
CONFIG_SYS_NIOS_CPU_LAN[0-9]_BASE na_lan91c111
CONFIG_SYS_NIOS_CPU_LAN[0-9]_OFFS LAN91C111_REGISTERS_OFFSET
CONFIG_SYS_NIOS_CPU_LAN[0-9]_IRQ na_lan91c111_irq
CONFIG_SYS_NIOS_CPU_LAN[0-9]_BUSW LAN91C111_DATA_BUS_WIDTH
CONFIG_SYS_NIOS_CPU_LAN[0-9]_TYPE
s y s t e m c o m p o s i n g N I O S S D K
-------------------------------------------------------------------------------
CONFIG_SYS_NIOS_CPU_TICK_TIMER (na_low_priority_timer2)
CONFIG_SYS_NIOS_CPU_USER_TIMER (na_timer1)
CONFIG_SYS_NIOS_CPU_BUTTON_PIO (na_button_pio)
CONFIG_SYS_NIOS_CPU_LCD_PIO (na_lcd_pio)
CONFIG_SYS_NIOS_CPU_LED_PIO (na_led_pio)
CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO (na_seven_seg_pio)
CONFIG_SYS_NIOS_CPU_RECONF_PIO (na_reconfig_request_pio)
CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO (na_cf_present_pio)
CONFIG_SYS_NIOS_CPU_CFPOWER_PIO (na_cf_power_pio)
CONFIG_SYS_NIOS_CPU_CFATASEL_PIO (na_cf_ata_select_pio)
CONFIG_SYS_NIOS_CPU_USER_SPI (na_spi)
===============================================================================
R E F E R E N C E S
===============================================================================
[1] http://www.altera.com/literature/ds/ds_nioscpu.pdf
[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
[5] http://www.altera.com/literature/ds/ds_nios_asmi.pdf
[6] http://www.altera.com/literature/ds/ds_nios_spi.pdf
[7] http://www.altera.com/literature/ds/ds_legacy_sdram_ctrl.pdf
===============================================================================
Stephan Linz <linz@li-pro.net>

8
api/api_storage.c
View File

@ -67,28 +67,28 @@ static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, };
void dev_stor_init(void)
{
#if defined(CONFIG_CMD_IDE)
specs[ENUM_IDE].max_dev = CFG_IDE_MAXDEVICE;
specs[ENUM_IDE].max_dev = CONFIG_SYS_IDE_MAXDEVICE;
specs[ENUM_IDE].enum_started = 0;
specs[ENUM_IDE].enum_ended = 0;
specs[ENUM_IDE].type = DEV_TYP_STOR | DT_STOR_IDE;
specs[ENUM_IDE].name = "ide";
#endif
#if defined(CONFIG_CMD_MMC)
specs[ENUM_MMC].max_dev = CFG_MMC_MAX_DEVICE;
specs[ENUM_MMC].max_dev = CONFIG_SYS_MMC_MAX_DEVICE;
specs[ENUM_MMC].enum_started = 0;
specs[ENUM_MMC].enum_ended = 0;
specs[ENUM_MMC].type = DEV_TYP_STOR | DT_STOR_MMC;
specs[ENUM_MMC].name = "mmc";
#endif
#if defined(CONFIG_CMD_SATA)
specs[ENUM_SATA].max_dev = CFG_SATA_MAX_DEVICE;
specs[ENUM_SATA].max_dev = CONFIG_SYS_SATA_MAX_DEVICE;
specs[ENUM_SATA].enum_started = 0;
specs[ENUM_SATA].enum_ended = 0;
specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
specs[ENUM_SATA].name = "sata";
#endif
#if defined(CONFIG_CMD_SCSI)
specs[ENUM_SCSI].max_dev = CFG_SCSI_MAX_DEVICE;
specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;
specs[ENUM_SCSI].enum_started = 0;
specs[ENUM_SCSI].enum_ended = 0;
specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;

2
board/AtmarkTechno/suzaku/flash.c
View File

@ -24,7 +24,7 @@
#include <common.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
unsigned long flash_init(void)
{

30
board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
View File

@ -32,7 +32,7 @@
int checkboard (void)
{
puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
#if (TEXT_BASE == CFG_INT_FLASH_BASE)
#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
puts (" Boot from Internal FLASH\n");
#endif
@ -45,10 +45,10 @@ phys_size_t initdram (int board_type)
size = 0;
MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6
| MCFSDRAMC_DCR_RC ((15 * CFG_CLK) >> 4);
#ifdef CFG_SDRAM_BASE0
| MCFSDRAMC_DCR_RC ((15 * CONFIG_SYS_CLK) >> 4);
#ifdef CONFIG_SYS_SDRAM_BASE0
MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE0)
MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE0)
| MCFSDRAMC_DACR_CASL (1)
| MCFSDRAMC_DACR_CBM (3)
| MCFSDRAMC_DACR_PS_16;
@ -57,17 +57,17 @@ phys_size_t initdram (int board_type)
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
*(unsigned short *) (CFG_SDRAM_BASE0) = 0xA5A5;
*(unsigned short *) (CONFIG_SYS_SDRAM_BASE0) = 0xA5A5;
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
for (i = 0; i < 2000; i++)
asm (" nop");
mbar_writeLong (MCFSDRAMC_DACR0,
mbar_readLong (MCFSDRAMC_DACR0) | MCFSDRAMC_DACR_IMRS);
*(unsigned int *) (CFG_SDRAM_BASE0 + 0x220) = 0xA5A5;
size += CFG_SDRAM_SIZE * 1024 * 1024;
*(unsigned int *) (CONFIG_SYS_SDRAM_BASE0 + 0x220) = 0xA5A5;
size += CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
#ifdef CFG_SDRAM_BASE1
MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE1)
#ifdef CONFIG_SYS_SDRAM_BASE1
MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
| MCFSDRAMC_DACR_CASL (1)
| MCFSDRAMC_DACR_CBM (3)
| MCFSDRAMC_DACR_PS_16;
@ -76,25 +76,25 @@ phys_size_t initdram (int board_type)
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
*(unsigned short *) (CFG_SDRAM_BASE1) = 0xA5A5;
*(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
for (i = 0; i < 2000; i++)
asm (" nop");
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
*(unsigned int *) (CFG_SDRAM_BASE1 + 0x220) = 0xA5A5;
size += CFG_SDRAM_SIZE1 * 1024 * 1024;
*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
#endif
return size;
}
#if defined(CFG_DRAM_TEST)
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");

2
board/BuS/EB+MCF-EV123/VCxK.c
View File

@ -25,7 +25,7 @@
#include <asm/m5282.h>
#include "VCxK.h"
vu_char *vcxk_bws = (vu_char *)(CFG_CS3_BASE);
vu_char *vcxk_bws = (vu_char *)(CONFIG_SYS_CS3_BASE);
#define VCXK_BWS vcxk_bws
static ulong vcxk_driver;

16
board/BuS/EB+MCF-EV123/cfm_flash.c
View File

@ -28,14 +28,14 @@
#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
#if (CFG_CLK>20000000)
#define CFM_CLK (((long) CFG_CLK / (400000 * 8) + 1) | 0x40)
#if (CONFIG_SYS_CLK>20000000)
#define CFM_CLK (((long) CONFIG_SYS_CLK / (400000 * 8) + 1) | 0x40)
#else
#define CFM_CLK ((long) CFG_CLK / 400000 + 1)
#define CFM_CLK ((long) CONFIG_SYS_CLK / 400000 + 1)
#endif
#define cmf_backdoor_address(addr) (((addr) & 0x0007FFFF) | 0x04000000 | \
(CFG_MBAR & 0xC0000000))
(CONFIG_SYS_MBAR & 0xC0000000))
void cfm_flash_print_info (flash_info_t * info)
{
@ -60,8 +60,8 @@ void cfm_flash_init (flash_info_t * info)
MCFCFM_MCR = 0;
MCFCFM_CLKD = CFM_CLK;
debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\
CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
CFG_CLK);
CONFIG_SYS_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
CONFIG_SYS_CLK);
MCFCFM_SACC = 0;
MCFCFM_DACC = 0;
@ -86,7 +86,7 @@ void cfm_flash_init (flash_info_t * info)
{
if (sector == 0)
{
info->start[sector] = CFG_INT_FLASH_BASE;
info->start[sector] = CONFIG_SYS_INT_FLASH_BASE;
}
else
{
@ -187,7 +187,7 @@ int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cn
return rc;
}
#ifdef CFG_FLASH_PROTECTION
#ifdef CONFIG_SYS_FLASH_PROTECTION
int cfm_flash_protect(flash_info_t * info,long sector,int prot)
{

2
board/BuS/EB+MCF-EV123/cfm_flash.h
View File

@ -33,7 +33,7 @@ extern void cfm_flash_print_info (flash_info_t * info);
extern int cfm_flash_erase_sector (flash_info_t * info, int sector);
extern void cfm_flash_init (flash_info_t * info);
extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
#ifdef CFG_FLASH_PROTECTION
#ifdef CONFIG_SYS_FLASH_PROTECTION
extern int cfm_flash_protect(flash_info_t * info,long sector,int prot);
#endif

20
board/BuS/EB+MCF-EV123/flash.c
View File

@ -27,10 +27,10 @@
#include <common.h>
#include "cfm_flash.h"
#define PHYS_FLASH_1 CFG_FLASH_BASE
#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
#define FLASH_BANK_SIZE 0x200000
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
void flash_print_info (flash_info_t * info)
{
@ -83,7 +83,7 @@ unsigned long flash_init (void)
int i, j;
ulong size = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
switch (i)
@ -93,8 +93,8 @@ unsigned long flash_init (void)
(AMD_MANUFACT & FLASH_VENDMASK) |
(AMD_ID_LV160B & FLASH_TYPEMASK);
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
flashbase = PHYS_FLASH_1;
for (j = 0; j < flash_info[i].sector_count; j++) {
if (j == 0) {
@ -128,8 +128,8 @@ unsigned long flash_init (void)
}
flash_protect (FLAG_PROTECT_SET,
CFG_FLASH_BASE,
CFG_FLASH_BASE + 0xffff, &flash_info[0]);
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + 0xffff, &flash_info[0]);
return size;
}
@ -177,7 +177,7 @@ int amd_flash_erase_sector(flash_info_t * info, int sector)
result = *addr;
/* check timeout */
if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
state = ERR_TIMOUT;
}
@ -303,7 +303,7 @@ volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data)
result = *addr;
/* check timeout */
if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
state = ERR_TIMOUT;
}
if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK)))
@ -390,7 +390,7 @@ int amd_flash_protect(flash_info_t * info,long sector,int prot)
return rc;
}
#ifdef CFG_FLASH_PROTECTION
#ifdef CONFIG_SYS_FLASH_PROTECTION
int flash_real_protect(flash_info_t * info,long sector,int prot)
{

12
board/BuS/EB+MCF-EV123/mii.c
View File

@ -38,15 +38,15 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
{
if (setclear) {
MCFGPIO_PASPAR |= 0x0F00;
MCFGPIO_PEHLPAR = CFG_PEHLPAR;
MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
} else {
MCFGPIO_PASPAR &= 0xF0FF;
MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR;
MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
}
return 0;
}
#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
@ -132,9 +132,9 @@ uint mii_send(uint mii_cmd)
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
#if defined(CFG_DISCOVER_PHY)
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@ -199,7 +199,7 @@ int mii_discover_phy(struct eth_device *dev)
return phyaddr;
}
#endif /* CFG_DISCOVER_PHY */
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));

52
board/LEOX/elpt860/elpt860.c
View File

@ -138,23 +138,23 @@ const uint sdram_table[] = {
/* ------------------------------------------------------------------------- */
#define CFG_PC4 0x0800
#define CONFIG_SYS_PC4 0x0800
#define CFG_DS1 CFG_PC4
#define CONFIG_SYS_DS1 CONFIG_SYS_PC4
/*
* Very early board init code (fpga boot, etc.)
*/
int board_early_init_f (void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
/*
* Light up the red led on ELPT860 pcb (DS1) (PCDAT)
*/
immr->im_ioport.iop_pcdat &= ~CFG_DS1; /* PCDAT (DS1 = 0) */
immr->im_ioport.iop_pcpar &= ~CFG_DS1; /* PCPAR (0=general purpose I/O) */
immr->im_ioport.iop_pcdir |= CFG_DS1; /* PCDIR (I/O: 0=input, 1=output) */
immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1; /* PCDAT (DS1 = 0) */
immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1; /* PCPAR (0=general purpose I/O) */
immr->im_ioport.iop_pcdir |= CONFIG_SYS_DS1; /* PCDIR (I/O: 0=input, 1=output) */
return (0); /* success */
}
@ -181,7 +181,7 @@ int checkboard (void)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size8, size9;
long int size_b0 = 0;
@ -207,7 +207,7 @@ phys_size_t initdram (int board_type)
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
/*
* The following value is used as an address (i.e. opcode) for
@ -229,10 +229,10 @@ phys_size_t initdram (int board_type)
* preliminary addresses - these have to be modified after the
* SDRAM size has been determined.
*/
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay (200);
@ -252,7 +252,7 @@ phys_size_t initdram (int board_type)
*
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL,
size8 = dram_size (CONFIG_SYS_MAMR_8COL,
SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);
@ -260,7 +260,7 @@ phys_size_t initdram (int board_type)
/*
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL,
size9 = dram_size (CONFIG_SYS_MAMR_9COL,
SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
@ -269,7 +269,7 @@ phys_size_t initdram (int board_type)
} else { /* back to 8 columns */
size_b0 = size8;
memctl->memc_mamr = CFG_MAMR_8COL;
memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
udelay (500);
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
}
@ -282,22 +282,22 @@ phys_size_t initdram (int board_type)
*/
if (size_b0 < 0x02000000) {
/* reduce to 15.6 us (62.4 us / quad) */
memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
udelay (1000);
}
/*
* Final mapping: map bigger bank first
*/
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
{
unsigned long reg;
/* adjust refresh rate depending on SDRAM type, one bank */
reg = memctl->memc_mptpr;
reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
memctl->memc_mptpr = reg;
}
@ -319,7 +319,7 @@ phys_size_t initdram (int board_type)
static long int
dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_mamr = mamr_value;
@ -329,20 +329,20 @@ dram_size (long int mamr_value, long int *base, long int maxsize)
/* ------------------------------------------------------------------------- */
#define CFG_PA1 0x4000
#define CFG_PA2 0x2000
#define CONFIG_SYS_PA1 0x4000
#define CONFIG_SYS_PA2 0x2000
#define CFG_LBKs (CFG_PA2 | CFG_PA1)
#define CONFIG_SYS_LBKs (CONFIG_SYS_PA2 | CONFIG_SYS_PA1)
void reset_phy (void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
/*
* Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
* and no AUI loopback
*/
immr->im_ioport.iop_padat &= ~CFG_LBKs; /* PADAT (LBK eth 1&2 = 0) */
immr->im_ioport.iop_papar &= ~CFG_LBKs; /* PAPAR (0=general purpose I/O) */
immr->im_ioport.iop_padir |= CFG_LBKs; /* PADIR (I/O: 0=input, 1=output) */
immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs; /* PADAT (LBK eth 1&2 = 0) */
immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs; /* PAPAR (0=general purpose I/O) */
immr->im_ioport.iop_padir |= CONFIG_SYS_LBKs; /* PADIR (I/O: 0=input, 1=output) */
}

30
board/LEOX/elpt860/flash.c
View File

@ -33,7 +33,7 @@
/*
** Note 1: In this file, you have to provide the following variable:
** ------
** flash_info_t flash_info[CFG_MAX_FLASH_BANKS]
** flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]
** 'flash_info_t' structure is defined into 'include/flash.h'
** and defined as extern into 'common/cmd_flash.c'
**
@ -62,10 +62,10 @@
#ifndef CONFIG_ENV_ADDR
# define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#endif
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Internal Functions
@ -82,13 +82,13 @@ static int write_byte (flash_info_t *info, ulong dest, uchar data);
unsigned long
flash_init (void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size_b0;
int i;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
{
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@ -105,20 +105,20 @@ flash_init (void)
}
/* Remap FLASH according to real size */
memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V;
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V;
/* Re-do sizing to get full correct info */
size_b0 = flash_get_size ((volatile unsigned char *)CFG_FLASH_BASE,
size_b0 = flash_get_size ((volatile unsigned char *)CONFIG_SYS_FLASH_BASE,
&flash_info[0]);
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len-1,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + monitor_flash_len-1,
&flash_info[0]);
#endif
@ -383,7 +383,7 @@ flash_erase (flash_info_t *info,
addr = (volatile unsigned char *)(info->start[l_sect]);
while ( (addr[0] & 0x80) != 0x80 )
{
if ( (now = get_timer(start)) > CFG_FLASH_ERASE_TOUT )
if ( (now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT )
{
printf ("Timeout\n");
return ( 1 );
@ -556,7 +556,7 @@ write_word (flash_info_t *info,
start = get_timer (0);
while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) )
{
if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT )
{
return (1);
}
@ -602,7 +602,7 @@ write_byte (flash_info_t *info,
start = get_timer (0);
while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) )
{
if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT )
{
return (1);
}

2
board/MAI/AmigaOneG3SE/cmd_boota.c
View File

@ -27,7 +27,7 @@ struct bootcode_block bblk;
int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
unsigned char *load_address = (unsigned char *) CFG_LOAD_ADDR;
unsigned char *load_address = (unsigned char *) CONFIG_SYS_LOAD_ADDR;
unsigned char *base_address;
unsigned long offset;

4
board/MAI/AmigaOneG3SE/flash.c
View File

@ -1,14 +1,14 @@
#include <common.h>
#include <flash.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
unsigned long flash_init(void)
{
int i;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
{
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = 0;

30
board/MAI/AmigaOneG3SE/flash_new.c
View File

@ -39,7 +39,7 @@
#endif
/*---------------------------------------------------------------------*/
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
static ulong flash_get_size (ulong addr, flash_info_t *info);
static int flash_get_offsets (ulong base, flash_info_t *info);
@ -80,7 +80,7 @@ unsigned long flash_init_old(void)
{
int i;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
{
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = 0;
@ -101,25 +101,25 @@ unsigned long flash_init (void)
flash_to_xd();
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = 0;
flash_info[i].size = 0;
}
DEBUGF("\n## Get flash size @ 0x%08x\n", CFG_FLASH_BASE);
DEBUGF("\n## Get flash size @ 0x%08x\n", CONFIG_SYS_FLASH_BASE);
flash_size = flash_get_size (CFG_FLASH_BASE, flash_info);
flash_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info);
DEBUGF("## Flash bank size: %08lx\n", flash_size);
if (flash_size) {
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \
CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \
CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_MAX_SIZE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[0]);
#endif
@ -286,10 +286,10 @@ static ulong flash_get_size (ulong addr, flash_info_t *info)
}
if (info->sector_count > CFG_MAX_FLASH_SECT) {
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CFG_MAX_FLASH_SECT);
info->sector_count = CFG_MAX_FLASH_SECT;
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
if (! flash_get_offsets (addr, info)) {
@ -418,10 +418,10 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
last = start;
addr = info->start[l_sect];
DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT);
DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT);
while ((in8(addr) & 0x80) != 0x80) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
flash_reset (info->start[0]);
flash_to_mem();
@ -562,7 +562,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
/* data polling for D7 */
start = get_timer (0);
while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
flash_reset (addr);
flash_to_mem();
return (1);

28
board/MAI/AmigaOneG3SE/i8259.h
View File

@ -21,20 +21,20 @@
* MA 02111-1307 USA
*/
#define ICW1_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW1
#define ICW1_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW1
#define ICW2_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW2
#define ICW2_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW2
#define ICW3_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW3
#define ICW3_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW3
#define ICW4_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW4
#define ICW4_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW4
#define OCW1_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW1
#define OCW1_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW1
#define OCW2_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW2
#define OCW2_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW2
#define OCW3_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW3
#define OCW3_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW3
#define ICW1_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW1
#define ICW1_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW1
#define ICW2_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW2
#define ICW2_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW2
#define ICW3_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW3
#define ICW3_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW3
#define ICW4_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW4
#define ICW4_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW4
#define OCW1_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW1
#define OCW1_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW1
#define OCW2_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW2
#define OCW2_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW2
#define OCW3_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW3
#define OCW3_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW3
#define IMR_1 OCW1_1
#define IMR_2 OCW1_2

4
board/MAI/AmigaOneG3SE/interrupts.c
View File

@ -119,12 +119,12 @@ int interrupt_init (void)
#ifdef DEBUG
puts("interrupt_init: setting decrementer_count\n");
#endif
decrementer_count = get_tbclk() / CFG_HZ;
decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
#ifdef DEBUG
puts("interrupt_init: setting actual decremter\n");
#endif
set_dec (get_tbclk() / CFG_HZ);
set_dec (get_tbclk() / CONFIG_SYS_HZ);
#ifdef DEBUG
puts("interrupt_init: clearing external interrupt table\n");

10
board/MAI/AmigaOneG3SE/ps2kbd.c
View File

@ -214,7 +214,7 @@ int isa_kbd_init (void)
}
}
#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE
#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
extern int overwrite_console (void);
#else
int overwrite_console (void)
@ -492,22 +492,22 @@ unsigned char handle_kbd_event (void)
*/
unsigned char kbd_read_status(void)
{
return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
}
unsigned char kbd_read_input(void)
{
return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
}
void kbd_write_command(unsigned char cmd)
{
out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
}
void kbd_write_output(unsigned char data)
{
out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
}
int kbd_read_data(void)

6
board/MAI/AmigaOneG3SE/serial.c
View File

@ -6,7 +6,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CFG_NS16550
#ifndef CONFIG_SYS_NS16550
static uint32 ComPort1;
uint16 SerialEcho = 1;
@ -147,8 +147,8 @@ void serial_debug_putc (int c)
#else
const NS16550_t Com0 = (NS16550_t) CFG_NS16550_COM1;
const NS16550_t Com1 = (NS16550_t) CFG_NS16550_COM2;
const NS16550_t Com0 = (NS16550_t) CONFIG_SYS_NS16550_COM1;
const NS16550_t Com1 = (NS16550_t) CONFIG_SYS_NS16550_COM2;
int serial_init (void)
{

2
board/MAI/AmigaOneG3SE/usb_uhci.c
View File

@ -627,7 +627,7 @@ int usb_lowlevel_init(void)
pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr);
USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr);
usb_base_addr&=0xFFFFFFF0;
usb_base_addr+=CFG_ISA_IO_BASE_ADDRESS;
usb_base_addr+=CONFIG_SYS_ISA_IO_BASE_ADDRESS;
rh.devnum = 0;
usb_init_skel();
reset_hc();

22
board/Marvell/common/flash.c
View File

@ -48,7 +48,7 @@
int flash_erase_intel (flash_info_t * info, int s_first, int s_last);
int write_word_intel (bank_addr_t addr, bank_word_t value);
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
@ -68,14 +68,14 @@ unsigned long flash_init (void)
unsigned long base, flash_size;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* the boot flash */
base = CFG_FLASH_BASE;
base = CONFIG_SYS_FLASH_BASE;
size_b0 =
flash_get_size (CFG_BOOT_FLASH_WIDTH, (vu_long *) base,
flash_get_size (CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *) base,
&flash_info[0]);
printf ("[%ldkB@%lx] ", size_b0 / 1024, base);
@ -84,11 +84,11 @@ unsigned long flash_init (void)
printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b0, size_b0 << 20);
}
base = memoryGetDeviceBaseAddress (CFG_EXTRA_FLASH_DEVICE);
base = memoryGetDeviceBaseAddress (CONFIG_SYS_EXTRA_FLASH_DEVICE);
/* base = memoryGetDeviceBaseAddress(DEV_CS3_BASE_ADDR);*/
for (i = 1; i < CFG_MAX_FLASH_BANKS; i++) {
for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
unsigned long size =
flash_get_size (CFG_EXTRA_FLASH_WIDTH,
flash_get_size (CONFIG_SYS_EXTRA_FLASH_WIDTH,
(vu_long *) base, &flash_info[i]);
printf ("[%ldMB@%lx] ", size >> 20, base);
@ -617,7 +617,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
/* has the timeout limit been reached? */
if (get_timer (start)
>
CFG_FLASH_ERASE_TOUT)
CONFIG_SYS_FLASH_ERASE_TOUT)
{
/* timeout limit reached */
printf ("Time out limit reached erasing sector at address %08lx\n", info->start[sect]);
@ -776,7 +776,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
addr = (volatile unsigned char *) (info->start[l_sect]);
/* broken for 2x16: TODO */
while ((addr[0] & 0x80) != 0x80) {
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
@ -956,7 +956,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)
{
/* has the timeout limit been reached? */
if (get_timer (start) >
CFG_FLASH_WRITE_TOUT) {
CONFIG_SYS_FLASH_WRITE_TOUT) {
/* timeout limit reached */
printf ("Time out limit reached programming address %08lx with data %08lx\n", dest, data);
/* reset the flash */
@ -1064,7 +1064,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)
/* data polling for D7 */
start = get_timer (0);
while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}

8
board/Marvell/common/i2c.c
View File

@ -48,7 +48,7 @@ static void i2c_init (int speed, int slaveaddr)
unsigned int actualN = 0, actualM = 0;
unsigned int control, status;
unsigned int minMargin = 0xffffffff;
unsigned int tclk = CFG_TCLK;
unsigned int tclk = CONFIG_SYS_TCLK;
unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */
DP (puts ("i2c_init\n"));
@ -372,7 +372,7 @@ i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
int len)
{
uchar status = 0;
unsigned int i2cFreq = CFG_I2C_SPEED;
unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
DP (puts ("i2c_read\n"));
@ -447,7 +447,7 @@ i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
int len)
{
uchar status = 0;
unsigned int i2cFreq = CFG_I2C_SPEED;
unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
DP (puts ("i2c_write\n"));
@ -500,7 +500,7 @@ int i2c_probe (uchar chip)
unsigned int i2c_status;
#endif
uchar status = 0;
unsigned int i2cFreq = CFG_I2C_SPEED;
unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
DP (puts ("i2c_probe\n"));

4
board/Marvell/common/intel_flash.c
View File

@ -152,7 +152,7 @@ int write_word_intel (bank_addr_t addr, bank_word_t value)
/* data polling for D7 */
start = get_timer (0);
do {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
retval = 1;
goto done;
}
@ -227,7 +227,7 @@ int flash_erase_intel (flash_info_t * info, int s_first, int s_last)
do {
now = get_timer (start);
if (now - estart > CFG_FLASH_ERASE_TOUT) {
if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout (sect %d)\n", sect);
haderr = 1;
break;

2
board/Marvell/common/intel_flash.h
View File

@ -68,7 +68,7 @@
/* ID and Lock Configuration */
#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */
#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */
#define CHIP_RD_ID_DEV CFG_FLASH_ID
#define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID
/* dimensions */
#define CHIP_WIDTH 2 /* chips are in 16 bit mode */

18
board/Marvell/common/misc.S
View File

@ -16,7 +16,7 @@
board_relocate_rom:
mflr r7
/* update the location of the GT registers */
lis r11, CFG_GT_REGS@h
lis r11, CONFIG_SYS_GT_REGS@h
/* if we're using ECC, we must use the DMA engine to copy ourselves */
bl start_idma_transfer_0
bl wait_for_idma_0
@ -29,12 +29,12 @@ board_relocate_rom:
board_init_ecc:
mflr r7
/* NOTE: r10 still contains the location we've been relocated to
* which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
* which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
/* now that we're running from ram, init the rest of main memory
* for ECC use */
lis r8, CFG_MONITOR_LEN@h
ori r8, r8, CFG_MONITOR_LEN@l
lis r8, CONFIG_SYS_MONITOR_LEN@h
ori r8, r8, CONFIG_SYS_MONITOR_LEN@l
divw r3, r10, r8
@ -120,15 +120,15 @@ stop_idma_engine_0:
blr
#endif
#ifdef CFG_BOARD_ASM_INIT
#ifdef CONFIG_SYS_BOARD_ASM_INIT
/* NOTE: trashes r3-r7 */
.globl board_asm_init
board_asm_init:
/* just move the GT registers to where they belong */
lis r3, CFG_DFL_GT_REGS@h
ori r3, r3, CFG_DFL_GT_REGS@l
lis r4, CFG_GT_REGS@h
ori r4, r4, CFG_GT_REGS@l
lis r3, CONFIG_SYS_DFL_GT_REGS@h
ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l
lis r4, CONFIG_SYS_GT_REGS@h
ori r4, r4, CONFIG_SYS_GT_REGS@l
li r5, INTERNAL_SPACE_DECODE
/* test to see if we've already moved */

6
board/Marvell/common/ns16550.c
View File

@ -1,7 +1,7 @@
/*
* COM1 NS16550 support
* originally from linux source (arch/ppc/boot/ns16550.c)
* modified to use CFG_ISA_MEM and new defines
* modified to use CONFIG_SYS_ISA_MEM and new defines
*
* further modified by Josh Huber <huber@mclx.com> to support
* the DUART on the Galileo Eval board. (db64360)
@ -13,8 +13,8 @@
#ifdef ZUMA_NTL
/* no 16550 device */
#else
const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_DUART_IO + 0),
(NS16550_t) (CFG_DUART_IO + 0x20)
const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0),
(NS16550_t) (CONFIG_SYS_DUART_IO + 0x20)
};
volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)

2
board/Marvell/common/ns16550.h
View File

@ -2,7 +2,7 @@
* NS16550 Serial Port
* originally from linux source (arch/ppc/boot/ns16550.h)
* modified slightly to
* have addresses as offsets from CFG_ISA_BASE
* have addresses as offsets from CONFIG_SYS_ISA_BASE
* added a few more definitions
* added prototypes for ns16550.c
* reduced no of com ports to 2

22
board/Marvell/common/serial.c
View File

@ -52,17 +52,17 @@ DECLARE_GLOBAL_DATA_PTR;
int serial_init (void)
{
#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
int clock_divisor = 230400 / gd->baudrate;
#endif
mpsc_init (gd->baudrate);
/* init the DUART chans so that KGDB in the kernel can use them */
#ifdef CFG_INIT_CHAN1
#ifdef CONFIG_SYS_INIT_CHAN1
NS16550_reinit (COM_PORTS[0], clock_divisor);
#endif
#ifdef CFG_INIT_CHAN2
#ifdef CONFIG_SYS_INIT_CHAN2
NS16550_reinit (COM_PORTS[1], clock_divisor);
#endif
return (0);
@ -97,10 +97,10 @@ int serial_init (void)
{
int clock_divisor = 230400 / gd->baudrate;
#ifdef CFG_INIT_CHAN1
#ifdef CONFIG_SYS_INIT_CHAN1
(void) NS16550_init (0, clock_divisor);
#endif
#ifdef CFG_INIT_CHAN2
#ifdef CONFIG_SYS_INIT_CHAN2
(void) NS16550_init (1, clock_divisor);
#endif
return (0);
@ -109,29 +109,29 @@ int serial_init (void)
void serial_putc (const char c)
{
if (c == '\n')
NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r');
NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c);
NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
}
int serial_getc (void)
{
return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]);
return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
}
int serial_tstc (void)
{
return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]);
return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
}
void serial_setbrg (void)
{
int clock_divisor = 230400 / gd->baudrate;
#ifdef CFG_INIT_CHAN1
#ifdef CONFIG_SYS_INIT_CHAN1
NS16550_reinit (COM_PORTS[0], clock_divisor);
#endif
#ifdef CFG_INIT_CHAN2
#ifdef CONFIG_SYS_INIT_CHAN2
NS16550_reinit (COM_PORTS[1], clock_divisor);
#endif
}

140
board/Marvell/db64360/db64360.c
View File

@ -55,7 +55,7 @@
/* ------------------------------------------------------------------------- */
/* this is the current GT register space location */
/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
/* Unfortunately, we cant change it while we are in flash, so we initialize it
* to the "final" value. This means that any debug_led calls before
@ -64,7 +64,7 @@
*/
void board_prebootm_init (void);
unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
int display_mem_map (void);
/* ------------------------------------------------------------------------- */
@ -127,7 +127,7 @@ static void gt_pci_config (void)
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
(stat & 0xffff0000) | CFG_PCI_IDSEL);
(stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
@ -136,7 +136,7 @@ static void gt_pci_config (void)
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
(stat & 0xffff0000) | CFG_PCI_IDSEL);
(stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
/* Enable master */
@ -154,21 +154,21 @@ static void gt_pci_config (void)
/* ronen- add write to pci remap registers for 64460.
in 64360 when writing to pci base go and overide remap automaticaly,
in 64460 it doesn't */
GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
/* PCI interface settings */
/* Timeout set to retry forever */
@ -184,7 +184,7 @@ static void gt_pci_config (void)
for (stat = 0; stat <= PCI_HOST1; stat++)
pciWriteConfigReg (stat,
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
SELF, CFG_GT_REGS);
SELF, CONFIG_SYS_GT_REGS);
#endif
}
@ -200,7 +200,7 @@ static void gt_cpu_config (void)
tmp = GTREGREAD (CPU_CONFIGURATION);
/* set the SINGLE_CPU bit see MV64360 P.399 */
#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
tmp |= CPU_CONF_SINGLE_CPU;
#endif
@ -251,7 +251,7 @@ int board_early_init_f (void)
* it last time. (huber)
*/
my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
/* No PCI in first release of Port To_do: enable it. */
#ifdef CONFIG_PCI
@ -297,56 +297,56 @@ int board_early_init_f (void)
* on-board sram on the eval board, and updates the correct
* registers to boot from the sram. (device0)
*/
if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
sram_boot = 1;
if (!sram_boot)
memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
/* configure device timing */
#ifdef CFG_DEV0_PAR /* set port parameters for SRAM device module access */
#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */
if (!sram_boot)
GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
#endif
#ifdef CFG_DEV1_PAR /* set port parameters for RTC device module access */
GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */
GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
#endif
#ifdef CFG_DEV2_PAR /* set port parameters for DUART device module access */
GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */
GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
#endif
#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
/* detect if we are booting from the 32 bit flash */
if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
/* 32 bit boot flash */
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
CFG_32BIT_BOOT_PAR);
CONFIG_SYS_32BIT_BOOT_PAR);
} else {
/* 8 bit boot flash */
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
}
#else
/* 8 bit boot flash only */
/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
#endif
gt_cpu_config ();
/* MPP setup */
GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
DEBUG_LED0_ON ();
DEBUG_LED1_ON ();
DEBUG_LED2_ON ();
@ -359,7 +359,7 @@ int board_early_init_f (void)
int misc_init_r ()
{
icache_enable ();
#ifdef CFG_L2
#ifdef CONFIG_SYS_L2
l2cache_enable ();
#endif
#ifdef CONFIG_MPSC
@ -380,9 +380,9 @@ void after_reloc (ulong dest_addr, gd_t * gd)
/* check to see if we booted from the sram. If so, move things
* back to the way they should be. (we're running from main
* memory at this point now */
if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
}
display_mem_map ();
/* now, jump to the main ppcboot board init code */
@ -402,7 +402,7 @@ int checkboard (void)
{
int l_type = 0;
printf ("BOARD: %s\n", CFG_BOARD_NAME);
printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
return (l_type);
}
@ -415,34 +415,34 @@ void debug_led (int led, int mode)
if (mode == 1) {
switch (led) {
case 0:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x08000);
break;
case 1:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x0c000);
break;
case 2:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x10000);
break;
}
} else if (mode == 0) {
switch (led) {
case 0:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x14000);
break;
case 1:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x18000);
break;
case 2:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x1c000);
break;
}
@ -513,7 +513,7 @@ int display_mem_map (void)
/* DRAM check routines copied from gw8260 */
#if defined (CFG_DRAM_TEST)
#if defined (CONFIG_SYS_DRAM_TEST)
/*********************************************************************/
/* NAME: move64() - moves a double word (64-bit) */
@ -544,7 +544,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
}
#if defined (CFG_DRAM_TEST_DATA)
#if defined (CONFIG_SYS_DRAM_TEST_DATA)
unsigned long long pattern[] = {
0xaaaaaaaaaaaaaaaaULL,
@ -607,7 +607,7 @@ unsigned long long pattern[] = {
/*********************************************************************/
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
@ -634,9 +634,9 @@ int mem_test_data (void)
return 0;
}
#endif /* CFG_DRAM_TEST_DATA */
#endif /* CONFIG_SYS_DRAM_TEST_DATA */
#if defined (CFG_DRAM_TEST_ADDRESS)
#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
/*********************************************************************/
/* NAME: mem_test_address() - test address lines */
/* */
@ -661,8 +661,8 @@ int mem_test_data (void)
int mem_test_address (void)
{
volatile unsigned int *pmem =
(volatile unsigned int *) CFG_MEMTEST_START;
const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
unsigned int i;
/* write address to each location */
@ -679,9 +679,9 @@ int mem_test_address (void)
}
return 0;
}
#endif /* CFG_DRAM_TEST_ADDRESS */
#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
#if defined (CFG_DRAM_TEST_WALK)
#if defined (CONFIG_SYS_DRAM_TEST_WALK)
/*********************************************************************/
/* NAME: mem_march() - memory march */
/* */
@ -739,7 +739,7 @@ int mem_march (volatile unsigned long long *base,
}
return 0;
}
#endif /* CFG_DRAM_TEST_WALK */
#endif /* CONFIG_SYS_DRAM_TEST_WALK */
/*********************************************************************/
/* NAME: mem_test_walk() - a simple walking ones test */
@ -771,8 +771,8 @@ int mem_test_walk (void)
{
unsigned long long mask;
volatile unsigned long long *pmem =
(volatile unsigned long long *) CFG_MEMTEST_START;
const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
unsigned int i;
@ -848,9 +848,9 @@ int testdram (void)
/* runwalk = 0; */
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
}
#ifdef CFG_DRAM_TEST_DATA
#ifdef CONFIG_SYS_DRAM_TEST_DATA
if (rundata == 1) {
printf ("Test DATA ... ");
if (mem_test_data () == 1) {
@ -860,7 +860,7 @@ int testdram (void)
printf ("ok \n");
}
#endif
#ifdef CFG_DRAM_TEST_ADDRESS
#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
if (runaddress == 1) {
printf ("Test ADDRESS ... ");
if (mem_test_address () == 1) {
@ -870,7 +870,7 @@ int testdram (void)
printf ("ok \n");
}
#endif
#ifdef CFG_DRAM_TEST_WALK
#ifdef CONFIG_SYS_DRAM_TEST_WALK
if (runwalk == 1) {
printf ("Test WALKING ONEs ... ");
if (mem_test_walk () == 1) {
@ -886,7 +886,7 @@ int testdram (void)
return 0;
}
#endif /* CFG_DRAM_TEST */
#endif /* CONFIG_SYS_DRAM_TEST */
/* ronen - the below functions are used by the bootm function */
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
@ -925,7 +925,7 @@ void board_prebootm_init ()
/* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */
/* Relocate MV64360 internal regs */
my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
icache_disable ();
dcache_disable ();

6
board/Marvell/db64360/mpsc.c
View File

@ -426,7 +426,7 @@ void mpsc_sdma_init (void)
(MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
/* Setup MPSC internal address space base address */
GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
/* no high address remap*/
GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
@ -516,9 +516,9 @@ int galbrg_set_baudrate (int channel, int rate)
#ifdef ZUMA_NTL
/* from tclk */
clock = (CFG_TCLK / (16 * rate)) - 1;
clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
#else
clock = (CFG_TCLK / (16 * rate)) - 1;
clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
#endif
galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */

20
board/Marvell/db64360/pci.c
View File

@ -859,14 +859,14 @@ void pci_init_board (void)
/* PCI memory space */
pci_set_region (pci0_hose.regions + 0,
CFG_PCI0_0_MEM_SPACE,
CFG_PCI0_0_MEM_SPACE,
CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
CONFIG_SYS_PCI0_0_MEM_SPACE,
CONFIG_SYS_PCI0_0_MEM_SPACE,
CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci0_hose.regions + 1,
CFG_PCI0_IO_SPACE_PCI,
CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
CONFIG_SYS_PCI0_IO_SPACE_PCI,
CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci0_hose,
pci_hose_read_config_byte_via_dword,
@ -901,14 +901,14 @@ void pci_init_board (void)
/* PCI memory space */
pci_set_region (pci1_hose.regions + 0,
CFG_PCI1_0_MEM_SPACE,
CFG_PCI1_0_MEM_SPACE,
CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
CONFIG_SYS_PCI1_0_MEM_SPACE,
CONFIG_SYS_PCI1_0_MEM_SPACE,
CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci1_hose.regions + 1,
CFG_PCI1_IO_SPACE_PCI,
CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
CONFIG_SYS_PCI1_IO_SPACE_PCI,
CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci1_hose,
pci_hose_read_config_byte_via_dword,

28
board/Marvell/db64360/sdram_init.c
View File

@ -312,7 +312,7 @@ return 0;
} else
dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
for (i = 0; i <= 127; i++) {
printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
@ -690,16 +690,16 @@ return 0;
if ((dimmInfo->
minimumCycleTimeAtMaxCasLatancy_LoP
<
CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
||
((dimmInfo->
minimumCycleTimeAtMaxCasLatancy_LoP
==
CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
&& (dimmInfo->
minimumCycleTimeAtMaxCasLatancy_RoP
<
CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
{
dimmInfo->
maxClSupported_DDR
@ -714,16 +714,16 @@ return 0;
if ((dimmInfo->
minimumCycleTimeAtMaxCasLatancy_LoP
>
CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
||
((dimmInfo->
minimumCycleTimeAtMaxCasLatancy_LoP
==
CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
&& (dimmInfo->
minimumCycleTimeAtMaxCasLatancy_RoP
>
CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
{
printf ("*********************************************************\n");
printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
@ -1290,37 +1290,37 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
case 0x0:
case 0x80: /* refresh period is 15.625 usec */
sdram_config_reg =
(unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ)
(unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_HZ)
/ (float) 1000000.0);
break;
case 0x1:
case 0x81: /* refresh period is 3.9 usec */
sdram_config_reg =
(unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) /
(unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_HZ) /
(float) 1000000.0);
break;
case 0x2:
case 0x82: /* refresh period is 7.8 usec */
sdram_config_reg =
(unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) /
(unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_HZ) /
(float) 1000000.0);
break;
case 0x3:
case 0x83: /* refresh period is 31.3 usec */
sdram_config_reg =
(unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) /
(unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_HZ) /
(float) 1000000.0);
break;
case 0x4:
case 0x84: /* refresh period is 62.5 usec */
sdram_config_reg =
(unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) /
(unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_HZ) /
(float) 1000000.0);
break;
case 0x5:
case 0x85: /* refresh period is 125 usec */
sdram_config_reg =
(unsigned int) (((float) 125 * (float) CFG_BUS_HZ) /
(unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_HZ) /
(float) 1000000.0);
break;
default: /* refresh period undefined */
@ -1807,7 +1807,7 @@ phys_size_t initdram (int board_type)
printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
/* skip over banks that are not populated */
if (!checkbank[bank_no])
continue;

140
board/Marvell/db64460/db64460.c
View File

@ -55,7 +55,7 @@
/* ------------------------------------------------------------------------- */
/* this is the current GT register space location */
/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
/* Unfortunately, we cant change it while we are in flash, so we initialize it
* to the "final" value. This means that any debug_led calls before
@ -64,7 +64,7 @@
*/
void board_prebootm_init (void);
unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
int display_mem_map (void);
/* ------------------------------------------------------------------------- */
@ -127,7 +127,7 @@ static void gt_pci_config (void)
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
(stat & 0xffff0000) | CFG_PCI_IDSEL);
(stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
@ -136,7 +136,7 @@ static void gt_pci_config (void)
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
(stat & 0xffff0000) | CFG_PCI_IDSEL);
(stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
/* Enable master */
@ -154,21 +154,21 @@ static void gt_pci_config (void)
/* ronen- add write to pci remap registers for 64460.
in 64360 when writing to pci base go and overide remap automaticaly,
in 64460 it doesn't */
GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
/* PCI interface settings */
/* Timeout set to retry forever */
@ -184,7 +184,7 @@ static void gt_pci_config (void)
for (stat = 0; stat <= PCI_HOST1; stat++)
pciWriteConfigReg (stat,
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
SELF, CFG_GT_REGS);
SELF, CONFIG_SYS_GT_REGS);
#endif
}
@ -200,7 +200,7 @@ static void gt_cpu_config (void)
tmp = GTREGREAD (CPU_CONFIGURATION);
/* set the SINGLE_CPU bit see MV64460 P.399 */
#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
tmp |= CPU_CONF_SINGLE_CPU;
#endif
@ -251,7 +251,7 @@ int board_early_init_f (void)
* it last time. (huber)
*/
my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
/* No PCI in first release of Port To_do: enable it. */
#ifdef CONFIG_PCI
@ -297,56 +297,56 @@ int board_early_init_f (void)
* on-board sram on the eval board, and updates the correct
* registers to boot from the sram. (device0)
*/
if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
sram_boot = 1;
if (!sram_boot)
memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
/* configure device timing */
#ifdef CFG_DEV0_PAR /* set port parameters for SRAM device module access */
#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */
if (!sram_boot)
GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
#endif
#ifdef CFG_DEV1_PAR /* set port parameters for RTC device module access */
GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */
GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
#endif
#ifdef CFG_DEV2_PAR /* set port parameters for DUART device module access */
GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */
GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
#endif
#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
/* detect if we are booting from the 32 bit flash */
if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
/* 32 bit boot flash */
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
CFG_32BIT_BOOT_PAR);
CONFIG_SYS_32BIT_BOOT_PAR);
} else {
/* 8 bit boot flash */
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
}
#else
/* 8 bit boot flash only */
/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
#endif
gt_cpu_config ();
/* MPP setup */
GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
DEBUG_LED0_ON ();
DEBUG_LED1_ON ();
DEBUG_LED2_ON ();
@ -359,7 +359,7 @@ int board_early_init_f (void)
int misc_init_r ()
{
icache_enable ();
#ifdef CFG_L2
#ifdef CONFIG_SYS_L2
l2cache_enable ();
#endif
#ifdef CONFIG_MPSC
@ -380,9 +380,9 @@ void after_reloc (ulong dest_addr, gd_t * gd)
/* check to see if we booted from the sram. If so, move things
* back to the way they should be. (we're running from main
* memory at this point now */
if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
}
display_mem_map ();
/* now, jump to the main ppcboot board init code */
@ -402,7 +402,7 @@ int checkboard (void)
{
int l_type = 0;
printf ("BOARD: %s\n", CFG_BOARD_NAME);
printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
return (l_type);
}
@ -415,34 +415,34 @@ void debug_led (int led, int mode)
if (mode == 1) {
switch (led) {
case 0:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x08000);
break;
case 1:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x0c000);
break;
case 2:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x10000);
break;
}
} else if (mode == 0) {
switch (led) {
case 0:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x14000);
break;
case 1:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x18000);
break;
case 2:
addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
0x1c000);
break;
}
@ -513,7 +513,7 @@ int display_mem_map (void)
/* DRAM check routines copied from gw8260 */
#if defined (CFG_DRAM_TEST)
#if defined (CONFIG_SYS_DRAM_TEST)
/*********************************************************************/
/* NAME: move64() - moves a double word (64-bit) */
@ -544,7 +544,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
}
#if defined (CFG_DRAM_TEST_DATA)
#if defined (CONFIG_SYS_DRAM_TEST_DATA)
unsigned long long pattern[] = {
0xaaaaaaaaaaaaaaaaULL,
@ -607,7 +607,7 @@ unsigned long long pattern[] = {
/*********************************************************************/
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
@ -634,9 +634,9 @@ int mem_test_data (void)
return 0;
}
#endif /* CFG_DRAM_TEST_DATA */
#endif /* CONFIG_SYS_DRAM_TEST_DATA */
#if defined (CFG_DRAM_TEST_ADDRESS)
#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
/*********************************************************************/
/* NAME: mem_test_address() - test address lines */
/* */
@ -661,8 +661,8 @@ int mem_test_data (void)
int mem_test_address (void)
{
volatile unsigned int *pmem =
(volatile unsigned int *) CFG_MEMTEST_START;
const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
unsigned int i;
/* write address to each location */
@ -679,9 +679,9 @@ int mem_test_address (void)
}
return 0;
}
#endif /* CFG_DRAM_TEST_ADDRESS */
#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
#if defined (CFG_DRAM_TEST_WALK)
#if defined (CONFIG_SYS_DRAM_TEST_WALK)
/*********************************************************************/
/* NAME: mem_march() - memory march */
/* */
@ -739,7 +739,7 @@ int mem_march (volatile unsigned long long *base,
}
return 0;
}
#endif /* CFG_DRAM_TEST_WALK */
#endif /* CONFIG_SYS_DRAM_TEST_WALK */
/*********************************************************************/
/* NAME: mem_test_walk() - a simple walking ones test */
@ -771,8 +771,8 @@ int mem_test_walk (void)
{
unsigned long long mask;
volatile unsigned long long *pmem =
(volatile unsigned long long *) CFG_MEMTEST_START;
const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
unsigned int i;
@ -848,9 +848,9 @@ int testdram (void)
/* runwalk = 0; */
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
}
#ifdef CFG_DRAM_TEST_DATA
#ifdef CONFIG_SYS_DRAM_TEST_DATA
if (rundata == 1) {
printf ("Test DATA ... ");
if (mem_test_data () == 1) {
@ -860,7 +860,7 @@ int testdram (void)
printf ("ok \n");
}
#endif
#ifdef CFG_DRAM_TEST_ADDRESS
#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
if (runaddress == 1) {
printf ("Test ADDRESS ... ");
if (mem_test_address () == 1) {
@ -870,7 +870,7 @@ int testdram (void)
printf ("ok \n");
}
#endif
#ifdef CFG_DRAM_TEST_WALK
#ifdef CONFIG_SYS_DRAM_TEST_WALK
if (runwalk == 1) {
printf ("Test WALKING ONEs ... ");
if (mem_test_walk () == 1) {
@ -886,7 +886,7 @@ int testdram (void)
return 0;
}
#endif /* CFG_DRAM_TEST */
#endif /* CONFIG_SYS_DRAM_TEST */
/* ronen - the below functions are used by the bootm function */
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
@ -925,7 +925,7 @@ void board_prebootm_init ()
GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00);
/* Relocate MV64460 internal regs */
my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
icache_disable ();
dcache_disable ();

6
board/Marvell/db64460/mpsc.c
View File

@ -426,7 +426,7 @@ void mpsc_sdma_init (void)
(MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
/* Setup MPSC internal address space base address */
GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
/* no high address remap*/
GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
@ -516,9 +516,9 @@ int galbrg_set_baudrate (int channel, int rate)
#ifdef ZUMA_NTL
/* from tclk */
clock = (CFG_TCLK / (16 * rate)) - 1;
clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
#else
clock = (CFG_TCLK / (16 * rate)) - 1;
clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
#endif
galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */

20
board/Marvell/db64460/pci.c
View File

@ -859,14 +859,14 @@ void pci_init_board (void)
/* PCI memory space */
pci_set_region (pci0_hose.regions + 0,
CFG_PCI0_0_MEM_SPACE,
CFG_PCI0_0_MEM_SPACE,
CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
CONFIG_SYS_PCI0_0_MEM_SPACE,
CONFIG_SYS_PCI0_0_MEM_SPACE,
CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci0_hose.regions + 1,
CFG_PCI0_IO_SPACE_PCI,
CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
CONFIG_SYS_PCI0_IO_SPACE_PCI,
CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci0_hose,
pci_hose_read_config_byte_via_dword,
@ -901,14 +901,14 @@ void pci_init_board (void)
/* PCI memory space */
pci_set_region (pci1_hose.regions + 0,
CFG_PCI1_0_MEM_SPACE,
CFG_PCI1_0_MEM_SPACE,
CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
CONFIG_SYS_PCI1_0_MEM_SPACE,
CONFIG_SYS_PCI1_0_MEM_SPACE,
CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci1_hose.regions + 1,
CFG_PCI1_IO_SPACE_PCI,
CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
CONFIG_SYS_PCI1_IO_SPACE_PCI,
CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci1_hose,
pci_hose_read_config_byte_via_dword,

28
board/Marvell/db64460/sdram_init.c
View File

@ -312,7 +312,7 @@ return 0;
} else
dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
for (i = 0; i <= 127; i++) {
printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
@ -690,16 +690,16 @@ return 0;
if ((dimmInfo->
minimumCycleTimeAtMaxCasLatancy_LoP
<
CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
||
((dimmInfo->
minimumCycleTimeAtMaxCasLatancy_LoP
==
CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
&& (dimmInfo->
minimumCycleTimeAtMaxCasLatancy_RoP
<
CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
{
dimmInfo->
maxClSupported_DDR
@ -714,16 +714,16 @@ return 0;
if ((dimmInfo->
minimumCycleTimeAtMaxCasLatancy_LoP
>
CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
||
((dimmInfo->
minimumCycleTimeAtMaxCasLatancy_LoP
==
CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
&& (dimmInfo->
minimumCycleTimeAtMaxCasLatancy_RoP
>
CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
{
printf ("*********************************************************\n");
printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
@ -1289,37 +1289,37 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
case 0x0:
case 0x80: /* refresh period is 15.625 usec */
sdram_config_reg =
(unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ)
(unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_HZ)
/ (float) 1000000.0);
break;
case 0x1:
case 0x81: /* refresh period is 3.9 usec */
sdram_config_reg =
(unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) /
(unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_HZ) /
(float) 1000000.0);
break;
case 0x2:
case 0x82: /* refresh period is 7.8 usec */
sdram_config_reg =
(unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) /
(unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_HZ) /
(float) 1000000.0);
break;
case 0x3:
case 0x83: /* refresh period is 31.3 usec */
sdram_config_reg =
(unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) /
(unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_HZ) /
(float) 1000000.0);
break;
case 0x4:
case 0x84: /* refresh period is 62.5 usec */
sdram_config_reg =
(unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) /
(unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_HZ) /
(float) 1000000.0);
break;
case 0x5:
case 0x85: /* refresh period is 125 usec */
sdram_config_reg =
(unsigned int) (((float) 125 * (float) CFG_BUS_HZ) /
(unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_HZ) /
(float) 1000000.0);
break;
default: /* refresh period undefined */
@ -1816,7 +1816,7 @@ phys_size_t initdram (int board_type)
printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
/* skip over banks that are not populated */
if (!checkbank[bank_no])
continue;

6
board/MigoR/migo_r.c
View File

@ -42,9 +42,9 @@ int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_memstart = CFG_SDRAM_BASE;
gd->bd->bi_memsize = CFG_SDRAM_SIZE;
printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
return 0;
}

16
board/RPXClassic/RPXClassic.c
View File

@ -111,7 +111,7 @@ void board_get_enetaddr (uchar * enet)
char buff[256], *cp;
/* Initialize I2C */
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
/* Read 256 bytes in EEPROM */
i2c_read (0x54, 0, 1, (uchar *)buff, 128);
@ -167,7 +167,7 @@ void rpxclassic_init (void)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size10;
@ -175,15 +175,15 @@ phys_size_t initdram (int board_type)
sizeof (sdram_table) / sizeof (uint));
/* Refresh clock prescalar */
memctl->memc_mptpr = CFG_MPTPR;
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
memctl->memc_mar = 0x00000000;
/* Map controller banks 1 to the SDRAM bank */
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay (200);
@ -200,7 +200,7 @@ phys_size_t initdram (int board_type)
* try 10 column mode
*/
size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM,
size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
return (size10);
@ -218,7 +218,7 @@ phys_size_t initdram (int board_type)
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_mamr = mamr_value;

2
board/RPXClassic/eccx.c
View File

@ -299,7 +299,7 @@ void video_get_info_str (int line_number, char *info)
*/
unsigned int board_video_init (void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* Program ECCX registers */

18
board/RPXClassic/flash.c
View File

@ -33,7 +33,7 @@
#include <common.h>
#include <mpc8xx.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
@ -51,20 +51,20 @@ unsigned long flash_init (void)
int i;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
@ -313,7 +313,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
last = start;
addr = (vu_long *)(info->start[l_sect]);
while ((addr[0] & 0x80808080) != 0x80808080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
@ -436,7 +436,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
/* data polling for D7 */
start = get_timer (0);
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}

14
board/RPXlite/RPXlite.c
View File

@ -104,7 +104,7 @@ int checkboard (void)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size10;
@ -112,15 +112,15 @@ phys_size_t initdram (int board_type)
sizeof (sdram_table) / sizeof (uint));
/* Refresh clock prescalar */
memctl->memc_mptpr = CFG_MPTPR;
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
memctl->memc_mar = 0x00000000;
/* Map controller banks 1 to the SDRAM bank */
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay (200);
@ -137,7 +137,7 @@ phys_size_t initdram (int board_type)
* try 10 column mode
*/
size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM,
size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
return (size10);
@ -156,7 +156,7 @@ phys_size_t initdram (int board_type)
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_mamr = mamr_value;

24
board/RPXlite/flash.c
View File

@ -38,7 +38,7 @@
#include <common.h>
#include <mpc8xx.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
@ -52,13 +52,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info);
unsigned long flash_init (void)
{
/* volatile immap_t *immap = (immap_t *)CFG_IMMR; */
/* volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; */
/* volatile memctl8xx_t *memctl = &immap->im_memctl; */
unsigned long size_b0 ;
int i;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@ -73,19 +73,19 @@ unsigned long flash_init (void)
*/
/* Remap FLASH according to real size */
/*%%%
memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
%%%*/
/* Re-do sizing to get full correct info */
size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
@ -390,7 +390,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
last = start;
addr = (vu_long *)(info->start[l_sect]);
while ((addr[0] & 0x80808080) != 0x80808080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
@ -513,7 +513,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
/* data polling for D7 */
start = get_timer (0);
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}

16
board/RPXlite_dw/RPXlite_dw.c
View File

@ -106,22 +106,22 @@ int checkboard (void)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size9;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
/* Refresh clock prescalar */
memctl->memc_mptpr = CFG_MPTPR ;
memctl->memc_mptpr = CONFIG_SYS_MPTPR ;
memctl->memc_mar = 0x00000088;
/* Map controller banks 1 to the SDRAM bank */
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
/*Disable Periodic timer A. */
udelay(200);
@ -142,13 +142,13 @@ phys_size_t initdram (int board_type)
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
/*
* Final mapping:
*/
memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
udelay (1000);
@ -171,7 +171,7 @@ void rpxlite_init (void)
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_mamr = mamr_value;

18
board/RPXlite_dw/flash.c
View File

@ -49,7 +49,7 @@
#include <common.h>
#include <mpc8xx.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions vu_long : volatile unsigned long IN include/common.h
@ -64,22 +64,22 @@ unsigned long flash_init (void)
int i;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* If Monitor is in the cope of FLASH,then
* protect this area by default in case for
* other occupation. [SAM] */
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
&flash_info[0]);
#endif
flash_info[0].size = size_b0;
@ -360,7 +360,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
last = start;
addr = (vu_long *)(info->start[l_sect]);
while ((addr[0] & 0x80808080) != 0x80808080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
@ -482,7 +482,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
/* data polling for D7 */
start = get_timer (0);
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}

26
board/RRvision/RRvision.c
View File

@ -112,7 +112,7 @@ int checkboard (void)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long reg;
long int size8, size9;
@ -126,17 +126,17 @@ phys_size_t initdram (int board_type)
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
memctl->memc_mar = 0x00000088;
/*
* Map controller bank 1 the SDRAM bank 2 at physical address 0.
*/
memctl->memc_or1 = CFG_OR2_PRELIM;
memctl->memc_br1 = CFG_BR2_PRELIM;
memctl->memc_or1 = CONFIG_SYS_OR2_PRELIM;
memctl->memc_br1 = CONFIG_SYS_BR2_PRELIM;
memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay (200);
@ -156,7 +156,7 @@ phys_size_t initdram (int board_type)
*
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL,
size8 = dram_size (CONFIG_SYS_MAMR_8COL,
SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
@ -165,7 +165,7 @@ phys_size_t initdram (int board_type)
/*
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL,
size9 = dram_size (CONFIG_SYS_MAMR_9COL,
SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
@ -174,7 +174,7 @@ phys_size_t initdram (int board_type)
/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
} else { /* back to 8 columns */
size = size8;
memctl->memc_mamr = CFG_MAMR_8COL;
memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
udelay (500);
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
}
@ -187,15 +187,15 @@ phys_size_t initdram (int board_type)
*/
if (size < 0x02000000) {
/* reduce to 15.6 us (62.4 us / quad) */
memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
udelay (1000);
}
/*
* Final mapping
*/
memctl->memc_or1 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
memctl->memc_or1 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
/*
* No bank 1
@ -206,7 +206,7 @@ phys_size_t initdram (int board_type)
/* adjust refresh rate depending on SDRAM type, one bank */
reg = memctl->memc_mptpr;
reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
memctl->memc_mptpr = reg;
udelay (10000);
@ -227,7 +227,7 @@ phys_size_t initdram (int board_type)
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_mamr = mamr_value;

24
board/RRvision/flash.c
View File

@ -27,10 +27,10 @@
#include <mpc8xx.h>
#ifndef CONFIG_ENV_ADDR
#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#endif
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
@ -43,13 +43,13 @@ static int write_word (flash_info_t *info, ulong dest, ulong data);
unsigned long flash_init (void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size;
int i;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@ -63,17 +63,17 @@ unsigned long flash_init (void)
}
/* Remap FLASH according to real size */
memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & OR_AM_MSK);
memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & OR_AM_MSK);
memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
/* Re-do sizing to get full correct info */
size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
@ -388,7 +388,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
last = start;
addr = (vu_long*)(info->start[l_sect]);
while ((addr[0] & 0x00800080) != 0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
puts ("Timeout\n");
return 1;
}
@ -511,7 +511,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
/* data polling for D7 */
start = get_timer (0);
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}

2
board/a3000/a3000.c
View File

@ -46,7 +46,7 @@ phys_size_t initdram (int board_type)
long mear1;
long emear1;
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
new_bank0_end = size - 1;
mear1 = mpc824x_mpc107_getreg(MEAR1);

30
board/a3000/flash.c
View File

@ -27,7 +27,7 @@
#if defined(CONFIG_ENV_IS_IN_FLASH)
# ifndef CONFIG_ENV_ADDR
# define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
# endif
# ifndef CONFIG_ENV_SIZE
# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
@ -48,7 +48,7 @@
#endif
/*---------------------------------------------------------------------*/
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
@ -65,13 +65,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info);
unsigned long flash_init (void)
{
unsigned long flash_banks[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS;
unsigned long size, size_b[CFG_MAX_FLASH_BANKS];
unsigned long flash_banks[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_BANKS;
unsigned long size, size_b[CONFIG_SYS_MAX_FLASH_BANKS];
int i;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
{
flash_info[i].flash_id = FLASH_UNKNOWN;
@ -99,12 +99,12 @@ unsigned long flash_init (void)
}
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, CFG_MONITOR_LEN);
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN);
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
&flash_info[0]);
#endif
@ -119,7 +119,7 @@ unsigned long flash_init (void)
size = 0;
DEBUGF("## Final Flash bank sizes: ");
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
{
DEBUGF("%08lx ", size_b[i]);
size += size_b[i];
@ -285,10 +285,10 @@ static ulong flash_get_size (vu_char *addr, flash_info_t *info)
}
if (info->sector_count > CFG_MAX_FLASH_SECT) {
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CFG_MAX_FLASH_SECT);
info->sector_count = CFG_MAX_FLASH_SECT;
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
addr[0] = BS(0xFF); /* restore read mode */
@ -356,7 +356,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
udelay (1000);
while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = BS(0xB0); /* suspend erase */
*addr = BS(0xFF); /* reset to read mode */
@ -439,7 +439,7 @@ static int write_data (flash_info_t *info, uchar *dest, uchar data)
start = get_timer (0);
while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = BS(0xFF); /* restore read mode */
return 1;
}

14
board/actux1/actux1.c
View File

@ -49,16 +49,16 @@ int board_init (void)
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
/* Setup GPIO's for PCI INTA */
GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI1_INTA);
GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI1_INTA);
GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA);
GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA);
/* Setup GPIO's for 33MHz clock output */
GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
*IXP425_GPIO_GPCLKR = 0x011001FF;
/* CS5: Debug port */
@ -69,7 +69,7 @@ int board_init (void)
*IXP425_EXP_CS7 = 0x80900003;
udelay (533);
GPIO_OUTPUT_SET (CFG_GPIO_IORST);
GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
ACTUX1_LED1 (2);
ACTUX1_LED2 (2);

22
board/actux1/actux1_hw.h
View File

@ -42,16 +42,16 @@
#define ACTUX1_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
/* GPIO settings */
#define CFG_GPIO_PCI1_INTA 2
#define CFG_GPIO_PCI2_INTA 3
#define CFG_GPIO_I2C_SDA 4
#define CFG_GPIO_I2C_SCL 5
#define CFG_GPIO_DBGJUMPER 9
#define CFG_GPIO_BUTTON1 10
#define CFG_GPIO_DBGSENSE 11
#define CFG_GPIO_DTR 12
#define CFG_GPIO_IORST 13 /* Out */
#define CFG_GPIO_PCI_CLK 14 /* Out */
#define CFG_GPIO_EXTBUS_CLK 15 /* Out */
#define CONFIG_SYS_GPIO_PCI1_INTA 2
#define CONFIG_SYS_GPIO_PCI2_INTA 3
#define CONFIG_SYS_GPIO_I2C_SDA 4
#define CONFIG_SYS_GPIO_I2C_SCL 5
#define CONFIG_SYS_GPIO_DBGJUMPER 9
#define CONFIG_SYS_GPIO_BUTTON1 10
#define CONFIG_SYS_GPIO_DBGSENSE 11
#define CONFIG_SYS_GPIO_DTR 12
#define CONFIG_SYS_GPIO_IORST 13 /* Out */
#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
#endif

28
board/actux2/actux2.c
View File

@ -50,24 +50,24 @@ int board_init (void)
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
GPIO_OUTPUT_ENABLE (CFG_GPIO_ETHRST);
GPIO_OUTPUT_ENABLE (CFG_GPIO_DSR);
GPIO_OUTPUT_ENABLE (CFG_GPIO_DCD);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR);
GPIO_OUTPUT_SET (CFG_GPIO_DCD);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
/* Setup GPIO's for Interrupt inputs */
GPIO_OUTPUT_DISABLE (CFG_GPIO_DBGINT);
GPIO_OUTPUT_DISABLE (CFG_GPIO_ETHINT);
GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
/* Setup GPIO's for 33MHz clock output */
GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
*IXP425_GPIO_GPCLKR = 0x011001FF;
/* CS1: IPAC-X */
@ -80,8 +80,8 @@ int board_init (void)
*IXP425_EXP_CS7 = 0x80900003;
udelay (533);
GPIO_OUTPUT_SET (CFG_GPIO_IORST);
GPIO_OUTPUT_SET (CFG_GPIO_ETHRST);
GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
ACTUX2_LED1 (1);
ACTUX2_LED2 (0);

32
board/actux2/actux2_hw.h
View File

@ -39,21 +39,21 @@
/*
* GPIO settings
*/
#define CFG_GPIO_DBGINT 0
#define CFG_GPIO_ETHINT 1
#define CFG_GPIO_ETHRST 2 /* Out */
#define CFG_GPIO_LED5_GN 3 /* Out */
#define CFG_GPIO_UNUSED4 4
#define CFG_GPIO_UNUSED5 5
#define CFG_GPIO_DSR 6 /* Out */
#define CFG_GPIO_DCD 7 /* Out */
#define CFG_GPIO_IPAC_INT 8
#define CFG_GPIO_DBGJUMPER 9
#define CFG_GPIO_BUTTON1 10
#define CFG_GPIO_DBGSENSE 11
#define CFG_GPIO_DTR 12
#define CFG_GPIO_IORST 13 /* Out */
#define CFG_GPIO_PCI_CLK 14 /* Out */
#define CFG_GPIO_EXTBUS_CLK 15 /* Out */
#define CONFIG_SYS_GPIO_DBGINT 0
#define CONFIG_SYS_GPIO_ETHINT 1
#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */
#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */
#define CONFIG_SYS_GPIO_UNUSED4 4
#define CONFIG_SYS_GPIO_UNUSED5 5
#define CONFIG_SYS_GPIO_DSR 6 /* Out */
#define CONFIG_SYS_GPIO_DCD 7 /* Out */
#define CONFIG_SYS_GPIO_IPAC_INT 8
#define CONFIG_SYS_GPIO_DBGJUMPER 9
#define CONFIG_SYS_GPIO_BUTTON1 10
#define CONFIG_SYS_GPIO_DBGSENSE 11
#define CONFIG_SYS_GPIO_DTR 12
#define CONFIG_SYS_GPIO_IORST 13 /* Out */
#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
#endif

40
board/actux3/actux3.c
View File

@ -50,35 +50,35 @@ int board_init (void)
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
GPIO_OUTPUT_ENABLE (CFG_GPIO_ETHRST);
GPIO_OUTPUT_ENABLE (CFG_GPIO_DSR);
GPIO_OUTPUT_ENABLE (CFG_GPIO_DCD);
GPIO_OUTPUT_ENABLE (CFG_GPIO_LED5_GN);
GPIO_OUTPUT_ENABLE (CFG_GPIO_LED6_RT);
GPIO_OUTPUT_ENABLE (CFG_GPIO_LED6_GN);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED5_GN);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_RT);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_GN);
GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR);
GPIO_OUTPUT_SET (CFG_GPIO_DCD);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
GPIO_OUTPUT_CLEAR (CFG_GPIO_LED5_GN);
GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_RT);
GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_GN);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED5_GN);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_RT);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_GN);
/*
* Setup GPIO's for Interrupt inputs
*/
GPIO_OUTPUT_DISABLE (CFG_GPIO_DBGINT);
GPIO_OUTPUT_DISABLE (CFG_GPIO_ETHINT);
GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
/*
* Setup GPIO's for 33MHz clock output
*/
GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
*IXP425_GPIO_GPCLKR = 0x011001FF;
/* CS1: IPAC-X */
@ -91,8 +91,8 @@ int board_init (void)
*IXP425_EXP_CS7 = 0x80900003;
udelay (533);
GPIO_OUTPUT_SET (CFG_GPIO_IORST);
GPIO_OUTPUT_SET (CFG_GPIO_ETHRST);
GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
ACTUX3_LED1_RT (1);
ACTUX3_LED1_GN (0);

30
board/actux3/actux3_hw.h
View File

@ -41,20 +41,20 @@
#define ACTUX3_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
/* GPIO settings */
#define CFG_GPIO_DBGINT 0
#define CFG_GPIO_ETHINT 1
#define CFG_GPIO_ETHRST 2 /* Out */
#define CFG_GPIO_LED5_GN 3 /* Out */
#define CFG_GPIO_LED6_RT 4 /* Out */
#define CFG_GPIO_LED6_GN 5 /* Out */
#define CFG_GPIO_DSR 6 /* Out */
#define CFG_GPIO_DCD 7 /* Out */
#define CFG_GPIO_DBGJUMPER 9
#define CFG_GPIO_BUTTON1 10
#define CFG_GPIO_DBGSENSE 11
#define CFG_GPIO_DTR 12
#define CFG_GPIO_IORST 13 /* Out */
#define CFG_GPIO_PCI_CLK 14 /* Out */
#define CFG_GPIO_EXTBUS_CLK 15 /* Out */
#define CONFIG_SYS_GPIO_DBGINT 0
#define CONFIG_SYS_GPIO_ETHINT 1
#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */
#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */
#define CONFIG_SYS_GPIO_LED6_RT 4 /* Out */
#define CONFIG_SYS_GPIO_LED6_GN 5 /* Out */
#define CONFIG_SYS_GPIO_DSR 6 /* Out */
#define CONFIG_SYS_GPIO_DCD 7 /* Out */
#define CONFIG_SYS_GPIO_DBGJUMPER 9
#define CONFIG_SYS_GPIO_BUTTON1 10
#define CONFIG_SYS_GPIO_DBGSENSE 11
#define CONFIG_SYS_GPIO_DTR 12
#define CONFIG_SYS_GPIO_IORST 13 /* Out */
#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
#endif

54
board/actux4/actux4.c
View File

@ -49,53 +49,53 @@ int board_init (void)
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
GPIO_OUTPUT_CLEAR (CFG_GPIO_nPWRON);
GPIO_OUTPUT_ENABLE (CFG_GPIO_nPWRON);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_nPWRON);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_nPWRON);
GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
/* led not populated on board*/
GPIO_OUTPUT_ENABLE (CFG_GPIO_LED3);
GPIO_OUTPUT_SET (CFG_GPIO_LED3);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED3);
GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED3);
/* middle LED */
GPIO_OUTPUT_ENABLE (CFG_GPIO_LED2);
GPIO_OUTPUT_SET (CFG_GPIO_LED2);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED2);
GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED2);
/* right LED */
/* weak pulldown = LED weak on */
GPIO_OUTPUT_DISABLE (CFG_GPIO_LED1);
GPIO_OUTPUT_SET (CFG_GPIO_LED1);
GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_LED1);
GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED1);
/* Setup GPIO's for Interrupt inputs */
GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTA);
GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTB);
GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTC);
GPIO_OUTPUT_DISABLE (CFG_GPIO_RTCINT);
GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI_INTA);
GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI_INTB);
GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTA);
GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTB);
GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTC);
GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_RTCINT);
GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTA);
GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTB);
GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTA);
GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTB);
GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTC);
GPIO_INT_ACT_LOW_SET (CFG_GPIO_RTCINT);
GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI_INTA);
GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI_INTB);
GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTA);
GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTB);
GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTC);
GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_RTCINT);
GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTA);
GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTB);
/* Setup GPIO's for 33MHz clock output */
*IXP425_GPIO_GPCLKR = 0x011001FF;
GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
*IXP425_EXP_CS1 = 0xbd113c42;
udelay (10000);
GPIO_OUTPUT_SET (CFG_GPIO_IORST);
GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
udelay (10000);
GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
udelay (10000);
GPIO_OUTPUT_SET (CFG_GPIO_IORST);
GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
return 0;
}

32
board/actux4/actux4_hw.h
View File

@ -29,21 +29,21 @@
/*
* GPIO settings
*/
#define CFG_GPIO_USBINTA 0
#define CFG_GPIO_USBINTB 1
#define CFG_GPIO_USBINTC 2
#define CFG_GPIO_nPWRON 3 /* Out */
#define CFG_GPIO_I2C_SCL 4
#define CFG_GPIO_I2C_SDA 5
#define CFG_GPIO_PCI_INTB 6
#define CFG_GPIO_BUTTON1 7
#define CFG_GPIO_LED1 8 /* Out */
#define CFG_GPIO_RTCINT 9
#define CFG_GPIO_LED2 10 /* Out */
#define CFG_GPIO_PCI_INTA 11
#define CFG_GPIO_IORST 12 /* Out */
#define CFG_GPIO_LED3 13 /* Out */
#define CFG_GPIO_PCI_CLK 14 /* Out */
#define CFG_GPIO_EXTBUS_CLK 15 /* Out */
#define CONFIG_SYS_GPIO_USBINTA 0
#define CONFIG_SYS_GPIO_USBINTB 1
#define CONFIG_SYS_GPIO_USBINTC 2
#define CONFIG_SYS_GPIO_nPWRON 3 /* Out */
#define CONFIG_SYS_GPIO_I2C_SCL 4
#define CONFIG_SYS_GPIO_I2C_SDA 5
#define CONFIG_SYS_GPIO_PCI_INTB 6
#define CONFIG_SYS_GPIO_BUTTON1 7
#define CONFIG_SYS_GPIO_LED1 8 /* Out */
#define CONFIG_SYS_GPIO_RTCINT 9
#define CONFIG_SYS_GPIO_LED2 10 /* Out */
#define CONFIG_SYS_GPIO_PCI_INTA 11
#define CONFIG_SYS_GPIO_IORST 12 /* Out */
#define CONFIG_SYS_GPIO_LED3 13 /* Out */
#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
#endif

10
board/adder/adder.c
View File

@ -68,7 +68,7 @@ static uint sdram_table[] = {
phys_size_t initdram (int board_type)
{
long int msize;
volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;
volatile immap_t *immap = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
@ -76,7 +76,7 @@ phys_size_t initdram (int board_type)
/* Configure SDRAM refresh */
memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
memctl->memc_mamr = (94 << 24) | CFG_MAMR; /* No refresh */
memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */
udelay(200);
/* Run precharge from location 0x15 */
@ -94,10 +94,10 @@ phys_size_t initdram (int board_type)
udelay(200);
memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */
memctl->memc_or1 = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
memctl->memc_br1 = CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
memctl->memc_or1 |= ~(msize - 1);
return msize;

134
board/ads5121/ads5121.c
View File

@ -53,16 +53,16 @@ long int fixed_sdram(void);
int board_early_init_f (void)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 lpcaw;
/*
* Initialize Local Window for the CPLD registers access (CS2 selects
* the CPLD chip)
*/
im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
im->lpc.cs_cfg[2] = CFG_CS2_CFG;
im->sysconf.lpcs2aw = CSAW_START(CONFIG_SYS_CPLD_BASE) |
CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE);
im->lpc.cs_cfg[2] = CONFIG_SYS_CS2_CFG;
/*
* According to MPC5121e RM, configuring local access windows should
@ -80,21 +80,21 @@ int board_early_init_f (void)
*/
#ifdef CONFIG_ADS5121_REV2
*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
#else
if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) {
*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
if (*((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
} else {
/* running from Backup flash */
*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32;
*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0x32;
}
#endif
/*
* Configure Flash Speed
*/
*((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG;
*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS0_CONFIG)) = CONFIG_SYS_CS0_CFG;
if (SVR_MJREV (im->sysconf.spridr) >= 2) {
*((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CFG_CS_ALETIMING;
*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CONFIG_SYS_CS_ALETIMING;
}
/*
* Enable clocks
@ -120,8 +120,8 @@ phys_size_t initdram (int board_type)
*/
long int fixed_sdram (void)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u32 msize = CFG_DDR_SIZE * 1024 * 1024;
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2 (msize);
u32 i;
@ -129,7 +129,7 @@ long int fixed_sdram (void)
im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR;
/* Initialize DDR Local Window */
im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
im->sysconf.ddrlaw.bar = CONFIG_SYS_DDR_BASE & 0xFFFFF000;
im->sysconf.ddrlaw.ar = msize_log2 - 1;
/*
@ -141,68 +141,68 @@ long int fixed_sdram (void)
__asm__ __volatile__ ("isync");
/* Enable DDR */
im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;
im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN;
/* Initialize DDR Priority Manager */
im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1;
im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2;
im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG;
im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU;
im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML;
im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU;
im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML;
im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU;
im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML;
im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU;
im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML;
im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU;
im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML;
im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU;
im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL;
im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU;
im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL;
im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU;
im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL;
im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU;
im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL;
im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU;
im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL;
/* Initialize MDDRC */
im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;
im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG;
im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1;
im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2;
/* Initialize DDR */
for (i = 0; i < 10; i++)
im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CFG_MICRON_RFSH;
im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CFG_MICRON_RFSH;
im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CFG_MICRON_EM2;
im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CFG_MICRON_EM2;
im->mddrc.ddr_command = CFG_MICRON_EM3;
im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CFG_MICRON_RFSH;
im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
/* Start MDDRC */
im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;
im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN;
im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN;
return msize;
}
@ -292,8 +292,8 @@ static iopin_t ioregs_init[] = {
int checkboard (void)
{
ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
brd_rev, cpld_rev);

4
board/ads5121/ads5121_diu.c
View File

@ -43,7 +43,7 @@ static int xres, yres;
void diu_set_pixel_clock(unsigned int pixclock)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile clk512x_t *clk = &immap->clk;
volatile unsigned int *clkdvdr = &clk->scfr[0];
unsigned long speed_ccb, temp, pixval;
@ -100,7 +100,7 @@ int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
}
U_BOOT_CMD(
diufb, CFG_MAXARGS, 1, ads5121diu_init_show_bmp,
diufb, CONFIG_SYS_MAXARGS, 1, ads5121diu_init_show_bmp,
"diufb init | addr - Init or Display BMP file\n",
"init\n - initialize DIU\n"
"addr\n - display bmp at address 'addr'\n"

44
board/ads5121/pci.c
View File

@ -33,8 +33,8 @@
DECLARE_GLOBAL_DATA_PTR;
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
static struct pci_controller pci_hose;
@ -46,7 +46,7 @@ static struct pci_controller pci_hose;
void
pci_init_board(void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile law512x_t *pci_law;
volatile pot512x_t *pci_pot;
volatile pcictrl512x_t *pci_ctrl;
@ -87,10 +87,10 @@ pci_init_board(void)
/*
* Configure PCI Local Access Windows
*/
pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
/*
@ -98,18 +98,18 @@ pci_init_board(void)
*/
/* PCI mem space - prefetch */
pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M;
/* PCI IO space */
pci_pot[1].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[1].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[1].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[1].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
/* PCI mmio - non-prefetch mem space */
pci_pot[2].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[2].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[2].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[2].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
/*
@ -129,23 +129,23 @@ pci_init_board(void)
/* PCI memory prefetch space */
pci_set_region(hose->regions + 0,
CFG_PCI_MEM_BASE,
CFG_PCI_MEM_PHYS,
CFG_PCI_MEM_SIZE,
CONFIG_SYS_PCI_MEM_BASE,
CONFIG_SYS_PCI_MEM_PHYS,
CONFIG_SYS_PCI_MEM_SIZE,
PCI_REGION_MEM|PCI_REGION_PREFETCH);
/* PCI memory space */
pci_set_region(hose->regions + 1,
CFG_PCI_MMIO_BASE,
CFG_PCI_MMIO_PHYS,
CFG_PCI_MMIO_SIZE,
CONFIG_SYS_PCI_MMIO_BASE,
CONFIG_SYS_PCI_MMIO_PHYS,
CONFIG_SYS_PCI_MMIO_SIZE,
PCI_REGION_MEM);
/* PCI IO space */
pci_set_region(hose->regions + 2,
CFG_PCI_IO_BASE,
CFG_PCI_IO_PHYS,
CFG_PCI_IO_SIZE,
CONFIG_SYS_PCI_IO_BASE,
CONFIG_SYS_PCI_IO_PHYS,
CONFIG_SYS_PCI_IO_SIZE,
PCI_REGION_IO);
/* System memory space */
@ -158,8 +158,8 @@ pci_init_board(void)
hose->region_count = 4;
pci_setup_indirect(hose,
(CFG_IMMR + 0x8300),
(CFG_IMMR + 0x8304));
(CONFIG_SYS_IMMR + 0x8300),
(CONFIG_SYS_IMMR + 0x8304));
pci_register_hose(hose);

40
board/alaska/alaska.c
View File

@ -32,48 +32,48 @@ void setupBat (ulong size)
int blocksize = 0;
/* Flash 0 */
#if defined (CFG_AMD_BOOT)
batu = CFG_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
#if defined (CONFIG_SYS_AMD_BOOT)
batu = CONFIG_SYS_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
#else
batu = CFG_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
batu = CONFIG_SYS_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
#endif
batl = CFG_FLASH0_BASE | 0x22;
batl = CONFIG_SYS_FLASH0_BASE | 0x22;
write_bat (IBAT0, batu, batl);
write_bat (DBAT0, batu, batl);
/* Flash 1 */
#if defined (CFG_AMD_BOOT)
batu = CFG_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
#if defined (CONFIG_SYS_AMD_BOOT)
batu = CONFIG_SYS_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
#else
batu = CFG_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
batu = CONFIG_SYS_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
#endif
batl = CFG_FLASH1_BASE | 0x22;
batl = CONFIG_SYS_FLASH1_BASE | 0x22;
write_bat (IBAT1, batu, batl);
write_bat (DBAT1, batu, batl);
/* CPLD */
batu = CFG_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
batl = CFG_CPLD_BASE | 0x22;
batu = CONFIG_SYS_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
batl = CONFIG_SYS_CPLD_BASE | 0x22;
write_bat (IBAT2, 0, 0);
write_bat (DBAT2, batu, batl);
/* FPGA */
batu = CFG_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
batl = CFG_FPGA_BASE | 0x22;
batu = CONFIG_SYS_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
batl = CONFIG_SYS_FPGA_BASE | 0x22;
write_bat (IBAT3, 0, 0);
write_bat (DBAT3, batu, batl);
/* MBAR - Data only */
batu = CFG_MBAR | BPP_RW | BPP_RX;
batl = CFG_MBAR | 0x22;
batu = CONFIG_SYS_MBAR | BPP_RW | BPP_RX;
batl = CONFIG_SYS_MBAR | 0x22;
mtspr (IBAT4L, 0);
mtspr (IBAT4U, 0);
mtspr (DBAT4L, batl);
mtspr (DBAT4U, batu);
/* MBAR - SRAM */
batu = CFG_SRAM_BASE | BPP_RW | BPP_RX;
batl = CFG_SRAM_BASE | 0x42;
batu = CONFIG_SYS_SRAM_BASE | BPP_RW | BPP_RX;
batl = CONFIG_SYS_SRAM_BASE | 0x42;
mtspr (IBAT5L, batl);
mtspr (IBAT5U, batu);
mtspr (DBAT5L, batl);
@ -93,8 +93,8 @@ void setupBat (ulong size)
blocksize = BL_256M << 2;
/* Memory */
batu = CFG_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
batl = CFG_SDRAM_BASE | 0x42;
batu = CONFIG_SYS_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
batl = CONFIG_SYS_SDRAM_BASE | 0x42;
mtspr (IBAT6L, batl);
mtspr (IBAT6U, batu);
mtspr (DBAT6L, batl);
@ -120,9 +120,9 @@ void setupBat (ulong size)
else if (size <= 0x10000000) /* 256MB */
blocksize = BL_256M << 2;
batu = (CFG_SDRAM_BASE +
batu = (CONFIG_SYS_SDRAM_BASE +
0x10000000) | blocksize | BPP_RW | BPP_RX;
batl = (CFG_SDRAM_BASE + 0x10000000) | 0x42;
batl = (CONFIG_SYS_SDRAM_BASE + 0x10000000) | 0x42;
}
mtspr (IBAT7L, batl);

76
board/alaska/flash.c
View File

@ -28,7 +28,7 @@
#include <linux/byteorder/swab.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Board support for 1 or 2 flash devices */
#define FLASH_PORT_WIDTH8
@ -86,30 +86,30 @@ unsigned long flash_init (void)
ulong size = 0;
ulong fsize = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
memset (&flash_info[i], 0, sizeof (flash_info_t));
switch (i) {
case 0:
flash_get_size ((FPW *) CFG_FLASH1_BASE,
flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
&flash_info[i]);
flash_get_offsets (CFG_FLASH1_BASE, &flash_info[i]);
flash_get_offsets (CONFIG_SYS_FLASH1_BASE, &flash_info[i]);
break;
case 1:
flash_get_size ((FPW *) CFG_FLASH1_BASE,
flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
&flash_info[i]);
fsize = CFG_FLASH1_BASE + flash_info[i - 1].size;
fsize = CONFIG_SYS_FLASH1_BASE + flash_info[i - 1].size;
flash_get_offsets (fsize, &flash_info[i]);
break;
case 2:
flash_get_size ((FPW *) CFG_FLASH0_BASE,
flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
&flash_info[i]);
flash_get_offsets (CFG_FLASH0_BASE, &flash_info[i]);
flash_get_offsets (CONFIG_SYS_FLASH0_BASE, &flash_info[i]);
break;
case 3:
flash_get_size ((FPW *) CFG_FLASH0_BASE,
flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
&flash_info[i]);
fsize = CFG_FLASH0_BASE + flash_info[i - 1].size;
fsize = CONFIG_SYS_FLASH0_BASE + flash_info[i - 1].size;
flash_get_offsets (fsize, &flash_info[i]);
break;
default:
@ -124,23 +124,23 @@ unsigned long flash_init (void)
/* Protect monitor and environment sectors
*/
#if defined (CFG_AMD_BOOT)
#if defined (CONFIG_SYS_AMD_BOOT)
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[2]);
flash_protect (FLAG_PROTECT_SET,
CFG_INTEL_BASE,
CFG_INTEL_BASE + monitor_flash_len - 1,
CONFIG_SYS_INTEL_BASE,
CONFIG_SYS_INTEL_BASE + monitor_flash_len - 1,
&flash_info[1]);
#else
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[3]);
flash_protect (FLAG_PROTECT_SET,
CFG_AMD_BASE,
CFG_AMD_BASE + monitor_flash_len - 1, &flash_info[0]);
CONFIG_SYS_AMD_BASE,
CONFIG_SYS_AMD_BASE + monitor_flash_len - 1, &flash_info[0]);
#endif
flash_protect (FLAG_PROTECT_SET,
@ -294,10 +294,10 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
break;
}
if (info->sector_count > CFG_MAX_FLASH_SECT) {
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CFG_MAX_FLASH_SECT);
info->sector_count = CFG_MAX_FLASH_SECT;
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
if (value == (FPW) INTEL_ID_28F128J3A)
@ -348,7 +348,7 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
/*
* first, wait for the WSM to be finished. The rationale for
* waiting for the WSM to become idle for at most
* CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
* CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
* because of: (1) erase, (2) program or (3) lock bit
* configuration. So we just wait for the longest timeout of
* the (1)-(3), i.e. the erase timeout.
@ -361,7 +361,7 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
start = get_timer (0);
while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
*addr = (FPW) INTEL_RESET; /* restore read mode */
printf("WSM busy too long, can't get prot status\n");
return 1;
@ -391,7 +391,7 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
*/
static unsigned char same_chip_banks (int bank1, int bank2)
{
unsigned char same_chip[CFG_MAX_FLASH_BANKS][CFG_MAX_FLASH_BANKS] = {
unsigned char same_chip[CONFIG_SYS_MAX_FLASH_BANKS][CONFIG_SYS_MAX_FLASH_BANKS] = {
{1, 1, 0, 0},
{1, 1, 0, 0},
{0, 0, 1, 1},
@ -467,7 +467,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
} else {
FPWV *base; /* first address in bank */
base = (FPWV *) (CFG_AMD_BASE);
base = (FPWV *) (CONFIG_SYS_AMD_BASE);
base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */
@ -479,7 +479,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
if (intel) {
*addr = (FPW) 0x00B000B0; /* suspend erase */
@ -684,7 +684,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data)
/* wait while polling the status register */
while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
@ -728,7 +728,7 @@ static int write_data_block (flash_info_t * info, ulong src, ulong dest)
/* wait while polling the status register */
while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
@ -746,7 +746,7 @@ static int write_data_block (flash_info_t * info, ulong src, ulong dest)
/* wait while polling the status register */
while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
@ -779,7 +779,7 @@ static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
return (2);
}
base = (FPWV *) (CFG_AMD_BASE);
base = (FPWV *) (CONFIG_SYS_AMD_BASE);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
@ -799,7 +799,7 @@ static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
/* data polling for D7 */
while (res == 0
&& (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (FPW) 0x00F000F0; /* reset bank */
res = 1;
}
@ -856,7 +856,7 @@ int flash_real_protect (flash_info_t * info, long sector, int prot)
start = get_timer (0);
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) {
if (get_timer (start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
printf ("Flash lock bit operation timed out\n");
rc = 1;
break;
@ -886,17 +886,17 @@ int flash_real_protect (flash_info_t * info, long sector, int prot)
*/
/* find the current bank number */
curr_bank = CFG_MAX_FLASH_BANKS + 1;
for (j = 0; j < CFG_MAX_FLASH_BANKS; ++j) {
curr_bank = CONFIG_SYS_MAX_FLASH_BANKS + 1;
for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; ++j) {
if (&flash_info[j] == info) {
curr_bank = j;
}
}
if (curr_bank == CFG_MAX_FLASH_BANKS + 1) {
if (curr_bank == CONFIG_SYS_MAX_FLASH_BANKS + 1) {
printf("Error: can't determine bank number!\n");
}
for (bank = 0; bank < CFG_MAX_FLASH_BANKS; ++bank) {
for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
if (!same_chip_banks(curr_bank, bank)) {
continue;
}
@ -910,7 +910,7 @@ int flash_real_protect (flash_info_t * info, long sector, int prot)
while ((*addr & INTEL_FINISHED) !=
INTEL_FINISHED) {
if (get_timer (start) >
CFG_FLASH_UNLOCK_TOUT) {
CONFIG_SYS_FLASH_UNLOCK_TOUT) {
printf ("Flash lock bit operation timed out\n");
rc = 1;
break;

14
board/altera/common/AMDLV065D.c
View File

@ -30,7 +30,7 @@
#endif
#define SECTSZ (64 * 1024)
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
/*----------------------------------------------------------------------*/
unsigned long flash_init (void)
@ -39,18 +39,18 @@ unsigned long flash_init (void)
unsigned long addr;
flash_info_t *fli = &flash_info[0];
fli->size = CFG_FLASH_SIZE;
fli->sector_count = CFG_MAX_FLASH_SECT;
fli->size = CONFIG_SYS_FLASH_SIZE;
fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
addr = CFG_FLASH_BASE;
addr = CONFIG_SYS_FLASH_BASE;
for (i = 0; i < fli->sector_count; ++i) {
fli->start[i] = addr;
addr += SECTSZ;
fli->protect[i] = 1;
}
return (CFG_FLASH_SIZE);
return (CONFIG_SYS_FLASH_SIZE);
}
/*--------------------------------------------------------------------*/
void flash_print_info (flash_info_t * info)
@ -135,7 +135,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
while ( readb (addr2) != 0xff) {
udelay (1000 * 1000);
putc ('.');
if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("timeout\n");
return 1;
}
@ -177,7 +177,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
/* Verify write */
start = get_timer (0);
while (readb (dst) != b) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return 1;
}
}

6
board/altera/common/epled.c
View File

@ -33,7 +33,7 @@ static led_id_t val = 0;
void __led_init (led_id_t mask, int state)
{
nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
if (state == STATUS_LED_ON)
val &= ~mask;
@ -44,7 +44,7 @@ void __led_init (led_id_t mask, int state)
void __led_set (led_id_t mask, int state)
{
nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
if (state == STATUS_LED_ON)
val &= ~mask;
@ -55,7 +55,7 @@ void __led_set (led_id_t mask, int state)
void __led_toggle (led_id_t mask)
{
nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
val ^= mask;
writel (&pio->data, val);

12
board/altera/common/flash.c
View File

@ -25,7 +25,7 @@
#include <common.h>
#include <nios.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
/*--------------------------------------------------------------------*/
void flash_print_info (flash_info_t * info)
@ -68,8 +68,8 @@ void flash_print_info (flash_info_t * info)
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
volatile CFG_FLASH_WORD_SIZE *addr2;
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
int prot, sect;
unsigned oldpri;
ulong start;
@ -112,7 +112,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
*/
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
*addr = 0xaa;
*addr = 0x55;
*addr = 0x80;
@ -128,7 +128,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
while (*addr2 != 0xff) {
udelay (1000 * 1000);
putc ('.');
if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("timeout\n");
return 1;
}
@ -181,7 +181,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
/* Verify write */
start = get_timer (0);
while (*dst != b) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
ipri (oldpri);
return 1;
}

6
board/altera/dk1c20/dk1c20.c
View File

@ -58,9 +58,9 @@ phys_size_t initdram (int board_type)
#if defined(CONFIG_CMD_IDE)
int ide_preinit (void)
{
nios_pio_t *present = (nios_pio_t *) CFG_CF_PRESENT;
nios_pio_t *power = (nios_pio_t *) CFG_CF_POWER;
nios_pio_t *atasel = (nios_pio_t *) CFG_CF_ATASEL;
nios_pio_t *present = (nios_pio_t *) CONFIG_SYS_CF_PRESENT;
nios_pio_t *power = (nios_pio_t *) CONFIG_SYS_CF_POWER;
nios_pio_t *atasel = (nios_pio_t *) CONFIG_SYS_CF_ATASEL;
/* setup data direction registers */
present->direction = NIOS_PIO_IN;

8
board/altera/dk1c20/flash.c
View File

@ -31,7 +31,7 @@
#include "../common/flash.c"
/*----------------------------------------------------------------------*/
#define BANKSZ CFG_FLASH_SIZE
#define BANKSZ CONFIG_SYS_FLASH_SIZE
#define SECTSZ (64 * 1024)
#define USERFLASH (2 * 1024 * 1024) /* bottom 2 MB for user */
@ -43,16 +43,16 @@ unsigned long flash_init (void)
flash_info_t *fli = &flash_info[0];
fli->size = BANKSZ;
fli->sector_count = CFG_MAX_FLASH_SECT;
fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
addr = CFG_FLASH_BASE;
addr = CONFIG_SYS_FLASH_BASE;
for (i = 0; i < fli->sector_count; ++i) {
fli->start[i] = addr;
addr += SECTSZ;
/* Protect all but 2 MByte user area */
if (addr < (CFG_FLASH_BASE + USERFLASH))
if (addr < (CONFIG_SYS_FLASH_BASE + USERFLASH))
fli->protect[i] = 0;
else
fli->protect[i] = 1;

6
board/altera/dk1s10/flash.c
View File

@ -43,16 +43,16 @@ unsigned long flash_init (void)
flash_info_t *fli = &flash_info[0];
fli->size = BANKSZ;
fli->sector_count = CFG_MAX_FLASH_SECT;
fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
addr = CFG_FLASH_BASE;
addr = CONFIG_SYS_FLASH_BASE;
for (i = 0; i < fli->sector_count; ++i) {
fli->start[i] = addr;
addr += SECTSZ;
/* Protect all but 2 MByte user area */
if (addr < (CFG_FLASH_BASE + USERFLASH))
if (addr < (CONFIG_SYS_FLASH_BASE + USERFLASH))
fli->protect[i] = 0;
else
fli->protect[i] = 1;

8
board/altera/dk1s10/vectors.S
View File

@ -58,12 +58,12 @@
.align 4
_vectors:
#if defined(CFG_NIOS_CPU_OCI_BASE)
#if defined(CONFIG_SYS_NIOS_CPU_OCI_BASE)
/* OCI does the reset job */
.long _def_xhandler@h /* Vector 0 - NMI / Reset */
#else
/* there is no OCI, so we have to do a direct reset jump here */
.long CFG_NIOS_CPU_RST_VECT /* Vector 0 - Reset to GERMS */
.long CONFIG_SYS_NIOS_CPU_RST_VECT /* Vector 0 - Reset to GERMS */
#endif
.long _cwp_lolimit@h /* Vector 1 - underflow */
.long _cwp_hilimit@h /* Vector 2 - overflow */
@ -81,7 +81,7 @@ _vectors:
.long _def_xhandler@h /* Vector 13 - future reserved */
.long _def_xhandler@h /* Vector 14 - future reserved */
.long _def_xhandler@h /* Vector 15 - future reserved */
#if (CFG_NIOS_TMRIRQ == 16)
#if (CONFIG_SYS_NIOS_TMRIRQ == 16)
.long _timebase_int@h /* Vector 16 - lopri timer*/
#else
.long _def_xhandler@h /* Vector 16 */
@ -119,7 +119,7 @@ _vectors:
.long _def_xhandler@h /* Vector 47 */
.long _def_xhandler@h /* Vector 48 */
.long _def_xhandler@h /* Vector 49 */
#if (CFG_NIOS_TMRIRQ == 50)
#if (CONFIG_SYS_NIOS_TMRIRQ == 50)
.long _timebase_int@h /* Vector 50 - lopri timer*/
#else
.long _def_xhandler@h /* Vector 50 */

34
board/amcc/acadia/acadia.c
View File

@ -31,24 +31,24 @@ static void acadia_gpio_init(void)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */
out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */
out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */
out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */
/*
* Ultra (405EZ) was nice enough to add another GPIO controller
*/
out32(GPIO1_OSRH, CFG_GPIO1_OSRH); /* output select */
out32(GPIO1_OSRL, CFG_GPIO1_OSRL);
out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H); /* input select */
out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L);
out32(GPIO1_TSRH, CFG_GPIO1_TSRH); /* three-state select */
out32(GPIO1_TSRL, CFG_GPIO1_TSRL);
out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */
out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH); /* output select */
out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL);
out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H); /* input select */
out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L);
out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH); /* three-state select */
out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL);
out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR); /* enable output driver for outputs */
}
int board_early_init_f(void)
@ -68,7 +68,7 @@ int board_early_init_f(void)
mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
mfsdr(sdrultra0, reg);
reg &= ~SDR_ULTRA0_CSN_MASK;
reg |= (SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS) |
reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
SDR_ULTRA0_NDGPIOBP |
SDR_ULTRA0_EBCRDYEN |
SDR_ULTRA0_NFSRSTEN;
@ -91,7 +91,7 @@ int board_early_init_f(void)
int misc_init_f(void)
{
/* Set EPLD to take PHY out of reset */
out8(CFG_CPLD_BASE + 0x05, 0x00);
out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00);
udelay(100000);
return 0;
@ -105,7 +105,7 @@ int checkboard(void)
char *s = getenv("serial#");
u8 rev;
rev = in8(CFG_CPLD_BASE + 0);
rev = in8(CONFIG_SYS_CPLD_BASE + 0);
printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev);
if (s != NULL) {

2
board/amcc/acadia/cmd_acadia.c
View File

@ -84,7 +84,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (i2c_write(chip, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", chip);
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0)
printf("Error2 writing to EEPROM at address 0x%x\n", chip);

18
board/amcc/acadia/memory.c
View File

@ -39,7 +39,7 @@ static void cram_bcr_write(u32 wr_val)
wr_val <<= 2;
/* set CRAM_CRE to 1 */
gpio_write_bit(CFG_GPIO_CRAM_CRE, 1);
gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1);
/* Write BCR to CRAM on CS1 */
out32(wr_val + 0x00200000, 0);
@ -53,7 +53,7 @@ static void cram_bcr_write(u32 wr_val)
eieio();
/* set CRAM_CRE back to 0 (normal operation) */
gpio_write_bit(CFG_GPIO_CRAM_CRE, 0);
gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0);
return;
}
@ -75,10 +75,10 @@ phys_size_t initdram(int board_type)
u32 val;
/* 1. EBC need to program READY, CLK, ADV for ASync mode */
gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
/* 2. EBC in Async mode */
mtebc(pb1ap, 0x078F1EC0);
@ -94,8 +94,8 @@ phys_size_t initdram(int board_type)
mtebc(pb2ap, 0x9C0201C0);
/* Set GPIO pins back to alternate function */
gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
/* Config EBC to use RDY */
mfsdr(sdrultra0, val);
@ -106,5 +106,5 @@ phys_size_t initdram(int board_type)
;
#endif
return (CFG_MBYTES_RAM << 20);
return (CONFIG_SYS_MBYTES_RAM << 20);
}

22
board/amcc/bamboo/bamboo.c
View File

@ -462,7 +462,7 @@ phys_size_t initdram (int board_type)
return dram_size;
#else
return CFG_MBYTES_SDRAM << 20;
return CONFIG_SYS_MBYTES_SDRAM << 20;
#endif
}
@ -529,7 +529,7 @@ int pci_pre_init(struct pci_controller *hose)
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
@ -543,14 +543,14 @@ void pci_target_init(struct pci_controller *hose)
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
@ -565,8 +565,8 @@ void pci_target_init(struct pci_controller *hose)
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
CFG_PCI_SUBSYS_VENDORID);
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
CONFIG_SYS_PCI_SUBSYS_VENDORID);
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
/* Configure command register as bus master */
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
@ -580,13 +580,13 @@ void pci_target_init(struct pci_controller *hose)
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
@ -601,7 +601,7 @@ void pci_master_init(struct pci_controller *hose)
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
/*************************************************************************
* is_pci_host

2
board/amcc/bamboo/config.mk
View File

@ -34,5 +34,5 @@ PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif

12
board/amcc/bamboo/flash.c
View File

@ -45,12 +45,12 @@
#define DEBUGF(x...)
#endif /* DEBUG */
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*
* Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
*/
static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
{0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
{0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */
{0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash */
@ -79,7 +79,7 @@ static int write_word(flash_info_t * info, ulong dest, ulong data);
unsigned long flash_init(void)
{
unsigned long total_b = 0;
unsigned long size_b[CFG_MAX_FLASH_BANKS];
unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
unsigned short index = 0;
int i;
unsigned long val;
@ -128,7 +128,7 @@ unsigned long flash_init(void)
DEBUGF("FLASH: Index: %d\n", index);
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
@ -150,8 +150,8 @@ unsigned long flash_init(void)
}
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
&flash_info[i]);
#if defined(CONFIG_ENV_IS_IN_FLASH)
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,

28
board/amcc/bamboo/init.S
View File

@ -48,29 +48,29 @@ tlbtab:
* speed up boot process. It is patched after relocation to enable SA_I
*/
#ifndef CONFIG_NAND_SPL
tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
#else
tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
#endif
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
/* PCI base & peripherals */
tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
tlbentry(CFG_NAND_ADDR, SZ_4K, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
/* PCI */
tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I)
/* USB 2.0 Device */
tlbentry(CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I)
tlbtab_end
@ -79,8 +79,8 @@ tlbtab:
* For NAND booting the first TLB has to be reconfigured to full size
* and with caching disabled after running from RAM!
*/
#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 0)
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
.globl reconfig_tlb0

16
board/amcc/bubinga/flash.c
View File

@ -32,7 +32,7 @@
#include <ppc4xx.h>
#include <asm/processor.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
#undef DEBUG
#ifdef DEBUG
@ -60,7 +60,7 @@ unsigned long flash_init(void)
unsigned long base_b0, base_b1;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@ -75,14 +75,14 @@ unsigned long flash_init(void)
}
/* Only one bank */
if (CFG_MAX_FLASH_BANKS == 1) {
if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
/* Setup offsets */
flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
&flash_info[0]);
#ifdef CONFIG_ENV_IS_IN_FLASH
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
@ -133,7 +133,7 @@ unsigned long flash_init(void)
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
base_b0 + size_b0 - CFG_MONITOR_LEN,
base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN,
base_b0 + size_b0 - 1, &flash_info[0]);
/* Also protect sector containing initial power-up instruction */
/* (flash_protect() checks address range - other call ignored) */
@ -151,12 +151,12 @@ unsigned long flash_init(void)
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
base_b1 + size_b1 - CFG_MONITOR_LEN,
base_b1 + size_b1 - CONFIG_SYS_MONITOR_LEN,
base_b1 + size_b1 - 1,
&flash_info[1]);
/* monitor protection OFF by default (one is enough) */
(void)flash_protect(FLAG_PROTECT_CLEAR,
base_b0 + size_b0 - CFG_MONITOR_LEN,
base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN,
base_b0 + size_b0 - 1,
&flash_info[0]);
} else {

2
board/amcc/canyonlands/bootstrap.c
View File

@ -168,7 +168,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
printf("Done\n");
printf("Please power-cycle the board for the changes to take effect\n");

48
board/amcc/canyonlands/canyonlands.c
View File

@ -29,11 +29,11 @@
#include <asm/4xx_pcie.h>
#include <asm/gpio.h>
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
DECLARE_GLOBAL_DATA_PTR;
#define CFG_BCSR3_PCIE 0x10
#define CONFIG_SYS_BCSR3_PCIE 0x10
#define BOARD_CANYONLANDS_PCIE 1
#define BOARD_CANYONLANDS_SATA 2
@ -86,7 +86,7 @@ int board_early_init_f(void)
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_NDFC_BAC_ENCODE(3) |
(0x80000000 >> (28 + CFG_NAND_CS));
(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
mtsdr(SDR0_CUST0, sdr0_cust0);
/*
@ -99,13 +99,13 @@ int board_early_init_f(void)
mtsdr(SDR0_PCI0, 0xe0000000);
/* Enable ethernet and take out of reset */
out_8((void *)CFG_BCSR_BASE + 6, 0);
out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
out_8((void *)CFG_BCSR_BASE + 5, 0);
out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
/* Enable USB host & USB-OTG */
out_8((void *)CFG_BCSR_BASE + 7, 0);
out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
@ -158,7 +158,7 @@ int checkboard(void)
gd->board_type = BOARD_GLACIER;
} else {
printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
if (in_8((void *)(CFG_BCSR_BASE + 3)) & CFG_BCSR3_PCIE)
if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
gd->board_type = BOARD_CANYONLANDS_PCIE;
else
gd->board_type = BOARD_CANYONLANDS_SATA;
@ -175,7 +175,7 @@ int checkboard(void)
break;
}
printf(", Rev. %X", in_8((void *)(CFG_BCSR_BASE + 0)));
printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
if (s != NULL) {
puts(", serial# ");
@ -208,7 +208,7 @@ u32 ddr_clktr(u32 default_val) {
*/
phys_size_t initdram(int board_type)
{
return CFG_MBYTES_SDRAM << 20;
return CONFIG_SYS_MBYTES_SDRAM << 20;
}
#endif
@ -219,7 +219,7 @@ phys_size_t initdram(int board_type)
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
/*
@ -234,7 +234,7 @@ void pci_target_init(struct pci_controller * hose )
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*/
out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
out_le32((void *)PCIX0_PIM0LAH, 0);
out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
out_le32((void *)PCIX0_BAR0, 0);
@ -242,12 +242,12 @@ void pci_target_init(struct pci_controller * hose )
/*
* Program the board's subsystem id/vendor id
*/
out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#if defined(CONFIG_PCI)
/*
@ -314,9 +314,9 @@ void pcie_setup_hoses(int busno)
/* setup mem resource */
pci_set_region(hose->regions + 0,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMSIZE,
PCI_REGION_MEM);
hose->region_count = 1;
pci_register_hose(hose);
@ -362,16 +362,16 @@ int board_early_init_r (void)
/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
mtebc(pb3cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#else
mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#endif
/* Remove TLB entry of boot EBC mapping */
remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);
remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
TLB_WORD2_I_ENABLE);
/*
@ -427,9 +427,9 @@ int misc_init_r(void)
* Disable square wave output: Batterie will be drained
* quickly, when this output is not disabled
*/
val = i2c_reg_read(CFG_I2C_RTC_ADDR, 0xa);
val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
val &= ~0x40;
i2c_reg_write(CFG_I2C_RTC_ADDR, 0xa, val);
i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
return 0;
}
@ -445,7 +445,7 @@ void ft_board_setup(void *blob, bd_t *bd)
/* Fixup NOR mapping */
val[0] = 0; /* chip select number */
val[1] = 0; /* always 0 */
val[2] = CFG_FLASH_BASE_PHYS_L; /* we fixed up this address */
val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L; /* we fixed up this address */
val[3] = gd->bd->bi_flashsize;
rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
val, sizeof(val), 1);

2
board/amcc/canyonlands/config.mk
View File

@ -37,5 +37,5 @@ PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif

40
board/amcc/canyonlands/init.S
View File

@ -47,10 +47,10 @@ tlbtab:
* enable SA_I
*/
#ifndef CONFIG_NAND_SPL
tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
#else
tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
#endif
@ -60,37 +60,37 @@ tlbtab:
* routine.
*/
#ifdef CFG_INIT_RAM_DCACHE
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
#endif
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
/* PCIe UTL register */
tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
/* TLB-entry for NAND */
tlbentry(CFG_NAND_ADDR, SZ_16M, CFG_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
/* TLB-entry for CPLD */
tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
/* TLB-entry for OCM */
tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CONFIG_SYS_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
/* TLB-entry for Local Configuration registers => peripherals */
tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
/* AHB: Internal USB Peripherals (USB, SATA) */
tlbentry(CFG_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbtab_end
@ -99,8 +99,8 @@ tlbtab:
* For NAND booting the first TLB has to be reconfigured to full size
* and with caching disabled after running from RAM!
*/
#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1)
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
.globl reconfig_tlb0

234
board/amcc/common/flash.c
View File

@ -35,13 +35,13 @@
#include <ppc4xx.h>
#include <asm/processor.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static int write_word(flash_info_t * info, ulong dest, ulong data);
#ifdef CFG_FLASH_2ND_16BIT_DEV
#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
static int write_word_1(flash_info_t * info, ulong dest, ulong data);
static int write_word_2(flash_info_t * info, ulong dest, ulong data);
static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
@ -171,7 +171,7 @@ void flash_print_info(flash_info_t * info)
/*
* The following code cannot be run from FLASH!
*/
#ifdef CFG_FLASH_2ND_16BIT_DEV
#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
static ulong flash_get_size(vu_long * addr, flash_info_t * info)
{
/* bit 0 used for big flash marking */
@ -188,32 +188,32 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
#endif
{
short i;
CFG_FLASH_WORD_SIZE value;
CONFIG_SYS_FLASH_WORD_SIZE value;
ulong base = (ulong) addr;
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
/* Write auto select command: read Manufacturer ID */
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
udelay(1000);
value = addr2[0];
DEBUGF("FLASH MANUFACT: %x\n", value);
switch (value) {
case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
info->flash_id = FLASH_MAN_SST;
break;
case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
info->flash_id = FLASH_MAN_STM;
break;
default:
@ -227,67 +227,67 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
DEBUGF("\nFLASH DEVICEID: %x\n", value);
switch (value) {
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 512 KiB */
break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 512 KiB */
break;
case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 512 KiB */
break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D:
info->flash_id += FLASH_AMD016;
info->sector_count = 32;
info->size = 0x00200000; /* => 2 MiB */
break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C:
info->flash_id += FLASH_AMDLV033C;
info->sector_count = 64;
info->size = 0x00400000; /* => 4 MiB */
break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00080000; /* => 512 KiB */
break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00080000; /* => 512 KiB */
break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000; /* => 1 MiB */
break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00100000; /* => 1 MiB */
break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00200000; /* => 2 MiB */
break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00200000; /* => 2 MiB */
@ -331,14 +331,14 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
/* For AMD29033C flash we need to resend the command of *
* reading flash protection for upper 8 Mb of flash */
if (i == 32) {
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
@ -348,7 +348,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
}
/* issue bank reset to return to read mode */
addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
return (info->size);
}
@ -356,14 +356,14 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
static int wait_for_DQ7_1(flash_info_t * info, int sect)
{
ulong start, now, last;
volatile CFG_FLASH_WORD_SIZE *addr =
(CFG_FLASH_WORD_SIZE *) (info->start[sect]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
start = get_timer(0);
last = start;
while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
(CFG_FLASH_WORD_SIZE) 0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf("Timeout\n");
return -1;
}
@ -376,7 +376,7 @@ static int wait_for_DQ7_1(flash_info_t * info, int sect)
return 0;
}
#ifdef CFG_FLASH_2ND_16BIT_DEV
#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
@ -394,8 +394,8 @@ static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
int flash_erase(flash_info_t * info, int s_first, int s_last)
#endif
{
volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
volatile CFG_FLASH_WORD_SIZE *addr2;
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
int i;
@ -435,24 +435,24 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */
for (i = 0; i < 50; i++)
udelay(1000); /* wait 1 ms */
} else {
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
}
l_sect = sect;
/*
@ -474,8 +474,8 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
udelay(1000);
/* reset to read mode */
addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
printf(" done\n");
return 0;
@ -557,7 +557,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
* 1 - write timeout
* 2 - Flash not erased
*/
#ifdef CFG_FLASH_2ND_16BIT_DEV
#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
static int write_word(flash_info_t * info, ulong dest, ulong data)
{
if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
@ -575,9 +575,9 @@ static int write_word_1(flash_info_t * info, ulong dest, ulong data)
static int write_word(flash_info_t * info, ulong dest, ulong data)
#endif
{
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
ulong start;
int i;
@ -586,15 +586,15 @@ static int write_word(flash_info_t * info, ulong dest, ulong data)
return (2);
}
for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
int flag;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
dest2[i] = data2[i];
@ -604,10 +604,10 @@ static int write_word(flash_info_t * info, ulong dest, ulong data)
/* data polling for D7 */
start = get_timer(0);
while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
(data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
@ -616,10 +616,10 @@ static int write_word(flash_info_t * info, ulong dest, ulong data)
return (0);
}
#ifdef CFG_FLASH_2ND_16BIT_DEV
#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
#undef CFG_FLASH_WORD_SIZE
#define CFG_FLASH_WORD_SIZE unsigned short
#undef CONFIG_SYS_FLASH_WORD_SIZE
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
/*
* The following code cannot be run from FLASH!
@ -628,35 +628,35 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
{
short i;
int n;
CFG_FLASH_WORD_SIZE value;
CONFIG_SYS_FLASH_WORD_SIZE value;
ulong base = (ulong) addr;
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
/* Write auto select command: read Manufacturer ID */
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
udelay(1000);
value = addr2[0];
DEBUGF("FLASH MANUFACT: %x\n", value);
switch (value) {
case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
info->flash_id = FLASH_MAN_SST;
break;
case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
info->flash_id = FLASH_MAN_STM;
break;
case (CFG_FLASH_WORD_SIZE) MX_MANUFACT:
case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT:
info->flash_id = FLASH_MAN_MX;
break;
default:
@ -672,22 +672,22 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
switch (value) {
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MiB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MiB */
case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
info->flash_id += FLASH_STMW320DT;
info->sector_count = 67;
info->size = 0x00400000; break; /* => 4 MiB */
case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T:
case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T:
info->flash_id += FLASH_MXLV320T;
info->sector_count = 71;
info->size = 0x00400000;
@ -776,14 +776,14 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
/* For AMD29033C flash we need to resend the command of *
* reading flash protection for upper 8 Mb of flash */
if (i == 32) {
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
@ -793,7 +793,7 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
}
/* issue bank reset to return to read mode */
addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
return (info->size);
}
@ -801,14 +801,14 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
static int wait_for_DQ7_2(flash_info_t * info, int sect)
{
ulong start, now, last;
volatile CFG_FLASH_WORD_SIZE *addr =
(CFG_FLASH_WORD_SIZE *) (info->start[sect]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
start = get_timer(0);
last = start;
while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
(CFG_FLASH_WORD_SIZE) 0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf("Timeout\n");
return -1;
}
@ -823,8 +823,8 @@ static int wait_for_DQ7_2(flash_info_t * info, int sect)
static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
{
volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
volatile CFG_FLASH_WORD_SIZE *addr2;
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
int i;
@ -864,24 +864,24 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */
for (i = 0; i < 50; i++)
udelay(1000); /* wait 1 ms */
} else {
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
}
l_sect = sect;
/*
@ -903,8 +903,8 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
udelay(1000);
/* reset to read mode */
addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
printf(" done\n");
return 0;
@ -912,9 +912,9 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
static int write_word_2(flash_info_t * info, ulong dest, ulong data)
{
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
ulong start;
int i;
@ -923,15 +923,15 @@ static int write_word_2(flash_info_t * info, ulong dest, ulong data)
return (2);
}
for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
int flag;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
dest2[i] = data2[i];
@ -941,10 +941,10 @@ static int write_word_2(flash_info_t * info, ulong dest, ulong data)
/* data polling for D7 */
start = get_timer(0);
while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
(data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
@ -952,4 +952,4 @@ static int write_word_2(flash_info_t * info, ulong dest, ulong data)
return (0);
}
#endif /* CFG_FLASH_2ND_16BIT_DEV */
#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */

2
board/amcc/ebony/config.mk
View File

@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif

12
board/amcc/ebony/ebony.c
View File

@ -35,7 +35,7 @@ long int fixed_sdram(void);
int board_early_init_f(void)
{
uint reg;
unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
unsigned char status;
/*--------------------------------------------------------------------
@ -204,7 +204,7 @@ int pci_pre_init(struct pci_controller *hose)
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
@ -219,7 +219,7 @@ void pci_target_init(struct pci_controller *hose)
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
out32r(PCIX0_PIM0LAH, 0);
out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
@ -228,12 +228,12 @@ void pci_target_init(struct pci_controller *hose)
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* is_pci_host

12
board/amcc/ebony/flash.c
View File

@ -50,7 +50,7 @@
#define FLASH_ONBD_N_VAL 2
#define FLASH_SRAM_SEL_VAL 1
static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
{0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */
{0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */
{0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */
@ -74,8 +74,8 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info);
unsigned long flash_init(void)
{
unsigned long total_b = 0;
unsigned long size_b[CFG_MAX_FLASH_BANKS];
unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
unsigned char switch_status;
unsigned short index = 0;
int i;
@ -98,7 +98,7 @@ unsigned long flash_init(void)
DEBUGF("FLASH: Index: %d\n", index);
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
@ -121,8 +121,8 @@ unsigned long flash_init(void)
}
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
&flash_info[2]);
#ifdef CONFIG_ENV_IS_IN_FLASH
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,

10
board/amcc/ebony/init.S
View File

@ -49,9 +49,9 @@ tlbtab:
* routine.
*/
tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
tlbtab_end

2
board/amcc/katmai/config.mk
View File

@ -34,5 +34,5 @@ PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif

48
board/amcc/katmai/init.S
View File

@ -59,20 +59,20 @@ tlbtabA:
* routine.
*/
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbtab_end
/**************************************************************************
@ -99,20 +99,20 @@ tlbtabB:
* routine.
*/
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_ACE_BASE, SZ_1K, CFG_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbtab_end

30
board/amcc/katmai/katmai.c
View File

@ -224,11 +224,11 @@ int board_early_init_f (void)
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
mtsdr(sdr_mfr, mfr);
mtsdr(SDR0_PFC0, CFG_PFC0);
mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
out32(GPIO0_OR, CFG_GPIO_OR);
out32(GPIO0_ODR, CFG_GPIO_ODR);
out32(GPIO0_TCR, CFG_GPIO_TCR);
out32(GPIO0_OR, CONFIG_SYS_GPIO_OR);
out32(GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
out32(GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
return 0;
}
@ -298,7 +298,7 @@ int pci_pre_init(struct pci_controller * hose )
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
/*-------------------------------------------------------------------+
@ -313,7 +313,7 @@ void pci_target_init(struct pci_controller * hose )
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*-------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIX0_BAR0, 0 );
@ -321,12 +321,12 @@ void pci_target_init(struct pci_controller * hose )
/*-------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*-------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
#if defined(CONFIG_PCI)
/*************************************************************************
@ -357,11 +357,11 @@ static int katmai_pcie_card_present(int port)
val = in32(GPIO0_IR);
switch (port) {
case 0:
return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT0));
return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0));
case 1:
return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT1));
return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1));
case 2:
return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT2));
return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2));
default:
return 0;
}
@ -404,9 +404,9 @@ void pcie_setup_hoses(int busno)
/* setup mem resource */
pci_set_region(hose->regions + 0,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMSIZE,
PCI_REGION_MEM);
hose->region_count = 1;
pci_register_hose(hose);

10
board/amcc/kilauea/cmd_pll.c
View File

@ -48,7 +48,7 @@
do { \
int __i; \
for (__i = 0; __i < 2; __i++) \
eeprom_write (CFG_I2C_EEPROM_ADDR, \
eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, \
EEPROM_CONF_OFFSET + __i*BUF_STEP, \
pll_select[freq], \
BUF_STEP + __i*BUF_STEP); \
@ -151,7 +151,7 @@ pll_debug(int off)
uchar buffer[EEPROM_SDSTP_PARAM];
memset(buffer, 0, sizeof(buffer));
eeprom_read(CFG_I2C_EEPROM_ADDR, off,
eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off,
buffer, EEPROM_SDSTP_PARAM);
printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
@ -168,9 +168,9 @@ test_write(void)
/*
* Write twice, 8 bytes per write
*/
eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
testbuf, 8);
eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
testbuf, 16);
printf("done\n");
@ -236,7 +236,7 @@ ret:
}
U_BOOT_CMD(
pllalter, CFG_MAXARGS, 1, do_pll_alter,
pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter,
"pllalter- change pll frequence \n",
"pllalter <selection> - change pll frequence \n\n\
** New freq take effect after reset. ** \n\

16
board/amcc/kilauea/kilauea.c
View File

@ -36,7 +36,7 @@
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*
* Board early initialization function
@ -197,7 +197,7 @@ int board_early_init_f (void)
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NRB_BUSY |
(0x80000000 >> (28 + CFG_NAND_CS));
(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
mtsdr(SDR0_CUST0, val);
/*
@ -210,9 +210,9 @@ int board_early_init_f (void)
/*
* Configure FPGA register with PCIe reset
*/
out_be32((void *)CFG_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */
out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */
mdelay(50);
out_be32((void *)CFG_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */
out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */
return 0;
}
@ -222,7 +222,7 @@ int misc_init_r(void)
#ifdef CONFIG_ENV_IS_IN_FLASH
/* Monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
-CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
#endif
@ -330,9 +330,9 @@ void pcie_setup_hoses(int busno)
/* setup mem resource */
pci_set_region(hose->regions + 0,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMSIZE,
PCI_REGION_MEM);
hose->region_count = 1;
pci_register_hose(hose);

2
board/amcc/luan/config.mk
View File

@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif

10
board/amcc/luan/flash.c
View File

@ -42,7 +42,7 @@
#define DEBUGF(x...)
#endif /* DEBUG */
static unsigned long flash_addr_table[1][CFG_MAX_FLASH_BANKS] = {
static unsigned long flash_addr_table[1][CONFIG_SYS_MAX_FLASH_BANKS] = {
{0xff900000, 0xff980000, 0xffc00000}, /* 0:000: configuraton 3 */
};
@ -59,7 +59,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info);
unsigned long flash_init(void)
{
unsigned long total_b = 0;
unsigned long size_b[CFG_MAX_FLASH_BANKS];
unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
unsigned short index = 0;
int i;
@ -69,7 +69,7 @@ unsigned long flash_init(void)
DEBUGF("FLASH: Index: %d\n", index);
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
@ -92,8 +92,8 @@ unsigned long flash_init(void)
}
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
&flash_info[2]);
#ifdef CONFIG_ENV_IS_IN_FLASH
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,

10
board/amcc/luan/init.S
View File

@ -54,7 +54,7 @@ tlbtab:
tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I)
/*
* TLB entries for SDRAM are not needed on this platform.
@ -63,12 +63,12 @@ tlbtab:
*/
/* internal ram (l2 cache) */
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I)
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I)
/* peripherals at f0000000 */
tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I)
/* PCI */
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I)
tlbtab_end

14
board/amcc/luan/luan.c
View File

@ -30,7 +30,7 @@
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*************************************************************************
@ -80,7 +80,7 @@ int board_early_init_f(void)
************************************************************************/
int misc_init_r(void)
{
volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE;
/* set modes of operation */
x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
@ -166,7 +166,7 @@ int pci_pre_init( struct pci_controller *hose )
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
@ -181,7 +181,7 @@ void pci_target_init(struct pci_controller *hose)
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
@ -190,12 +190,12 @@ void pci_target_init(struct pci_controller *hose)
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************

10
board/amcc/makalu/cmd_pll.c
View File

@ -48,7 +48,7 @@
do { \
int __i; \
for (__i = 0; __i < 2; __i++) \
eeprom_write (CFG_I2C_EEPROM_ADDR, \
eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, \
EEPROM_CONF_OFFSET + __i*BUF_STEP, \
pll_select[freq], \
BUF_STEP + __i*BUF_STEP); \
@ -151,7 +151,7 @@ pll_debug(int off)
uchar buffer[EEPROM_SDSTP_PARAM];
memset(buffer, 0, sizeof(buffer));
eeprom_read(CFG_I2C_EEPROM_ADDR, off,
eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off,
buffer, EEPROM_SDSTP_PARAM);
printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
@ -168,9 +168,9 @@ test_write(void)
/*
* Write twice, 8 bytes per write
*/
eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
testbuf, 8);
eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
testbuf, 16);
printf("done\n");
@ -236,7 +236,7 @@ ret:
}
U_BOOT_CMD(
pllalter, CFG_MAXARGS, 1, do_pll_alter,
pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter,
"pllalter- change pll frequence \n",
"pllalter <selection> - change pll frequence \n\n\
** New freq take effect after reset. ** \n\

14
board/amcc/makalu/makalu.c
View File

@ -37,7 +37,7 @@
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*
* Board early initialization function
@ -194,9 +194,9 @@ int board_early_init_f (void)
mtsdr(SDR0_SRST, 0);
/* Reset PCIe slots */
gpio_write_bit(CFG_GPIO_PCIE_RST, 0);
gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 0);
udelay(100);
gpio_write_bit(CFG_GPIO_PCIE_RST, 1);
gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 1);
/*
* Configure PFC (Pin Function Control) registers
@ -213,7 +213,7 @@ int misc_init_r(void)
#ifdef CONFIG_ENV_IS_IN_FLASH
/* Monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
-CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
#endif
@ -286,9 +286,9 @@ void pcie_setup_hoses(int busno)
/* setup mem resource */
pci_set_region(hose->regions + 0,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
CONFIG_SYS_PCIE_MEMSIZE,
PCI_REGION_MEM);
hose->region_count = 1;
pci_register_hose(hose);

2
board/amcc/ocotea/config.mk
View File

@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif

Some files were not shown because too many files have changed in this diff Show More