Merge git://www.denx.de/git/u-boot-marvell
This includes Marvell mvpp2 patches with the ethernet support for the ARMv8 Armada 7k/8k platforms. The ethernet patches are all acked by Joe and he is okay with me pushing them via the Marvell tree.
This commit is contained in:
commit
f532703665
@ -159,7 +159,7 @@
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&cpm_comphy {
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&cpm_comphy {
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phy0 {
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phy0 {
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phy-type = <PHY_TYPE_SGMII2>;
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phy-type = <PHY_TYPE_SGMII2>;
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phy-speed = <PHY_SPEED_3_125G>;
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phy-speed = <PHY_SPEED_1_25G>;
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};
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};
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phy1 {
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phy1 {
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@ -209,3 +209,28 @@
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no-1-8-v;
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no-1-8-v;
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non-removable;
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non-removable;
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};
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};
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&cpm_mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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&cpm_ethernet {
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status = "okay";
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};
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&cpm_eth1 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "sgmii";
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};
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&cpm_eth2 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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@ -283,3 +283,19 @@
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&cps_utmi0 {
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&cps_utmi0 {
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status = "okay";
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status = "okay";
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};
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};
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&cpm_mdio {
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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&cpm_ethernet {
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status = "okay";
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};
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&cpm_eth2 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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@ -61,6 +61,43 @@
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interrupt-parent = <&gic>;
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interrupt-parent = <&gic>;
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ranges = <0x0 0x0 0xf2000000 0x2000000>;
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ranges = <0x0 0x0 0xf2000000 0x2000000>;
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cpm_ethernet: ethernet@0 {
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compatible = "marvell,armada-7k-pp22";
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reg = <0x0 0x100000>, <0x129000 0xb000>;
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clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
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clock-names = "pp_clk", "gop_clk", "mg_clk";
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status = "disabled";
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dma-coherent;
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cpm_eth0: eth0 {
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <0>;
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gop-port-id = <0>;
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status = "disabled";
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};
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cpm_eth1: eth1 {
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <1>;
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gop-port-id = <2>;
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status = "disabled";
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};
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cpm_eth2: eth2 {
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <2>;
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gop-port-id = <3>;
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status = "disabled";
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};
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};
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cpm_mdio: mdio@12a200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0x12a200 0x10>;
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};
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cpm_syscon0: system-controller@440000 {
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cpm_syscon0: system-controller@440000 {
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compatible = "marvell,cp110-system-controller0",
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compatible = "marvell,cp110-system-controller0",
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"syscon";
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"syscon";
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@ -61,6 +61,43 @@
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interrupt-parent = <&gic>;
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interrupt-parent = <&gic>;
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ranges = <0x0 0x0 0xf4000000 0x2000000>;
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ranges = <0x0 0x0 0xf4000000 0x2000000>;
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cps_ethernet: ethernet@0 {
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compatible = "marvell,armada-7k-pp22";
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reg = <0x0 0x100000>, <0x129000 0xb000>;
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clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
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clock-names = "pp_clk", "gop_clk", "mg_clk";
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status = "disabled";
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dma-coherent;
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cps_eth0: eth0 {
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interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <0>;
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gop-port-id = <0>;
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status = "disabled";
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};
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cps_eth1: eth1 {
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interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <1>;
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gop-port-id = <2>;
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status = "disabled";
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};
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cps_eth2: eth2 {
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interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <2>;
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gop-port-id = <3>;
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status = "disabled";
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};
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};
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cps_mdio: mdio@12a200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0x12a200 0x10>;
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};
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cps_syscon0: system-controller@440000 {
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cps_syscon0: system-controller@440000 {
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compatible = "marvell,cp110-system-controller0",
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compatible = "marvell,cp110-system-controller0",
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"syscon";
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"syscon";
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@ -47,7 +47,8 @@ CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MARVELL=y
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CONFIG_MVPP2=y
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CONFIG_PCI=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_PCIE_DW_MVEBU=y
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CONFIG_PCIE_DW_MVEBU=y
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@ -47,7 +47,8 @@ CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MARVELL=y
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CONFIG_MVPP2=y
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CONFIG_PCI=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_PCIE_DW_MVEBU=y
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CONFIG_PCIE_DW_MVEBU=y
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@ -124,12 +124,12 @@ config FEC_MXC
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NXP i.MX processors.
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NXP i.MX processors.
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config MVPP2
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config MVPP2
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bool "Marvell Armada 375 network interface support"
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bool "Marvell Armada 375/7K/8K network interface support"
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depends on ARMADA_375
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depends on ARMADA_375 || ARMADA_8K
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select PHYLIB
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select PHYLIB
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help
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help
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This driver supports the network interface units in the
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This driver supports the network interface units in the
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Marvell ARMADA 375 SoC.
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Marvell ARMADA 375, 7K and 8K SoCs.
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config MACB
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config MACB
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bool "Cadence MACB/GEM Ethernet Interface"
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bool "Cadence MACB/GEM Ethernet Interface"
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1847
drivers/net/mvpp2.c
1847
drivers/net/mvpp2.c
File diff suppressed because it is too large
Load Diff
@ -81,6 +81,14 @@
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#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
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#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
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#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
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#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
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/*
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* Ethernet Driver configuration
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*/
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#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
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#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
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#define CONFIG_ARP_TIMEOUT 200
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#define CONFIG_NET_RETRY_COUNT 50
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/* USB 2.0 */
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/* USB 2.0 */
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
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@ -2,6 +2,7 @@
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#define _LINUX_BITOPS_H
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#define _LINUX_BITOPS_H
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#include <asm/types.h>
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#include <asm/types.h>
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#include <asm-generic/bitsperlong.h>
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#include <linux/compiler.h>
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#include <linux/compiler.h>
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#define BIT(nr) (1UL << (nr))
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#define BIT(nr) (1UL << (nr))
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@ -63,6 +63,9 @@ typedef enum {
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PHY_INTERFACE_MODE_RGMII_TXID,
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PHY_INTERFACE_MODE_RGMII_TXID,
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PHY_INTERFACE_MODE_RTBI,
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PHY_INTERFACE_MODE_RTBI,
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PHY_INTERFACE_MODE_XGMII,
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PHY_INTERFACE_MODE_XGMII,
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PHY_INTERFACE_MODE_XAUI,
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PHY_INTERFACE_MODE_RXAUI,
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PHY_INTERFACE_MODE_SFI,
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PHY_INTERFACE_MODE_NONE, /* Must be last */
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PHY_INTERFACE_MODE_NONE, /* Must be last */
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PHY_INTERFACE_MODE_COUNT,
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PHY_INTERFACE_MODE_COUNT,
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@ -82,6 +85,9 @@ static const char *phy_interface_strings[] = {
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[PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
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[PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
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[PHY_INTERFACE_MODE_RTBI] = "rtbi",
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[PHY_INTERFACE_MODE_RTBI] = "rtbi",
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[PHY_INTERFACE_MODE_XGMII] = "xgmii",
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[PHY_INTERFACE_MODE_XGMII] = "xgmii",
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[PHY_INTERFACE_MODE_XAUI] = "xaui",
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[PHY_INTERFACE_MODE_RXAUI] = "rxaui",
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[PHY_INTERFACE_MODE_SFI] = "sfi",
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[PHY_INTERFACE_MODE_NONE] = "",
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[PHY_INTERFACE_MODE_NONE] = "",
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};
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};
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