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Added RGMII support to the TSECs and Marvell 881111 Phy

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Added a phy initialization to adjust the RGMII RX and TX timing
Always set the R100 bit in 100 BaseT mode regardless of the TSEC mode

Signed-off-by: Nick Spence <nick.spence@freescale.com>
This commit is contained in:
Nick Spence 2006-09-07 07:39:46 -07:00 committed by Kim Phillips
parent ee58ea2689
commit f484dc791a
1 changed files with 4 additions and 4 deletions
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8
drivers/tsec.c
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@ -610,11 +610,10 @@ static void adjust_link(struct eth_device *dev)
regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
| MACCFG2_MII); | MACCFG2_MII);
/* If We're in reduced mode, we need /* Set R100 bit in all modes although
* to say whether we're 10 or 100 MB. * it is only used in RGMII mode
*/ */
if ((priv->speed == 100) if (priv->speed == 100)
&& (priv->flags & TSEC_REDUCED))
regs->ecntrl |= ECNTRL_R100; regs->ecntrl |= ECNTRL_R100;
else else
regs->ecntrl &= ~(ECNTRL_R100); regs->ecntrl &= ~(ECNTRL_R100);
@ -816,6 +815,7 @@ struct phy_info phy_info_M88E1111S = {
{0x1d, 0x5, NULL}, {0x1d, 0x5, NULL},
{0x1e, 0x0, NULL}, {0x1e, 0x0, NULL},
{0x1e, 0x100, NULL}, {0x1e, 0x100, NULL},
{0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
{MIIM_ANAR, MIIM_ANAR_INIT, NULL}, {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},