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arm/errata: Update required bits for A57 cores erratas

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This patch updates the setting of required bits for A57 cores erratas
- 828024 and 826974

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Dai Haruki <dai.haruki at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Bhupesh Sharma 2015-05-28 14:54:13 +05:30 committed by York Sun
parent dbe94dd11c
commit f299b5b0d2
1 changed files with 4 additions and 4 deletions
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8
arch/arm/cpu/armv8/start.S
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@ -115,18 +115,18 @@ apply_a57_core_errata:
#ifdef CONFIG_ARM_ERRATA_828024
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Disable non-allocate hint of w-b-n-a memory type */
mov x0, #0x1 << 49
orr x0, x0, #1 << 49
/* Disable write streaming no L1-allocate threshold */
mov x0, #0x3 << 25
orr x0, x0, #3 << 25
/* Disable write streaming no-allocate threshold */
mov x0, #0x3 << 27
orr x0, x0, #3 << 27
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif
#ifdef CONFIG_ARM_ERRATA_826974
mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
/* Disable speculative load execution ahead of a DMB */
mov x0, #0x1 << 59
orr x0, x0, #1 << 59
msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
#endif