imx: mx6ul_14x14_evk add basic board support
1. Add USDHC, I2C, UART, 74LV, USB, QSPI support. 2. Support SPL 3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default supports sd for usdhc2, but can do hardware rework to make usdhc2 support emmc. Boot Log: U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59) reading u-boot.img reading u-boot.img U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800) CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0 - invalid sensor device Reset cause: POR Board: MX6UL 14x14 EVK I2C: ready DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
6f4b65eda9
commit
f0ff57b0b2
@ -578,6 +578,13 @@ config TARGET_MX6SXSABRESD
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select DM
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select DM_THERMAL
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config TARGET_MX6UL_14X14_EVK
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bool "Support mx6ul_14x14_evk"
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select CPU_V7
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select DM
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select DM_THERMAL
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select SUPPORT_SPL
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config TARGET_GW_VENTANA
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bool "Support gw_ventana"
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select CPU_V7
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@ -915,6 +922,7 @@ source "board/freescale/mx6qsabreauto/Kconfig"
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source "board/freescale/mx6sabresd/Kconfig"
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source "board/freescale/mx6slevk/Kconfig"
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source "board/freescale/mx6sxsabresd/Kconfig"
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source "board/freescale/mx6ul_14x14_evk/Kconfig"
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source "board/freescale/vf610twr/Kconfig"
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source "board/gateworks/gw_ventana/Kconfig"
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source "board/genesi/mx51_efikamx/Kconfig"
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15
board/freescale/mx6ul_14x14_evk/Kconfig
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15
board/freescale/mx6ul_14x14_evk/Kconfig
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@ -0,0 +1,15 @@
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if TARGET_MX6UL_14X14_EVK
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config SYS_BOARD
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default "mx6ul_14x14_evk"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "mx6"
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config SYS_CONFIG_NAME
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default "mx6ul_14x14_evk"
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endif
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6
board/freescale/mx6ul_14x14_evk/MAINTAINERS
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6
board/freescale/mx6ul_14x14_evk/MAINTAINERS
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@ -0,0 +1,6 @@
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MX6ULEVK BOARD
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M: Peng Fan <Peng.Fan@freescale.com>
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S: Maintained
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F: board/freescale/mx6ul_14x14_evk/
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F: include/configs/mx6ul_14x14_evk.h
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F: configs/mx6ul_14x14_evk_defconfig
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6
board/freescale/mx6ul_14x14_evk/Makefile
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6
board/freescale/mx6ul_14x14_evk/Makefile
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@ -0,0 +1,6 @@
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# (C) Copyright 2015 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := mx6ul_14x14_evk.o
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636
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
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636
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
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@ -0,0 +1,636 @@
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx6ul_pins.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <asm/io.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <i2c.h>
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#include <linux/sizes.h>
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#include <mmc.h>
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#include <usb.h>
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#include <usb/ehci-fsl.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE)
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#define IOX_SDI IMX_GPIO_NR(5, 10)
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#define IOX_STCP IMX_GPIO_NR(5, 7)
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#define IOX_SHCP IMX_GPIO_NR(5, 11)
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#define IOX_OE IMX_GPIO_NR(5, 18)
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static iomux_v3_cfg_t const iox_pads[] = {
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/* IOX_SDI */
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MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* IOX_SHCP */
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MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* IOX_STCP */
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MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* IOX_nOE */
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MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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/*
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* HDMI_nRST --> Q0
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* ENET1_nRST --> Q1
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* ENET2_nRST --> Q2
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* CAN1_2_STBY --> Q3
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* BT_nPWD --> Q4
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* CSI_RST --> Q5
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* CSI_PWDN --> Q6
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* LCD_nPWREN --> Q7
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*/
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enum qn {
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HDMI_NRST,
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ENET1_NRST,
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ENET2_NRST,
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CAN1_2_STBY,
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BT_NPWD,
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CSI_RST,
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CSI_PWDN,
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LCD_NPWREN,
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};
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enum qn_func {
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qn_reset,
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qn_enable,
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qn_disable,
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};
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enum qn_level {
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qn_low = 0,
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qn_high = 1,
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};
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static enum qn_level seq[3][2] = {
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{0, 1}, {1, 1}, {0, 0}
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};
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static enum qn_func qn_output[8] = {
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qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
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qn_disable, qn_enable
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};
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static void iox74lv_init(void)
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{
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int i;
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gpio_direction_output(IOX_OE, 0);
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for (i = 7; i >= 0; i--) {
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gpio_direction_output(IOX_SHCP, 0);
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
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udelay(500);
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gpio_direction_output(IOX_SHCP, 1);
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udelay(500);
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}
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gpio_direction_output(IOX_STCP, 0);
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udelay(500);
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/*
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* shift register will be output to pins
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*/
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gpio_direction_output(IOX_STCP, 1);
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for (i = 7; i >= 0; i--) {
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gpio_direction_output(IOX_SHCP, 0);
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
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udelay(500);
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gpio_direction_output(IOX_SHCP, 1);
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udelay(500);
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}
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gpio_direction_output(IOX_STCP, 0);
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udelay(500);
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/*
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* shift register will be output to pins
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*/
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gpio_direction_output(IOX_STCP, 1);
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gpio_direction_output(IOX_OE, 1);
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};
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void iox74lv_set(int index)
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{
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int i;
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gpio_direction_output(IOX_OE, 0);
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for (i = 7; i >= 0; i--) {
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gpio_direction_output(IOX_SHCP, 0);
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if (i == index)
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
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else
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
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udelay(500);
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gpio_direction_output(IOX_SHCP, 1);
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udelay(500);
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}
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gpio_direction_output(IOX_STCP, 0);
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udelay(500);
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/*
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* shift register will be output to pins
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*/
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gpio_direction_output(IOX_STCP, 1);
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for (i = 7; i >= 0; i--) {
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gpio_direction_output(IOX_SHCP, 0);
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
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udelay(500);
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gpio_direction_output(IOX_SHCP, 1);
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udelay(500);
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}
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gpio_direction_output(IOX_STCP, 0);
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udelay(500);
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/*
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* shift register will be output to pins
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*/
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gpio_direction_output(IOX_STCP, 1);
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gpio_direction_output(IOX_OE, 1);
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};
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#ifdef CONFIG_SYS_I2C_MXC
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C1 for PMIC and EEPROM */
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
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.gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
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.gp = IMX_GPIO_NR(1, 28),
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},
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.sda = {
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.i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
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.gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
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.gp = IMX_GPIO_NR(1, 29),
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},
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};
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#endif
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/* VSELECT */
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MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/* CD */
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MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* RST_B */
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MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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/*
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* mx6ul_14x14_evk board default supports sd card. If want to use
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* EMMC, need to do board rework for sd2.
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* Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
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* emmc, need to define this macro.
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*/
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#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
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static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
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MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/*
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* RST_B
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*/
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MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#else
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc2_cd_pads[] = {
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/*
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* The evk board uses DAT3 to detect CD card plugin,
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* in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
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*/
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MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc2_dat3_pads[] = {
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MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
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MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
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};
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#endif
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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#ifdef CONFIG_FSL_QSPI
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#define QSPI_PAD_CTRL1 \
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(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
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PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
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static iomux_v3_cfg_t const quadspi_pads[] = {
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MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
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MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
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MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
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MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
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MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
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MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
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};
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int board_qspi_init(void)
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{
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/* Set the iomux */
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imx_iomux_v3_setup_multiple_pads(quadspi_pads,
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ARRAY_SIZE(quadspi_pads));
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/* Set the clock */
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enable_qspi_clk(0);
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return 0;
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}
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#endif
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#ifdef CONFIG_FSL_ESDHC
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static struct fsl_esdhc_cfg usdhc_cfg[2] = {
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{USDHC1_BASE_ADDR, 0, 4},
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#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
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{USDHC2_BASE_ADDR, 0, 8},
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#else
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{USDHC2_BASE_ADDR, 0, 4},
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#endif
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};
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#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
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#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
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#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
|
||||
#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC1_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC1_CD_GPIO);
|
||||
break;
|
||||
case USDHC2_BASE_ADDR:
|
||||
#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
|
||||
ret = 1;
|
||||
#else
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads,
|
||||
ARRAY_SIZE(usdhc2_cd_pads));
|
||||
gpio_direction_input(USDHC2_CD_GPIO);
|
||||
|
||||
/*
|
||||
* Since it is the DAT3 pin, this pin is pulled to
|
||||
* low voltage if no card
|
||||
*/
|
||||
ret = gpio_get_value(USDHC2_CD_GPIO);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads,
|
||||
ARRAY_SIZE(usdhc2_dat3_pads));
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
|
||||
ARRAY_SIZE(usdhc2_emmc_pads));
|
||||
#else
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
||||
#endif
|
||||
gpio_direction_output(USDHC2_PWR_GPIO, 0);
|
||||
udelay(500);
|
||||
gpio_direction_output(USDHC2_PWR_GPIO, 1);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
|
||||
#else
|
||||
int i, ret;
|
||||
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-boot device node) (Physical Port)
|
||||
* mmc0 USDHC1
|
||||
* mmc1 USDHC2
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
|
||||
gpio_direction_input(USDHC1_CD_GPIO);
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
|
||||
gpio_direction_output(USDHC1_PWR_GPIO, 0);
|
||||
udelay(500);
|
||||
gpio_direction_output(USDHC1_PWR_GPIO, 1);
|
||||
break;
|
||||
case 1:
|
||||
#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
|
||||
#else
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
||||
#endif
|
||||
gpio_direction_output(USDHC2_PWR_GPIO, 0);
|
||||
udelay(500);
|
||||
gpio_direction_output(USDHC2_PWR_GPIO, 1);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
||||
if (ret) {
|
||||
printf("Warning: failed to initialize mmc dev %d\n", i);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
#define USB_OTHERREGS_OFFSET 0x800
|
||||
#define UCTRL_PWR_POL (1 << 9)
|
||||
|
||||
static iomux_v3_cfg_t const usb_otg_pads[] = {
|
||||
MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
/* At default the 3v3 enables the MIC2026 for VBUS power */
|
||||
static void setup_usb(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
|
||||
ARRAY_SIZE(usb_otg_pads));
|
||||
}
|
||||
|
||||
int board_usb_phy_mode(int port)
|
||||
{
|
||||
if (port == 1)
|
||||
return USB_INIT_HOST;
|
||||
else
|
||||
return usb_phy_mode(port);
|
||||
}
|
||||
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
u32 *usbnc_usb_ctrl;
|
||||
|
||||
if (port > 1)
|
||||
return -EINVAL;
|
||||
|
||||
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
|
||||
port * 4);
|
||||
|
||||
/* Set Power polarity */
|
||||
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
|
||||
|
||||
iox74lv_init();
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
setup_usb();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
board_qspi_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
|
||||
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
||||
{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return get_cpu_rev();
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: MX6UL 14x14 EVK\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#include <libfdt.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch/mx6-ddr.h>
|
||||
|
||||
const struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
|
||||
.dram_dqm0 = 0x00000030,
|
||||
.dram_dqm1 = 0x00000030,
|
||||
.dram_ras = 0x00000030,
|
||||
.dram_cas = 0x00000030,
|
||||
.dram_odt0 = 0x00000030,
|
||||
.dram_odt1 = 0x00000030,
|
||||
.dram_sdba2 = 0x00000000,
|
||||
.dram_sdclk_0 = 0x00000008,
|
||||
.dram_sdqs0 = 0x00000038,
|
||||
.dram_sdqs1 = 0x00000030,
|
||||
.dram_reset = 0x00000030,
|
||||
};
|
||||
|
||||
const struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
|
||||
.grp_addds = 0x00000030,
|
||||
.grp_ddrmode_ctl = 0x00020000,
|
||||
.grp_b0ds = 0x00000030,
|
||||
.grp_ctlds = 0x00000030,
|
||||
.grp_b1ds = 0x00000030,
|
||||
.grp_ddrpke = 0x00000000,
|
||||
.grp_ddrmode = 0x00020000,
|
||||
.grp_ddr_type = 0x000c0000,
|
||||
};
|
||||
|
||||
const struct mx6_mmdc_calibration mx6_mmcd_calib = {
|
||||
.p0_mpwldectrl0 = 0x00070007,
|
||||
.p0_mpdgctrl0 = 0x41490145,
|
||||
.p0_mprddlctl = 0x40404546,
|
||||
.p0_mpwrdlctl = 0x4040524D,
|
||||
};
|
||||
|
||||
static struct mx6_ddr3_cfg mem_ddr = {
|
||||
.mem_speed = 800,
|
||||
.density = 4,
|
||||
.width = 16,
|
||||
.banks = 8,
|
||||
.rowaddr = 15,
|
||||
.coladdr = 10,
|
||||
.pagesz = 2,
|
||||
.trcd = 1375,
|
||||
.trcmin = 4875,
|
||||
.trasmin = 3500,
|
||||
};
|
||||
|
||||
static void ccgr_init(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
writel(0xFFFFFFFF, &ccm->CCGR0);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR1);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR2);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR3);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR4);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR5);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR6);
|
||||
writel(0xFFFFFFFF, &ccm->CCGR7);
|
||||
}
|
||||
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
struct mx6_ddr_sysinfo sysinfo = {
|
||||
.dsize = 0,
|
||||
.cs_density = 20,
|
||||
.ncs = 1,
|
||||
.cs1_mirror = 0,
|
||||
.rtt_wr = 2,
|
||||
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
|
||||
.walat = 1, /* Write additional latency */
|
||||
.ralat = 5, /* Read additional latency */
|
||||
.mif3_mode = 3, /* Command prediction working mode */
|
||||
.bi_on = 1, /* Bank interleaving enabled */
|
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
|
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
||||
};
|
||||
|
||||
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
|
||||
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* setup AIPS and disable watchdog */
|
||||
arch_cpu_init();
|
||||
|
||||
ccgr_init();
|
||||
|
||||
/* iomux and setup of i2c */
|
||||
board_early_init_f();
|
||||
|
||||
/* setup GP timer */
|
||||
timer_init();
|
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
/* load/boot image from boot device */
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
4
configs/mx6ul_14x14_evk_defconfig
Normal file
4
configs/mx6ul_14x14_evk_defconfig
Normal file
@ -0,0 +1,4 @@
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL"
|
||||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_MX6UL_14X14_EVK=y
|
||||
CONFIG_SPL=y
|
||||
227
include/configs/mx6ul_14x14_evk.h
Normal file
227
include/configs/mx6ul_14x14_evk.h
Normal file
@ -0,0 +1,227 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef __MX6UL_14X14_EVK_CONFIG_H
|
||||
#define __MX6UL_14X14_EVK_CONFIG_H
|
||||
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <linux/sizes.h>
|
||||
#include "mx6_common.h"
|
||||
#include <asm/imx-common/gpio.h>
|
||||
|
||||
/* SPL options */
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#define CONFIG_SPL_FAT_SUPPORT
|
||||
#include "imx6_spl.h"
|
||||
|
||||
#define CONFIG_MX6
|
||||
#define CONFIG_ROM_UNIFIED_SECTIONS
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
|
||||
#define CONFIG_CMD_FUSE
|
||||
#ifdef CONFIG_CMD_FUSE
|
||||
#define CONFIG_MXC_OCOTP
|
||||
#endif
|
||||
|
||||
/* MMC Configs */
|
||||
#ifdef CONFIG_FSL_USDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
|
||||
|
||||
/* NAND pin conflicts with usdhc2 */
|
||||
#ifdef CONFIG_NAND_MXS
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
#endif
|
||||
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
||||
#endif
|
||||
|
||||
#undef CONFIG_BOOTM_NETBSD
|
||||
#undef CONFIG_BOOTM_PLAN9
|
||||
#undef CONFIG_BOOTM_RTEMS
|
||||
|
||||
#undef CONFIG_CMD_EXPORTENV
|
||||
#undef CONFIG_CMD_IMPORTENV
|
||||
|
||||
/* I2C configs */
|
||||
#define CONFIG_CMD_I2C
|
||||
#ifdef CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#endif
|
||||
|
||||
#define PHYS_SDRAM_SIZE SZ_512M
|
||||
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=imx6ul-14x14-evk.dtb\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev};" \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_PROMPT "=> "
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
#define CONFIG_CMD_MEMTEST
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000)
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_STACKSIZE SZ_128K
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* FLASH and environment organization */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#define CONFIG_ENV_SIZE SZ_8K
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
#define CONFIG_CMD_BMODE
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_CMD_CACHE
|
||||
#endif
|
||||
|
||||
#define CONFIG_FSL_QSPI
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_SPI_FLASH_BAR
|
||||
#define CONFIG_SF_DEFAULT_BUS 0
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 40000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#define FSL_QSPI_FLASH_NUM 1
|
||||
#define FSL_QSPI_FLASH_SIZE SZ_32M
|
||||
#endif
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_CMD_USB
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_MX6
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#endif
|
||||
|
||||
#define CONFIG_IMX6_THERMAL
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user