misc: add i.MX8 misc driver
Add i.MX8 MISC driver to handle the communication between A35 Core and SCU. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan
Stefano Babic
parent
60b9de4f70
commit
ef64e782ec
@ -20,6 +20,7 @@ obj-$(CONFIG_FSL_IIM) += fsl_iim.o
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obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
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obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
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obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
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obj-$(CONFIG_IMX8) += imx8/
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obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
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obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
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obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
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3
drivers/misc/imx8/Makefile
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3
drivers/misc/imx8/Makefile
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0+
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obj-y += scu.o
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266
drivers/misc/imx8/scu.c
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266
drivers/misc/imx8/scu.c
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@ -0,0 +1,266 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2018 NXP
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*
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* Peng Fan <peng.fan@nxp.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <dm/lists.h>
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#include <dm/root.h>
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#include <dm/device-internal.h>
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#include <asm/arch/sci/sci.h>
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#include <linux/iopoll.h>
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#include <misc.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct mu_type {
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u32 tr[4];
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u32 rr[4];
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u32 sr;
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u32 cr;
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};
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struct imx8_scu {
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struct mu_type *base;
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struct udevice *clk;
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struct udevice *pinclk;
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};
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#define MU_CR_GIE_MASK 0xF0000000u
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#define MU_CR_RIE_MASK 0xF000000u
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#define MU_CR_GIR_MASK 0xF0000u
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#define MU_CR_TIE_MASK 0xF00000u
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#define MU_CR_F_MASK 0x7u
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#define MU_SR_TE0_MASK BIT(23)
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#define MU_SR_RF0_MASK BIT(27)
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#define MU_TR_COUNT 4
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#define MU_RR_COUNT 4
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static inline void mu_hal_init(struct mu_type *base)
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{
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/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
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clrbits_le32(&base->cr, MU_CR_GIE_MASK | MU_CR_RIE_MASK |
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MU_CR_TIE_MASK | MU_CR_GIR_MASK | MU_CR_F_MASK);
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}
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static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg)
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{
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u32 mask = MU_SR_TE0_MASK >> reg_index;
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u32 val;
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int ret;
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assert(reg_index < MU_TR_COUNT);
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/* Wait TX register to be empty. */
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ret = readl_poll_timeout(&base->sr, val, val & mask, 10000);
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if (ret < 0) {
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printf("%s timeout\n", __func__);
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return -ETIMEDOUT;
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}
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writel(msg, &base->tr[reg_index]);
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return 0;
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}
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static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg)
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{
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u32 mask = MU_SR_RF0_MASK >> reg_index;
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u32 val;
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int ret;
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assert(reg_index < MU_TR_COUNT);
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/* Wait RX register to be full. */
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ret = readl_poll_timeout(&base->sr, val, val & mask, 10000);
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if (ret < 0) {
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printf("%s timeout\n", __func__);
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return -ETIMEDOUT;
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}
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*msg = readl(&base->rr[reg_index]);
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return 0;
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}
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static int sc_ipc_read(struct mu_type *base, void *data)
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{
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struct sc_rpc_msg_s *msg = (struct sc_rpc_msg_s *)data;
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int ret;
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u8 count = 0;
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if (!msg)
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return -EINVAL;
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/* Read first word */
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ret = mu_hal_receivemsg(base, 0, (u32 *)msg);
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if (ret)
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return ret;
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count++;
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/* Check size */
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if (msg->size > SC_RPC_MAX_MSG) {
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*((u32 *)msg) = 0;
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return -EINVAL;
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}
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/* Read remaining words */
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while (count < msg->size) {
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ret = mu_hal_receivemsg(base, count % MU_RR_COUNT,
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&msg->DATA.u32[count - 1]);
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if (ret)
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return ret;
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count++;
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}
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return 0;
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}
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static int sc_ipc_write(struct mu_type *base, void *data)
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{
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struct sc_rpc_msg_s *msg = (struct sc_rpc_msg_s *)data;
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int ret;
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u8 count = 0;
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if (!msg)
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return -EINVAL;
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/* Check size */
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if (msg->size > SC_RPC_MAX_MSG)
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return -EINVAL;
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/* Write first word */
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ret = mu_hal_sendmsg(base, 0, *((u32 *)msg));
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if (ret)
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return ret;
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count++;
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/* Write remaining words */
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while (count < msg->size) {
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ret = mu_hal_sendmsg(base, count % MU_TR_COUNT,
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msg->DATA.u32[count - 1]);
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if (ret)
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return ret;
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count++;
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}
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return 0;
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}
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/*
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* Note the function prototype use msgid as the 2nd parameter, here
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* we take it as no_resp.
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*/
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static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
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int tx_size, void *rx_msg, int rx_size)
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{
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struct imx8_scu *priv = dev_get_priv(dev);
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sc_err_t result;
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int ret;
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/* Expect tx_msg, rx_msg are the same value */
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if (rx_msg && tx_msg != rx_msg)
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printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg);
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ret = sc_ipc_write(priv->base, tx_msg);
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if (ret)
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return ret;
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if (!no_resp) {
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ret = sc_ipc_read(priv->base, rx_msg);
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if (ret)
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return ret;
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}
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result = RPC_R8((struct sc_rpc_msg_s *)tx_msg);
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return sc_err_to_linux(result);
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}
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static int imx8_scu_probe(struct udevice *dev)
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{
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struct imx8_scu *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
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addr = devfdt_get_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->base = (struct mu_type *)addr;
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/* U-Boot not enable interrupts, so need to enable RX interrupts */
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mu_hal_init(priv->base);
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gd->arch.scu_dev = dev;
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device_probe(priv->clk);
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device_probe(priv->pinclk);
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return 0;
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}
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static int imx8_scu_remove(struct udevice *dev)
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{
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return 0;
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}
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static int imx8_scu_bind(struct udevice *dev)
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{
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struct imx8_scu *priv = dev_get_priv(dev);
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int ret;
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struct udevice *child;
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int node;
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debug("%s(dev=%p)\n", __func__, dev);
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node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
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"fsl,imx8qxp-clk");
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if (node < 0)
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panic("No clk node found\n");
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ret = lists_bind_fdt(dev, offset_to_ofnode(node), &child);
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if (ret)
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return ret;
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priv->clk = child;
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node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
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"fsl,imx8qxp-iomuxc");
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if (node < 0)
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panic("No iomuxc node found\n");
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ret = lists_bind_fdt(dev, offset_to_ofnode(node), &child);
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if (ret)
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return ret;
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priv->pinclk = child;
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return 0;
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}
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static struct misc_ops imx8_scu_ops = {
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.call = imx8_scu_call,
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};
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static const struct udevice_id imx8_scu_ids[] = {
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{ .compatible = "fsl,imx8qxp-mu" },
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{ .compatible = "fsl,imx8-mu" },
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{ }
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};
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U_BOOT_DRIVER(imx8_scu) = {
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.name = "imx8_scu",
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.id = UCLASS_MISC,
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.of_match = imx8_scu_ids,
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.probe = imx8_scu_probe,
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.bind = imx8_scu_bind,
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.remove = imx8_scu_remove,
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.ops = &imx8_scu_ops,
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.priv_auto_alloc_size = sizeof(struct imx8_scu),
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.flags = DM_FLAG_PRE_RELOC,
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};
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