arm: dts: ti: Add Support for J721E SoC
Add initial SoC definition for J721E SoC. Kernel dts posted here: https://lore.kernel.org/lkml/20190522161921.20750-1-nm@ti.com/ Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla
Tom Rini
parent
382f1dda97
commit
eeb2e8b6eb
231
arch/arm/dts/k3-j721e-main.dtsi
Normal file
231
arch/arm/dts/k3-j721e-main.dtsi
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@ -0,0 +1,231 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J721E SoC Family Main Domain peripherals
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*
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* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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&cbass_main {
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msmc_ram: sram@70000000 {
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compatible = "mmio-sram";
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reg = <0x0 0x70000000 0x0 0x800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x70000000 0x800000>;
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atf-sram@0 {
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reg = <0x0 0x20000>;
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};
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};
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01900000 0x00 0x100000>; /* GICR */
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/* vcpumntirq: virtual CPU interface maintenance interrupt */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: gic-its@18200000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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smmu0: smmu@36600000 {
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compatible = "arm,smmu-v3";
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reg = <0x0 0x36600000 0x0 0x100000>;
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "gerror";
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#iommu-cells = <1>;
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};
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secure_proxy_main: mailbox@32c00000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x32c00000 0x00 0x100000>,
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<0x00 0x32400000 0x00 0x100000>,
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<0x00 0x32800000 0x00 0x100000>;
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interrupt-names = "rx_011";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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};
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main_pmx0: pinmux@11c000 {
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compatible = "pinctrl-single";
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/* Proxy 0 addressing */
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reg = <0x0 0x11c000 0x0 0x2b4>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_uart0: serial@2800000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 146 0>;
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clock-names = "fclk";
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};
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main_uart1: serial@2810000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02810000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 278 0>;
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clock-names = "fclk";
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};
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main_uart2: serial@2820000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02820000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 279 0>;
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clock-names = "fclk";
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};
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main_uart3: serial@2830000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02830000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 280 0>;
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clock-names = "fclk";
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};
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main_uart4: serial@2840000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02840000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 281 0>;
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clock-names = "fclk";
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};
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main_uart5: serial@2850000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02850000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 282 0>;
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clock-names = "fclk";
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};
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main_uart6: serial@2860000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02860000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 283 0>;
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clock-names = "fclk";
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};
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main_uart7: serial@2870000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02870000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 284 0>;
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clock-names = "fclk";
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};
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main_uart8: serial@2880000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02880000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 285 0>;
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clock-names = "fclk";
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};
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main_uart9: serial@2890000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02890000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 286 0>;
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clock-names = "fclk";
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};
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main_sdhci0: sdhci@4f80000 {
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compatible = "ti,j721e-sdhci-8bit";
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reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
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assigned-clocks = <&k3_clks 91 1>;
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assigned-clock-parents = <&k3_clks 91 2>;
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bus-width = <8>;
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ti,otap-del-sel = <0x2>;
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ti,trm-icp = <0x8>;
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dma-coherent;
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};
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main_sdhci1: sdhci@4fb0000 {
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compatible = "ti,j721e-sdhci-4bit";
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reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
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assigned-clocks = <&k3_clks 92 0>;
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assigned-clock-parents = <&k3_clks 92 1>;
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ti,otap-del-sel = <0x2>;
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ti,trm-icp = <0x8>;
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dma-coherent;
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};
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};
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72
arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
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72
arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
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@ -0,0 +1,72 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
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*
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* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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&cbass_mcu_wakeup {
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dmsc: dmsc@44083000 {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy_main 11>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x00 0x44083000 0x0 0x1000>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <2>;
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};
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k3_clks: clocks {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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ti,scan-clocks-from-dt;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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wkup_pmx0: pinmux@4301c000 {
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compatible = "pinctrl-single";
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/* Proxy 0 addressing */
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reg = <0x00 0x4301c000 0x00 0x178>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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wkup_uart0: serial@42300000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x42300000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 287 0>;
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clock-names = "fclk";
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};
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mcu_uart0: serial@40a00000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x40a00000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <96000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 149 0>;
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clock-names = "fclk";
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};
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};
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177
arch/arm/dts/k3-j721e.dtsi
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177
arch/arm/dts/k3-j721e.dtsi
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@ -0,0 +1,177 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J721E SoC Family
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*
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* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/k3.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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/ {
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model = "Texas Instruments K3 J721E SoC";
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compatible = "ti,j721e";
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interrupt-parent = <&gic500>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &wkup_uart0;
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serial1 = &mcu_uart0;
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serial2 = &main_uart0;
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serial3 = &main_uart1;
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serial4 = &main_uart2;
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serial5 = &main_uart3;
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serial6 = &main_uart4;
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serial7 = &main_uart5;
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serial8 = &main_uart6;
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serial9 = &main_uart7;
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serial10 = &main_uart8;
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serial11 = &main_uart9;
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};
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chosen { };
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0: cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a72";
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reg = <0x000>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a72";
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reg = <0x001>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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};
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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next-level-cache = <&msmc_l3>;
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};
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msmc_l3: l3-cache0 {
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compatible = "cache";
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cache-level = <3>;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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a72_timer0: timer-cl0-cpu0 {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
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};
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pmu: pmu {
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compatible = "arm,armv8-pmuv3";
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/* Recommendation from GIC500 TRM Table A.3 */
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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|
||||
cbass_main: interconnect@100000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
|
||||
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
|
||||
<0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
|
||||
<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
|
||||
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
|
||||
<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
|
||||
<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
|
||||
<0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
|
||||
<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
|
||||
/* MCUSS_WKUP Range */
|
||||
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>,
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
|
||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
|
||||
|
||||
cbass_mcu_wakeup: interconnect@28380000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
|
||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Now include the peripherals for each bus segments */
|
||||
#include "k3-j721e-main.dtsi"
|
||||
#include "k3-j721e-mcu-wakeup.dtsi"
|
||||
Loading…
Reference in New Issue
Block a user