omap3evm: Reorder related config options
This patch brings related config options together. Most config options won't be evaluated for numerical value, but they are being set to 1. This patch also removes this assignment. Some formatting changes were also done for consistent look-n-feel after the movement. The patch doesn't make/include any other functional change. Signed-off-by: Sanjeev Premi <premi@ti.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Sanjeev Premi
Albert ARIBAUD
parent
b88befa550
commit
ee8e225400
@ -36,42 +36,80 @@
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP34XX 1 /* which is a 34XX */
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#define CONFIG_OMAP3430 1 /* which is in a 3430 */
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#define CONFIG_OMAP3_EVM 1 /* working with EVM */
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#define CONFIG_OMAP /* This is TI OMAP core */
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#define CONFIG_OMAP34XX /* belonging to 34XX family */
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#define CONFIG_OMAP3430 /* which is in a 3430 */
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#define CONFIG_SDRC /* The chip has SDRC controller */
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#define CONFIG_SDRC /* The chip has SDRC controller */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap3.h>
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#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
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#define CONFIG_OMAP3_MICRON_DDR /* with MICRON DDR part */
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#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
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/*
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* Display CPU and Board information
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* Get cpu and chip specific definitions
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*/
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#define CONFIG_DISPLAY_CPUINFO 1
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#define CONFIG_DISPLAY_BOARDINFO 1
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#include <asm/arch/cpu.h>
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#include <asm/arch/omap3.h>
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/* Clock Defines */
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#undef CONFIG_USE_IRQ /* no support for IRQs */
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/*
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* Clock related definitions
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*/
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#undef CONFIG_USE_IRQ /* no support for IRQs */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_REVISION_TAG 1
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/*
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* Size of malloc() pool
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
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/* Sector */
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#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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#define CONFIG_SYS_HZ 1000
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/* Size of environment - 128KB */
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#define CONFIG_ENV_SIZE (128 << 10)
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/* Size of malloc pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
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/*
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
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#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
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#endif
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/*
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* Physical Memory Map
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* Note 1: CS1 may or may not be populated
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* Note 2: SDRAM size is expected to be at least 32MB
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*/
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#define CONFIG_NR_DRAM_BANKS 2
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE (32 << 20)
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/* SDRAM Bank Allocation method */
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#define SDRC_R_B_C
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/* Limits for memtest */
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
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#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
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0x01F00000) /* 31MB */
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/* Default load address */
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
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/* -----------------------------------------------------------------------------
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* Hardware drivers
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* -----------------------------------------------------------------------------
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*/
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/*
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@ -88,29 +126,88 @@
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* select serial console configuration
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
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#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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#define CONFIG_MMC 1
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#define CONFIG_GENERIC_MMC 1
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#define CONFIG_OMAP_HSMMC 1
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#define CONFIG_DOS_PARTITION 1
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/* DDR - I use Micron DDR */
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#define CONFIG_OMAP3_MICRON_DDR 1
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/*
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* I2C
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*/
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#define CONFIG_HARD_I2C
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#define CONFIG_DRIVER_OMAP34XX_I2C
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 1
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#define CONFIG_SYS_I2C_BUS 0
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#define CONFIG_SYS_I2C_BUS_SELECT 1
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/*
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* PISMO support
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*/
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#define PISMO1_NAND_SIZE GPMC_SIZE_128M
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#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
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/* Monitor at start of flash - Reserve 2 sectors */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 << 10)
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/* Start location & size of environment */
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#define ONENAND_ENV_OFFSET 0x260000
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#define SMNAND_ENV_OFFSET 0x260000
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
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/*
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* NAND
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*/
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/* Physical address to access NAND */
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#define CONFIG_SYS_NAND_ADDR NAND_BASE
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/* Physical address to access NAND at CS0 */
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#define CONFIG_SYS_NAND_BASE NAND_BASE
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/* Max number of NAND devices */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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/* Timeout values (in ticks) */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
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/* Flash banks JFFS2 should use */
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#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
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CONFIG_SYS_MAX_NAND_DEVICE)
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#define CONFIG_SYS_JFFS2_MEM_NAND
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#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
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#define CONFIG_SYS_JFFS2_NUM_BANKS 1
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#define CONFIG_JFFS2_NAND
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/* nand device jffs2 lives on */
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#define CONFIG_JFFS2_DEV "nand0"
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/* Start of jffs2 partition */
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#define CONFIG_JFFS2_PART_OFFSET 0x680000
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/* Size of jffs2 partition */
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#define CONFIG_JFFS2_PART_SIZE 0xf980000
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/*
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* MMC
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*/
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_OMAP_HSMMC
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#define CONFIG_DOS_PARTITION
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/* USB
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*
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* Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
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* Enable CONFIG_MUSB_UDD for Device functionalities.
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*/
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#define CONFIG_USB_OMAP3 1
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#define CONFIG_MUSB_HCD 1
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/* #define CONFIG_MUSB_UDC 1 */
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#define CONFIG_USB_OMAP3
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#define CONFIG_MUSB_HCD
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/* #define CONFIG_MUSB_UDC */
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#ifdef CONFIG_USB_OMAP3
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@ -123,16 +220,17 @@
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#ifdef CONFIG_USB_KEYBOARD
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#define CONFIG_SYS_USB_EVENT_POLL
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#define CONFIG_PREBOOT "usb start"
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#define CONFIG_PREBOOT "usb start"
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#endif /* CONFIG_USB_KEYBOARD */
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#endif /* CONFIG_MUSB_HCD */
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#ifdef CONFIG_MUSB_UDC
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/* USB device configuration */
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#define CONFIG_USB_DEVICE 1
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#define CONFIG_USB_TTY 1
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
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#define CONFIG_USB_DEVICE
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#define CONFIG_USB_TTY
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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/* Change these to suit your needs */
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#define CONFIG_USBD_VENDORID 0x0451
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#define CONFIG_USBD_PRODUCTID 0x5678
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@ -142,7 +240,44 @@
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#endif /* CONFIG_USB_OMAP3 */
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/* commands to include */
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/* ----------------------------------------------------------------------------
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* U-boot features
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* ----------------------------------------------------------------------------
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT "OMAP3_EVM # "
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_MAXARGS 16 /* max args for a command */
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/* Display CPU and Board information */
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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/* Allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* Add auto-completion support */
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#define CONFIG_AUTO_COMPLETE
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/* Size of Console IO buffer */
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#define CONFIG_SYS_CBSIZE 512
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/* Size of print buffer */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/* Size of bootarg buffer */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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/* Default commands to include */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_EXT2 /* EXT2 Support */
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@ -160,40 +295,64 @@
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#undef CONFIG_CMD_IMI /* iminfo */
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#undef CONFIG_CMD_IMLS /* List all found images */
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/*
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* Additional definitions that depend on chosen commands
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*/
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/* NAND */
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
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#define CONFIG_NAND_OMAP_GPMC
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#define GPMC_NAND_ECC_LP_x16_LAYOUT
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
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#elif defined(CONFIG_CMD_ONENAND)
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#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
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#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
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#define CONFIG_ENV_IS_IN_ONENAND
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#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
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#endif
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#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
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#if defined(CONFIG_CMD_NET)
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/* Ethernet (SMSC9115 from SMSC9118 family) */
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#define CONFIG_SMC911X
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#define CONFIG_SMC911X_32_BIT
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#define CONFIG_SMC911X_BASE 0x2C000000
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/* BOOTP fields */
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#define CONFIG_BOOTP_SUBNETMASK 0x00000001
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#define CONFIG_BOOTP_GATEWAY 0x00000002
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#define CONFIG_BOOTP_HOSTNAME 0x00000004
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#define CONFIG_BOOTP_BOOTPATH 0x00000010
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#endif /* CONFIG_CMD_NET */
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/* Support for relocation */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
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#define CONFIG_SYS_INIT_RAM_SIZE 0x800
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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/* -----------------------------------------------------------------------------
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* Board specific
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* -----------------------------------------------------------------------------
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*/
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_HARD_I2C 1
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 1
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#define CONFIG_SYS_I2C_BUS 0
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#define CONFIG_SYS_I2C_BUS_SELECT 1
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#define CONFIG_DRIVER_OMAP34XX_I2C 1
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/*
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* TWL4030
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/* Uncomment to define the board revision statically */
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/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
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/* -----------------------------------------------------------------------------
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* Default environment
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* -----------------------------------------------------------------------------
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*/
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#define CONFIG_TWL4030_POWER 1
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/*
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* Board NAND Info.
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*/
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#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
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/* to access nand */
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access */
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/* nand at CS0 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
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/* NAND devices */
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#define CONFIG_JFFS2_NAND
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/* nand device jffs2 lives on */
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#define CONFIG_JFFS2_DEV "nand0"
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/* start of jffs2 partition */
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#define CONFIG_JFFS2_PART_OFFSET 0x680000
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#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
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/* Environment information */
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#define CONFIG_BOOTDELAY 10
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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@ -231,133 +390,4 @@
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"fi; " \
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"else run nandboot; fi"
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#define CONFIG_AUTO_COMPLETE 1
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_PROMPT "OMAP3_EVM # "
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command */
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/* args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
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#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
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0x01F00000) /* 31MB */
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
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/* address */
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/*
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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#define CONFIG_SYS_HZ 1000
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
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#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/* SDRAM Bank Allocation method */
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#define SDRC_R_B_C 1
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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/* **** PISMO SUPPORT *** */
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/* Configure the PISMO */
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#define PISMO1_NAND_SIZE GPMC_SIZE_128M
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#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
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#elif defined(CONFIG_CMD_ONENAND)
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#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
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#endif
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/* Monitor at start of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
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#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
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#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_NAND_OMAP_GPMC
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
|
||||
#elif defined(CONFIG_CMD_ONENAND)
|
||||
#define CONFIG_ENV_IS_IN_ONENAND 1
|
||||
#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
|
||||
#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
|
||||
|
||||
/*
|
||||
* Support for relocation
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/*
|
||||
* Define the board revision statically
|
||||
*/
|
||||
/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* SMSC9115 Ethernet from SMSC9118 family
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
|
||||
#define CONFIG_SMC911X
|
||||
#define CONFIG_SMC911X_32_BIT
|
||||
#define CONFIG_SMC911X_BASE 0x2C000000
|
||||
|
||||
#endif /* (CONFIG_CMD_NET) */
|
||||
|
||||
/*
|
||||
* BOOTP fields
|
||||
*/
|
||||
|
||||
#define CONFIG_BOOTP_SUBNETMASK 0x00000001
|
||||
#define CONFIG_BOOTP_GATEWAY 0x00000002
|
||||
#define CONFIG_BOOTP_HOSTNAME 0x00000004
|
||||
#define CONFIG_BOOTP_BOOTPATH 0x00000010
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user