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Add support for STX GP3SSA (stxssa) Board with 4 MiB flash.

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Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2007-05-31 17:20:09 +02:00
parent 9877d7dcd1
commit ee1529838a
3 changed files with 35 additions and 21 deletions
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12
Makefile
View File

@ -1771,8 +1771,16 @@ sbc8560_66_config: unconfig
stxgp3_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3
stxssa_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx stxssa
stxssa_config \
stxssa_4M_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _4M_,$@)" ] ; then \
echo "#define CONFIG_STXSSA_4M" >>$(obj)include/config.h ; \
echo "... with 4 MiB flash memory" ; \
else \
>$(obj)include/config.h ; \
fi
@$(MKCONFIG) -a stxssa ppc mpc85xx stxssa
TQM8540_config \
TQM8541_config \

3
board/stxssa/config.mk
View File

@ -22,13 +22,12 @@
# MA 02111-1307 USA
#
#
# default CCARBAR is at 0xff700000
# assume U-Boot is less than 0.5MB
# U-Boot is less than 256K, so push
# it further up into the flash
#
TEXT_BASE = 0xfffC0000
TEXT_BASE = 0xFFFC0000
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
PLATFORM_CPPFLAGS += -DCONFIG_E500=1

23
include/configs/stxssa.h
View File

@ -80,16 +80,20 @@
* This address, however, is used to configure a 256M local bus
* window that includes the Config latch below.
*/
#define CFG_LBC_OPTION_BASE 0xf0000000 /* Localbus Extension */
#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
#define CFG_LBC_OPTION_SIZE 256 /* 256MB */
/* There are various flash options used, we configure for the largest,
* which is 64Mbytes. The CFI works fine and will discover the proper
* sizes.
*/
#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH 64M */
#define CFG_BR0_PRELIM 0xFC001801 /* port size 32bit */
#define CFG_OR0_PRELIM 0xFC000FF7 /* 64 MB Flash */
#ifdef CONFIG_STXSSA_4M
#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
#else
#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
#endif
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x1801) /* port size 32bit */
#define CFG_OR0_PRELIM (CFG_FLASH_BASE | 0x0FF7)
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
@ -104,9 +108,9 @@
/* The configuration latch is Chip Select 1.
* It's an 8-bit latch in the lower 8 bits of the word.
*/
#define CFG_LBC_CFGLATCH_BASE 0xfb000000 /* Base of config latch */
#define CFG_BR1_PRELIM 0xfb001801 /* 32-bit port */
#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
#define CFG_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
#define CFG_BR1_PRELIM 0xFB001801 /* 32-bit port */
#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
@ -305,8 +309,11 @@
# define CFG_ENV_SIZE 2048
#else /* in flash */
# define CFG_ENV_IS_IN_FLASH 1
# ifdef CONFIG_STXSSA_4M
# define CFG_ENV_SECT_SIZE 0x20000
# else /* default configuration - 64 MiB flash */
# define CFG_ENV_SECT_SIZE 0x40000
# endif
# define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
# define CFG_ENV_SIZE 0x4000
# define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)