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ram: rk3399: Add ddrtimingC0

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Add DdrTimingC0 structure with associated bit fields.

These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki 2019-07-16 17:27:05 +05:30 committed by Kever Yang
parent b713e0291b
commit ed77ce728a
2 changed files with 12 additions and 2 deletions
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12
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
View File

@ -18,6 +18,16 @@ struct rk3399_ddr_pi_regs {
u32 denali_pi[200];
};
union noc_ddrtimingc0 {
u32 d32;
struct {
unsigned burstpenalty : 4;
unsigned reserved0 : 4;
unsigned wrtomwr : 6;
unsigned reserved1 : 18;
} b;
};
struct rk3399_msch_regs {
u32 coreid;
u32 revisionid;
@ -36,7 +46,7 @@ struct rk3399_msch_regs {
struct rk3399_msch_timings {
u32 ddrtiminga0;
u32 ddrtimingb0;
u32 ddrtimingc0;
union noc_ddrtimingc0 ddrtimingc0;
u32 devtodev0;
u32 ddrmode;
u32 agingx0;

2
drivers/ram/rockchip/sdram_rk3399.c
View File

@ -1110,7 +1110,7 @@ static void dram_all_config(struct dram_info *dram,
&ddr_msch_regs->ddrtiminga0);
writel(noc_timing->ddrtimingb0,
&ddr_msch_regs->ddrtimingb0);
writel(noc_timing->ddrtimingc0,
writel(noc_timing->ddrtimingc0.d32,
&ddr_msch_regs->ddrtimingc0);
writel(noc_timing->devtodev0,
&ddr_msch_regs->devtodev0);