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board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue

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Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register
to avoid the voltage peak issue while we do the IEEE PHY comformance test

Signed-off-by: Ken Lin <yungching0725@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Ian Ray <ian.ray@ge.com>
This commit is contained in:
Yung-Ching LIN 2017-02-21 09:56:56 +08:00 committed by Joe Hershberger
parent d42db168e6
commit ec7aa8fd67
1 changed files with 2 additions and 1 deletions
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3
board/ge/bx50v3/bx50v3.c
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@ -307,7 +307,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev)
/* set debug port address: SerDes Test and System Mode Control */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
/* enable rgmii tx clock delay */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
/* set the reserved bits to avoid board specific voltage peak issue*/
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
return 0;
}