arm: meson: Add supplementary ethernet registers definitions
On Amlogic Meson GXL/GXM, supplementary ethernet configuration registers were added to configure the internal RMII PHY interface. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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@ -22,11 +22,14 @@
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#define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50)
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#define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51)
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#define GXBB_ETH_REG_2 GXBB_PERIPHS_ADDR(0x56)
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#define GXBB_ETH_REG_3 GXBB_PERIPHS_ADDR(0x57)
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#define GXBB_ETH_REG_0_PHY_INTF BIT(0)
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#define GXBB_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
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#define GXBB_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
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#define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10)
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#define GXBB_ETH_REG_0_INVERT_RMII_CLK BIT(11)
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#define GXBB_ETH_REG_0_CLK_EN BIT(12)
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/* HIU registers */
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