* Added support for both PCMCIA slots (at the same time!) on MPC8xx
* Patch by Rod Boyce, 21 Nov 2002: fix PCMCIA on MBX8xx board * Patch by Pierre Aubert , 21 Nov 2002 Add CFG_CPM_POST_WORD_ADDR to make the offset of the bootmode word in DPRAM configurable
This commit is contained in:
wdenk
parent
b2184c314d
commit
ea909b7604
@ -2,6 +2,15 @@
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Changes since for U-Boot 0.1.0:
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======================================================================
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* Added support for both PCMCIA slots (at the same time!) on MPC8xx
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* Patch by Rod Boyce, 21 Nov 2002:
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fix PCMCIA on MBX8xx board
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* Patch by Pierre Aubert , 21 Nov 2002
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Add CFG_CPM_POST_WORD_ADDR to make the offset of the
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bootmode word in DPRAM configurable
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* Patch by Daniel Engström, 18 Nov 2002:
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Fixes for x86 port (mostly strings issues)
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6
README
6
README
@ -1653,6 +1653,12 @@ Low Level (hardware related) configuration options:
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wrong setting might damage your board. Read
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doc/README.MBX before setting this variable!
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- CFG_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only)
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Offset of the bootmode word in DPRAM used by post
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(Power On Self Tests). This definition overrides
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#define'd default value in commproc.h resp.
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cpm_8260.h.
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Building the Software:
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======================
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@ -171,7 +171,7 @@ Done:
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int flash_erase (flash_info_t *info, int s_first, int s_last)
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{
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ulong result;
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int iflag, cflag, prot, sect;
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int iflag, prot, sect;
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int rc = ERR_OK;
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int chip1, chip2;
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@ -285,4 +285,6 @@ int last_stage_init(void)
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minor |= ali512x_cio_in(20)?1:0;
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printf("AMD SC520 CDP revision %d.%d\n", major, minor);
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return 0;
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}
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@ -80,7 +80,7 @@ static int voltage_set(int slot, int vcc, int vpp);
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static void print_funcid (int func);
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static void print_fixed (volatile uchar *p);
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static int identify (volatile uchar *p);
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static int check_ide_device (void);
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static int check_ide_device (int slot);
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#endif /* CONFIG_IDE_8xx_PCCARD */
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static u_int m8xx_get_graycode(u_int size);
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@ -139,6 +139,8 @@ int pcmcia_on (void)
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int i;
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u_long reg, base;
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pcmcia_win_t *win;
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u_int slotbit;
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u_int rc, slot;
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debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
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@ -152,36 +154,42 @@ int pcmcia_on (void)
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return (1);
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}
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slotbit = PCMCIA_SLOT_x;
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for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
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win->br = base;
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#if (PCMCIA_SOCKETS_NO == 2)
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if (i == 4) /* Another slot starting from win 4 */
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slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B);
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#endif
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switch (i) {
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#ifdef CONFIG_IDE_8xx_PCCARD
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case 4:
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case 0: { /* map attribute memory */
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win->or = ( PCMCIA_BSIZE_64M
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| PCMCIA_PPS_8
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| PCMCIA_PRS_ATTR
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| PCMCIA_SLOT_x
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| slotbit
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| PCMCIA_PV
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| CFG_PCMCIA_TIMING );
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break;
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}
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case 5:
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case 1: { /* map I/O window for data reg */
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win->or = ( PCMCIA_BSIZE_1K
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| PCMCIA_PPS_16
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| PCMCIA_PRS_IO
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| PCMCIA_SLOT_x
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| slotbit
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| PCMCIA_PV
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| CFG_PCMCIA_TIMING );
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break;
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}
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case 6:
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case 2: { /* map I/O window for command/ctrl reg block */
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win->or = ( PCMCIA_BSIZE_1K
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| PCMCIA_PPS_8
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| PCMCIA_PRS_IO
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| PCMCIA_SLOT_x
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| slotbit
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| PCMCIA_PV
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| CFG_PCMCIA_TIMING );
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break;
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@ -198,19 +206,21 @@ int pcmcia_on (void)
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++win;
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}
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for (i = 0, rc = 0, slot = _slot_; i < PCMCIA_SOCKETS_NO; i++, slot = !slot) {
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/* turn off voltage */
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if (voltage_set(_slot_, 0, 0))
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return (1);
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if ((rc = voltage_set(slot, 0, 0)))
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continue;
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/* Enable external hardware */
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if (hardware_enable(_slot_))
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return (1);
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if ((rc = hardware_enable(slot)))
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continue;
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#ifdef CONFIG_IDE_8xx_PCCARD
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if (check_ide_device())
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return (1);
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if ((rc = check_ide_device(i)))
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continue;
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#endif
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return (0);
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}
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return (rc);
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}
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/* ------------------------------------------------------------------------- */
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@ -258,11 +268,11 @@ static int pcmcia_off (void)
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#define MAX_TUPEL_SZ 512
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#define MAX_FEATURES 4
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static int check_ide_device (void)
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static int check_ide_device (int slot)
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{
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volatile uchar *ident = NULL;
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volatile uchar *feature_p[MAX_FEATURES];
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volatile uchar *p, *start;
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volatile uchar *p, *start, *addr;
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int n_features = 0;
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uchar func_id = ~0;
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uchar code, len;
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@ -270,9 +280,11 @@ static int check_ide_device (void)
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int found = 0;
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int i;
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debug ("PCMCIA MEM: %08X\n", CFG_PCMCIA_MEM_ADDR);
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addr = (volatile uchar *)(CFG_PCMCIA_MEM_ADDR +
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CFG_PCMCIA_MEM_SIZE * (slot * 4));
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debug ("PCMCIA MEM: %08X\n", addr);
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start = p = (volatile uchar *) CFG_PCMCIA_MEM_ADDR;
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start = p = (volatile uchar *) addr;
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while ((p - start) < MAX_TUPEL_SZ) {
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@ -336,7 +348,7 @@ static int check_ide_device (void)
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}
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/* set I/O area in config reg -> only valid for ARGOSY D5!!! */
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*((uchar *)(CFG_PCMCIA_MEM_ADDR + config_base)) = 1;
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*((uchar *)(addr + config_base)) = 1;
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return (0);
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}
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@ -564,7 +576,7 @@ static int hardware_enable(int slot)
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debug ("[%d] %s: PIPR(%p)=0x%x\n",
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__LINE__,__FUNCTION__,
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&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
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if (pcmp->pcmc_pipr & 0x00001800) {
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if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
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printf (" No Card found\n");
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return (1);
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}
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@ -791,7 +803,7 @@ static int hardware_enable(int slot)
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debug ("[%d] %s: PIPR(%p)=0x%x\n",
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__LINE__,__FUNCTION__,
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&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
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if (pcmp->pcmc_pipr & 0x00001800) {
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if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
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printf (" No Card found\n");
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return (1);
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}
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@ -1096,7 +1108,7 @@ static int hardware_enable(int slot)
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debug ("[%d] %s: PIPR(%p)=0x%x\n",
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__LINE__,__FUNCTION__,
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&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
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if (pcmp->pcmc_pipr & 0x00001800) {
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if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
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printf (" No Card found\n");
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return (1);
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}
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@ -1366,7 +1378,7 @@ static int hardware_enable(int slot)
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debug ("[%d] %s: PIPR(%p)=0x%x\n",
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__LINE__,__FUNCTION__,
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&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
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if (pcmp->pcmc_pipr & 0x00001800) {
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if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
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printf (" No Card found\n");
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return (1);
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}
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@ -1694,11 +1706,11 @@ static int hardware_enable (int slot)
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/*
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* Make sure there is a card in the slot, then configure the interface.
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*/
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udelay (10000);
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debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__, __FUNCTION__,
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&(pcmp->pcmc_pipr), pcmp->pcmc_pipr);
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if (pcmp->pcmc_pipr & 0x00001800) {
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udelay(10000);
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debug ("[%d] %s: PIPR(%p)=0x%x\n",
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__LINE__,__FUNCTION__,
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&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
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if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
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printf (" No Card found\n");
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return (1);
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}
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@ -1816,7 +1828,7 @@ static int hardware_enable(int slot)
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debug ("[%d] %s: PIPR(%p)=0x%x\n",
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__LINE__,__FUNCTION__,
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&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
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if (pcmp->pcmc_pipr & 0x00001800) {
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if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
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printf (" No Card found\n");
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return (1);
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}
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@ -2008,32 +2020,33 @@ static int hardware_enable(int slot)
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sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */
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/* clear interrupt state, and disable interrupts */
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pcmp->pcmc_pscr = PCMCIA_MASK(_slot_);
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pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
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pcmp->pcmc_pscr = PCMCIA_MASK(slot);
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pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
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/* disable interrupts & DMA */
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PCMCIA_PGCRX(_slot_) = 0;
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PCMCIA_PGCRX(slot) = 0;
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/*
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* Disable PCMCIA buffers (isolate the interface)
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* and assert RESET signal
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*/
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debug ("Disable PCMCIA buffers and assert RESET\n");
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reg = PCMCIA_PGCRX(_slot_);
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reg = PCMCIA_PGCRX(slot);
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reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
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reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
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PCMCIA_PGCRX(_slot_) = reg;
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udelay(500);
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PCMCIA_PGCRX(slot) = reg;
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udelay(2500);
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/*
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* Configure Port B pins for
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* 3 Volts enable
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*/
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if (slot) { /* Slot A is built-in */
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cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3;
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cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3;
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/* remove all power */
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cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */
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}
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/*
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* Make sure there is a card in the slot, then configure the interface.
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*/
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@ -2041,7 +2054,7 @@ static int hardware_enable(int slot)
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debug ("[%d] %s: PIPR(%p)=0x%x\n",
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__LINE__,__FUNCTION__,
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&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
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if (pcmp->pcmc_pipr & 0x00001800) {
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if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
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printf (" No Card found\n");
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return (1);
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}
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@ -2049,6 +2062,7 @@ static int hardware_enable(int slot)
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/*
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* Power On.
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*/
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printf("\n Slot %c:", 'A' + slot);
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mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
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reg = pcmp->pcmc_pipr;
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debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
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@ -2058,6 +2072,7 @@ static int hardware_enable(int slot)
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if ((reg & mask) == mask) {
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puts (" 5.0V card found: NOT SUPPORTED !!!\n");
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} else {
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if(slot)
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cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3;
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puts (" 3.3V card found: ");
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}
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@ -2068,10 +2083,10 @@ static int hardware_enable(int slot)
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udelay(500000);
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#endif
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debug ("Enable PCMCIA buffers and stop RESET\n");
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reg = PCMCIA_PGCRX(_slot_);
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reg = PCMCIA_PGCRX(slot);
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reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
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reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
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PCMCIA_PGCRX(_slot_) = reg;
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PCMCIA_PGCRX(slot) = reg;
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udelay(250000); /* some cards need >150 ms to come up :-( */
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@ -2097,16 +2112,17 @@ static int hardware_disable(int slot)
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cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
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/* remove all power */
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cp->cp_pbdat |= DDC4000_PCMCIA_B_3V3;
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if (slot)
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cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3;
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/* Configure PCMCIA General Control Register */
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PCMCIA_PGCRX(_slot_) = 0;
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PCMCIA_PGCRX(slot) = 0;
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debug ("Disable PCMCIA buffers and assert RESET\n");
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reg = PCMCIA_PGCRX(_slot_);
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reg = PCMCIA_PGCRX(slot);
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reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
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reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
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PCMCIA_PGCRX(_slot_) = reg;
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PCMCIA_PGCRX(slot) = reg;
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udelay(10000);
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@ -2128,6 +2144,9 @@ static int voltage_set(int slot, int vcc, int vpp)
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" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
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'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
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if (!slot) /* Slot A is not configurable */
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return 0;
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immap = (immap_t *)CFG_IMMR;
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pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
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cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
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@ -2137,10 +2156,10 @@ static int voltage_set(int slot, int vcc, int vpp)
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* and assert RESET signal
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*/
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debug ("Disable PCMCIA buffers and assert RESET\n");
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reg = PCMCIA_PGCRX(_slot_);
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reg = PCMCIA_PGCRX(slot);
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reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
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reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
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PCMCIA_PGCRX(_slot_) = reg;
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PCMCIA_PGCRX(slot) = reg;
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udelay(500);
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debug ("PCMCIA power OFF\n");
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@ -2166,21 +2185,21 @@ static int voltage_set(int slot, int vcc, int vpp)
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puts("PCMCIA: vcc not supported");
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break;
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}
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udelay(10000);
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/* Checking supported voltages */
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debug ("PIPR: 0x%x --> %s\n",
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pcmp->pcmc_pipr,
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(pcmp->pcmc_pipr & 0x00008000)
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(pcmp->pcmc_pipr & (0x80000000 >> (slot << 4)))
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? "only 5 V --> NOT SUPPORTED"
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: "can do 3.3V");
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debug ("Enable PCMCIA buffers and stop RESET\n");
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reg = PCMCIA_PGCRX(_slot_);
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reg = PCMCIA_PGCRX(slot);
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reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
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reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
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PCMCIA_PGCRX(_slot_) = reg;
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PCMCIA_PGCRX(slot) = reg;
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udelay(500);
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debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
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@ -131,11 +131,15 @@ LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
|
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ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc)
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BFD_ROOT_DIR = /usr/local/tools
|
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else
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ifeq ($(HOSTARCH),$(ARCH))
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# native
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BFD_ROOT_DIR = /usr
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else
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#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386
|
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#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386
|
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#BFD_ROOT_DIR = /usr # native
|
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BFD_ROOT_DIR = /opt/powerpc
|
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endif
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endif
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#########################################################################
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@ -12,6 +12,7 @@
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#include <common.h>
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#ifdef CONFIG_PCI
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#ifndef __I386__
|
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|
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#include <asm/processor.h>
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#include <asm/io.h>
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@ -72,3 +73,4 @@ void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
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}
|
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|
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#endif
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#endif
|
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@ -136,7 +136,11 @@ typedef struct cpm_buf_desc {
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|
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/* Parameter RAM offsets from the base.
|
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*/
|
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#ifndef CFG_CPM_POST_WORD_ADDR
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#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */
|
||||
#else
|
||||
#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR
|
||||
#endif
|
||||
#define PROFF_SCC1 ((uint)0x8000)
|
||||
#define PROFF_SCC2 ((uint)0x8100)
|
||||
#define PROFF_SCC3 ((uint)0x8200)
|
||||
|
||||
@ -77,7 +77,11 @@
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef CFG_CPM_POST_WORD_ADDR
|
||||
#define CPM_POST_WORD_ADDR 0x07FC
|
||||
#else
|
||||
#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR
|
||||
#endif
|
||||
|
||||
#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
|
||||
|
||||
|
||||
@ -270,7 +270,8 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#define CONFIG_PCMCIA_SLOT_B 1 /* KUP4K use SLOT_B */
|
||||
/* KUP4K use both slots, SLOT_A as "primary". */
|
||||
#define CONFIG_PCMCIA_SLOT_A 1
|
||||
|
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
|
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
@ -281,6 +282,8 @@
|
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
|
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
|
||||
#define PCMCIA_SOCKETS_NO 2
|
||||
#define PCMCIA_MEM_WIN_NO 8
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
||||
*-----------------------------------------------------------------------
|
||||
@ -292,11 +295,13 @@
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
||||
#define CFG_IDE_MAXBUS 2
|
||||
#define CFG_IDE_MAXDEVICE 4
|
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE)
|
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
|
||||
|
||||
/* Offset for data I/O */
|
||||
|
||||
@ -74,6 +74,7 @@
|
||||
CFG_POST_CPU | \
|
||||
CFG_POST_UART | \
|
||||
CFG_POST_ETHER | \
|
||||
CFG_POST_I2C | \
|
||||
CFG_POST_SPI | \
|
||||
CFG_POST_USB | \
|
||||
CFG_POST_SPR)
|
||||
@ -116,16 +117,11 @@
|
||||
#undef CONFIG_STATUS_LED /* Status LED disabled */
|
||||
|
||||
/* enable I2C and select the hardware/software driver */
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
|
||||
|
||||
#ifdef CONFIG_HARD_I2C
|
||||
/*
|
||||
* Hardware (CPM) I2C driver configuration
|
||||
*/
|
||||
# define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
|
||||
# define CFG_I2C_SLAVE 0xFE
|
||||
#endif /* CONFIG_HARD_I2C */
|
||||
#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
|
||||
#define CFG_I2C_SLAVE 0xFE
|
||||
|
||||
#ifdef CONFIG_SOFT_I2C
|
||||
/*
|
||||
|
||||
@ -1,98 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Andreas Heppel <aheppel@sysgo.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* mpc75x.h
|
||||
*
|
||||
* MPC75x/MPC74xx specific definitions
|
||||
*/
|
||||
|
||||
#ifndef __MPC75X_H__
|
||||
#define __MPC75X_H__
|
||||
|
||||
/*----------------------------------------------------------------
|
||||
* Exception offsets (PowerPC standard)
|
||||
*/
|
||||
#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
|
||||
|
||||
/*----------------------------------------------------------------
|
||||
* l2cr values
|
||||
*/
|
||||
#define l2cr 1017
|
||||
|
||||
#define L2CR_L2E 0x80000000 /* bit 0 - enable */
|
||||
#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
|
||||
#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
|
||||
#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */
|
||||
#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */
|
||||
#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */
|
||||
#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */
|
||||
#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */
|
||||
#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */
|
||||
#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */
|
||||
#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */
|
||||
#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */
|
||||
#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */
|
||||
#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
|
||||
#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */
|
||||
#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
|
||||
#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
|
||||
#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */
|
||||
#define L2CR_TS 0x00040000 /* bit 13 - test support on */
|
||||
#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */
|
||||
#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */
|
||||
#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */
|
||||
#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */
|
||||
#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
|
||||
|
||||
/*----------------------------------------------------------------
|
||||
* BAT settings. Look in config_<BOARD>.h for the actual setup
|
||||
*/
|
||||
|
||||
#define BATU_BL_128K 0x00000000
|
||||
#define BATU_BL_256K 0x00000004
|
||||
#define BATU_BL_512K 0x0000000c
|
||||
#define BATU_BL_1M 0x0000001c
|
||||
#define BATU_BL_2M 0x0000003c
|
||||
#define BATU_BL_4M 0x0000007c
|
||||
#define BATU_BL_8M 0x000000fc
|
||||
#define BATU_BL_16M 0x000001fc
|
||||
#define BATU_BL_32M 0x000003fc
|
||||
#define BATU_BL_64M 0x000007fc
|
||||
#define BATU_BL_128M 0x00000ffc
|
||||
#define BATU_BL_256M 0x00001ffc
|
||||
|
||||
#define BATU_VS 0x00000002
|
||||
#define BATU_VP 0x00000001
|
||||
#define BATU_INVALID 0x00000000
|
||||
|
||||
#define BATL_WRITETHROUGH 0x00000080
|
||||
#define BATL_CACHEINHIBIT 0x00000040
|
||||
#define BATL_COHERENT 0x00000020
|
||||
#define BATL_GUARDED 0x00000010
|
||||
|
||||
#define BATL_NO_ACCESS 0x00000000
|
||||
#define BATL_RO 0x00000001
|
||||
#define BATL_RW 0x00000002
|
||||
|
||||
#endif /* __MPC75X_H__ */
|
||||
@ -76,8 +76,12 @@
|
||||
#error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
|
||||
#endif
|
||||
|
||||
#ifndef PCMCIA_SOCKETS_NO
|
||||
#define PCMCIA_SOCKETS_NO 1
|
||||
#endif
|
||||
#ifndef PCMCIA_MEM_WIN_NO
|
||||
#define PCMCIA_MEM_WIN_NO 4
|
||||
#endif
|
||||
#define PCMCIA_IO_WIN_NO 2
|
||||
|
||||
/* define _slot_ to be able to optimize macros */
|
||||
|
||||
@ -47,7 +47,7 @@ image_header_t *fake_header(image_header_t *hdr, void *ptr, int size)
|
||||
void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
|
||||
ulong addr, ulong *len_ptr, int verify)
|
||||
{
|
||||
ulong base_ptr;
|
||||
void *base_ptr;
|
||||
|
||||
ulong len = 0, checksum;
|
||||
ulong initrd_start, initrd_end;
|
||||
@ -150,7 +150,7 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
|
||||
initrd_end = 0;
|
||||
}
|
||||
|
||||
base_ptr = load_zimage(addr + sizeof(image_header_t), ntohl(hdr->ih_size),
|
||||
base_ptr = load_zimage((void*)addr + sizeof(image_header_t), ntohl(hdr->ih_size),
|
||||
initrd_start, initrd_end-initrd_start, 0);
|
||||
|
||||
if (NULL == base_ptr) {
|
||||
|
||||
@ -17,16 +17,16 @@
|
||||
#include <asm/io.h>
|
||||
#include <pci.h>
|
||||
|
||||
#define cfg_read(val, addr, type, op) *val = op((type)(addr))
|
||||
#define cfg_write(val, addr, type, op) op((val), (type *)(addr))
|
||||
#define cfg_read(val, addr, op) *val = op((int)(addr))
|
||||
#define cfg_write(val, addr, op) op((val), (int)(addr))
|
||||
|
||||
#define TYPE1_PCI_OP(rw, size, type, op, mask) \
|
||||
static int \
|
||||
type1_##rw##_config_##size(struct pci_controller *hose, \
|
||||
pci_dev_t dev, int offset, type val) \
|
||||
{ \
|
||||
outl(dev | (offset & 0xfc) | 0x80000000, hose->cfg_addr); \
|
||||
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
|
||||
outl(dev | (offset & 0xfc) | 0x80000000, (int)hose->cfg_addr); \
|
||||
cfg_##rw(val, hose->cfg_data + (offset & mask), op); \
|
||||
return 0; \
|
||||
}
|
||||
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/realmode.h>
|
||||
|
||||
|
||||
#define REALMODE_BASE ((char*)0x7c0)
|
||||
@ -44,16 +45,16 @@ int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out)
|
||||
/* copy the realmode switch code */
|
||||
if (i386boot_realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) {
|
||||
printf("realmode switch too large (%ld bytes, max is %d)\n",
|
||||
i386boot_realmode_size, (REALMODE_MAILBOX-REALMODE_BASE));
|
||||
i386boot_realmode_size, (int)(REALMODE_MAILBOX-REALMODE_BASE));
|
||||
return -1;
|
||||
}
|
||||
|
||||
memcpy(REALMODE_BASE, i386boot_realmode, i386boot_realmode_size);
|
||||
memcpy(REALMODE_BASE, (void*)i386boot_realmode, i386boot_realmode_size);
|
||||
|
||||
|
||||
in->eip = off;
|
||||
in->xcs = seg;
|
||||
if (3>in->esp & 0xffff) {
|
||||
if (3>(in->esp & 0xffff)) {
|
||||
printf("Warning: entering realmode with sp < 4 will fail\n");
|
||||
}
|
||||
|
||||
|
||||
10
post/cpu.c
10
post/cpu.c
@ -78,6 +78,7 @@ int cpu_post_test (int flags)
|
||||
int ic = icache_status ();
|
||||
int ret = 0;
|
||||
|
||||
WATCHDOG_RESET();
|
||||
if (ic)
|
||||
icache_disable ();
|
||||
|
||||
@ -89,15 +90,16 @@ int cpu_post_test (int flags)
|
||||
ret = cpu_post_test_two ();
|
||||
if (ret == 0)
|
||||
ret = cpu_post_test_twox ();
|
||||
WATCHDOG_RESET();
|
||||
if (ret == 0)
|
||||
ret = cpu_post_test_three ();
|
||||
if (ret == 0)
|
||||
ret = cpu_post_test_threex ();
|
||||
if (ret == 0)
|
||||
ret = cpu_post_test_threei ();
|
||||
WATCHDOG_RESET();
|
||||
if (ret == 0)
|
||||
ret = cpu_post_test_andi ();
|
||||
WATCHDOG_RESET();
|
||||
if (ret == 0)
|
||||
ret = cpu_post_test_srawi ();
|
||||
if (ret == 0)
|
||||
@ -106,25 +108,29 @@ int cpu_post_test (int flags)
|
||||
ret = cpu_post_test_rlwinm ();
|
||||
if (ret == 0)
|
||||
ret = cpu_post_test_rlwimi ();
|
||||
WATCHDOG_RESET();
|
||||
if (ret == 0)
|
||||
ret = cpu_post_test_store ();
|
||||
if (ret == 0)
|
||||
ret = cpu_post_test_load ();
|
||||
WATCHDOG_RESET();
|
||||
if (ret == 0)
|
||||
ret = cpu_post_test_cr ();
|
||||
if (ret == 0)
|
||||
ret = cpu_post_test_b ();
|
||||
WATCHDOG_RESET();
|
||||
if (ret == 0)
|
||||
ret = cpu_post_test_multi ();
|
||||
if (ret == 0)
|
||||
ret = cpu_post_test_string ();
|
||||
if (ret == 0)
|
||||
ret = cpu_post_test_complex ();
|
||||
WATCHDOG_RESET();
|
||||
|
||||
if (ic)
|
||||
icache_enable ();
|
||||
|
||||
WATCHDOG_RESET();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
11
post/post.c
11
post/post.c
@ -193,18 +193,21 @@ int post_run (char *name, int flags)
|
||||
(flags & test_flags[last] & POST_ALWAYS) &&
|
||||
(flags & test_flags[last] & POST_MEM)) {
|
||||
|
||||
post_run_single (post_list + last, test_flags[last],
|
||||
post_run_single (post_list + last,
|
||||
test_flags[last],
|
||||
flags | POST_REBOOT, last);
|
||||
|
||||
for (i = last + 1; i < post_list_size; i++) {
|
||||
post_run_single (post_list + i, test_flags[i],
|
||||
post_run_single (post_list + i,
|
||||
test_flags[i],
|
||||
flags, i);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i < post_list_size; i++) {
|
||||
post_run_single (post_list + i, test_flags[i], flags,
|
||||
i);
|
||||
post_run_single (post_list + i,
|
||||
test_flags[i],
|
||||
flags, i);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user