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MIPS: remove CONFIG_SYS_MHZ

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Resolve all uses of CONFIG_SYS_MHZ with the currently defined value.
Remove code which depends on CONFIG_SYS_MHZ but where no board configs
actually use that code.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Daniel Schwierzeck 2022-07-10 17:15:12 +02:00
parent ac14db1ca9
commit e9dcd5b402
10 changed files with 8 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/mips/mach-jz47xx/include/mach/jz4780.h
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@ -60,7 +60,7 @@
/* PLL setup */
#define JZ4780_SYS_EXTAL 48000000
#define JZ4780_SYS_MEM_SPEED (CONFIG_SYS_MHZ * 1000000)
#define JZ4780_SYS_MEM_SPEED (1200 * 1000000)
#define JZ4780_SYS_MEM_DIV 3
#define JZ4780_SYS_AUDIO_SPEED (768 * 1000000)

6
arch/mips/mach-jz47xx/jz4780/pll.c
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@ -399,11 +399,7 @@ static void cpu_mux_select(int pll)
((2 - 1) << CPM_CPCCR_L2DIV_BIT) |
((1 - 1) << CPM_CPCCR_CDIV_BIT);
if (CONFIG_SYS_MHZ >= 1000)
clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT;
else
clk_ctrl |= (6 - 1) << CPM_CPCCR_PDIV_BIT;
clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT;
clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl);
while (readl(cpm_regs + CPM_CPCSR) & (CPM_CPCSR_CDIV_BUSY |

4
board/imgtec/ci20/ci20.c
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@ -350,10 +350,6 @@ static const struct jz4780_ddr_config H5TQ2G83CFR_48_config = {
.pulldn = 0x0e,
};
#if (CONFIG_SYS_MHZ != 1200)
#error No DDR configuration for CPU speed
#endif
const struct jz4780_ddr_config *jz4780_get_ddr_config(void)
{
const int board_revision = ci20_revision();

3
include/configs/ap121.h
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@ -6,8 +6,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_MHZ 200
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000
#define CONFIG_SYS_SDRAM_BASE 0x80000000

3
include/configs/ap143.h
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@ -6,8 +6,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_MHZ 325
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
#define CONFIG_SYS_MIPS_TIMER_FREQ 325000000
#define CONFIG_SYS_SDRAM_BASE 0x80000000

3
include/configs/ap152.h
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@ -6,8 +6,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_MHZ 375
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
#define CONFIG_SYS_MIPS_TIMER_FREQ 375000000
#define CONFIG_SYS_SDRAM_BASE 0x80000000

3
include/configs/ci20.h
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@ -10,8 +10,7 @@
#define __CONFIG_CI20_H__
/* Ingenic JZ4780 clock configuration. */
#define CONFIG_SYS_MHZ 1200
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
#define CONFIG_SYS_MIPS_TIMER_FREQ 1200000000
/* Memory configuration */
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)

3
include/configs/malta.h
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@ -18,8 +18,7 @@
/*
* CPU Configuration
*/
#define CONFIG_SYS_MHZ 250 /* arbitrary value */
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
#define CONFIG_SYS_MIPS_TIMER_FREQ 250000000
/*
* Memory map

3
include/configs/tplink_wdr4300.h
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@ -6,8 +6,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_MHZ 280
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
#define CONFIG_SYS_MIPS_TIMER_FREQ 280000000
#define CONFIG_SYS_SDRAM_BASE 0xa0000000

1
scripts/config_whitelist.txt
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@ -872,7 +872,6 @@ CONFIG_SYS_MDIO1_OFFSET
CONFIG_SYS_MEMORY_BASE
CONFIG_SYS_MEM_RESERVE_SECURE
CONFIG_SYS_MFD
CONFIG_SYS_MHZ
CONFIG_SYS_MIPS_TIMER_FREQ
CONFIG_SYS_MMC_CD_PIN
CONFIG_SYS_MMC_CLK_OD