Clean up the TQM8xx_YYMHz configurations; allow to use the same
binary image for all clock frequencies. Implement run-time optimization of flash access timing based on the actual bus frequency.
This commit is contained in:
wdenk
parent
5cf91d6bdc
commit
e9132ea94c
@ -2,6 +2,11 @@
|
||||
Changes for U-Boot 1.1.1:
|
||||
======================================================================
|
||||
|
||||
* Clean up the TQM8xx_YYMHz configurations; allow to use the same
|
||||
binary image for all clok frequencies. Implement run-time
|
||||
optimization of flash access timing based on the actual bus
|
||||
frequency.
|
||||
|
||||
* Modify KUP4X board configuration to use SL811 driver for USB memory
|
||||
sticks (including FAT / VFAT filesystem support)
|
||||
|
||||
|
||||
46
Makefile
46
Makefile
@ -486,66 +486,26 @@ TOP860_config: unconfig
|
||||
@./mkconfig $(@:_config=) ppc mpc8xx top860 emk
|
||||
|
||||
# Play some tricks for configuration selection
|
||||
# All boards can come with 50 MHz (default), 66MHz, 80MHz or 100 MHz clock,
|
||||
# but only 855 and 860 boards may come with FEC
|
||||
# and 823 boards may have LCD support
|
||||
xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _100MHz,,$(subst _133MHz,,$(subst _LCD,,$(subst _config,,$1))))))
|
||||
# Only 855 and 860 boards may come with FEC
|
||||
# and only 823 boards may have LCD support
|
||||
xtract_8xx = $(subst _LCD,,$(subst _config,,$1))
|
||||
|
||||
FPS850L_config \
|
||||
FPS860L_config \
|
||||
NSCU_config \
|
||||
TQM823L_config \
|
||||
TQM823L_66MHz_config \
|
||||
TQM823L_80MHz_config \
|
||||
TQM823L_LCD_config \
|
||||
TQM823L_LCD_66MHz_config \
|
||||
TQM823L_LCD_80MHz_config \
|
||||
TQM850L_config \
|
||||
TQM850L_66MHz_config \
|
||||
TQM850L_80MHz_config \
|
||||
TQM855L_config \
|
||||
TQM855L_66MHz_config \
|
||||
TQM855L_80MHz_config \
|
||||
TQM860L_config \
|
||||
TQM860L_66MHz_config \
|
||||
TQM860L_80MHz_config \
|
||||
TQM862L_config \
|
||||
TQM862L_66MHz_config \
|
||||
TQM862L_80MHz_config \
|
||||
TQM823M_config \
|
||||
TQM823M_66MHz_config \
|
||||
TQM823M_80MHz_config \
|
||||
TQM850M_config \
|
||||
TQM850M_66MHz_config \
|
||||
TQM850M_80MHz_config \
|
||||
TQM855M_config \
|
||||
TQM855M_66MHz_config \
|
||||
TQM855M_80MHz_config \
|
||||
TQM860M_config \
|
||||
TQM860M_66MHz_config \
|
||||
TQM860M_80MHz_config \
|
||||
TQM862M_config \
|
||||
TQM862M_66MHz_config \
|
||||
TQM862M_80MHz_config \
|
||||
TQM862M_100MHz_config \
|
||||
TQM866M_config: unconfig
|
||||
@ >include/config.h
|
||||
@[ -z "$(findstring _66MHz,$@)" ] || \
|
||||
{ echo "#define CONFIG_66MHz" >>include/config.h ; \
|
||||
echo "... with 66MHz system clock" ; \
|
||||
}
|
||||
@[ -z "$(findstring _80MHz,$@)" ] || \
|
||||
{ echo "#define CONFIG_80MHz" >>include/config.h ; \
|
||||
echo "... with 80MHz system clock" ; \
|
||||
}
|
||||
@[ -z "$(findstring _100MHz,$@)" ] || \
|
||||
{ echo "#define CONFIG_100MHz" >>include/config.h ; \
|
||||
echo "... with 100MHz system clock" ; \
|
||||
}
|
||||
@[ -z "$(findstring _133MHz,$@)" ] || \
|
||||
{ echo "#define CONFIG_133MHz" >>include/config.h ; \
|
||||
echo "... with 133MHz system clock" ; \
|
||||
}
|
||||
@[ -z "$(findstring _LCD,$@)" ] || \
|
||||
{ echo "#define CONFIG_LCD" >>include/config.h ; \
|
||||
echo "#define CONFIG_NEC_NL6448BC20" >>include/config.h ; \
|
||||
|
||||
@ -29,6 +29,15 @@
|
||||
#include <mpc8xx.h>
|
||||
#include <environment.h>
|
||||
|
||||
#include <asm/processor.h>
|
||||
|
||||
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
|
||||
# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
|
||||
# define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
# endif
|
||||
#endif /* CONFIG_TQM8xxL/M, !TQM866M */
|
||||
|
||||
#ifndef CFG_ENV_ADDR
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
|
||||
#endif
|
||||
@ -51,6 +60,50 @@ unsigned long flash_init (void)
|
||||
unsigned long size_b0, size_b1;
|
||||
int i;
|
||||
|
||||
#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ
|
||||
int scy, trlx, flash_or_timing, clk_diff;
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
|
||||
if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
|
||||
trlx = OR_TRLX;
|
||||
scy *= 2;
|
||||
} else
|
||||
trlx = 0;
|
||||
|
||||
/* We assume that each 10MHz of bus clock require 1-clk SCY
|
||||
* adjustment.
|
||||
*/
|
||||
clk_diff = (gd->bus_clk / 1000000) - 50;
|
||||
|
||||
/* We need proper rounding here. This is what the "+5" and "-5"
|
||||
* are here for.
|
||||
*/
|
||||
if (clk_diff >= 0)
|
||||
scy += (clk_diff + 5) / 10;
|
||||
else
|
||||
scy += (clk_diff - 5) / 10;
|
||||
|
||||
/* For bus frequencies above 50MHz, we want to use relaxed timing
|
||||
* (OR_TRLX).
|
||||
*/
|
||||
if (gd->bus_clk >= 50000000)
|
||||
trlx = OR_TRLX;
|
||||
else
|
||||
trlx = 0;
|
||||
|
||||
if (trlx)
|
||||
scy /= 2;
|
||||
|
||||
if (scy > 0xf)
|
||||
scy = 0xf;
|
||||
if (scy < 1)
|
||||
scy = 1;
|
||||
|
||||
flash_or_timing = (scy << 4) | trlx |
|
||||
(CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
|
||||
#endif
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
@ -95,7 +148,11 @@ unsigned long flash_init (void)
|
||||
memctl->memc_br1, memctl->memc_or1);
|
||||
|
||||
/* Remap FLASH according to real size */
|
||||
#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
|
||||
memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
|
||||
#else
|
||||
memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK);
|
||||
#endif
|
||||
memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
|
||||
|
||||
debug ("## BR0: 0x%08x OR0: 0x%08x\n",
|
||||
@ -146,7 +203,11 @@ unsigned long flash_init (void)
|
||||
#endif
|
||||
|
||||
if (size_b1) {
|
||||
#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
|
||||
memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
|
||||
#else
|
||||
memctl->memc_or1 = flash_or_timing | (-size_b1 & 0xFFFF8000);
|
||||
#endif
|
||||
memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
|
||||
BR_MS_GPCM | BR_V;
|
||||
|
||||
|
||||
@ -347,4 +347,32 @@ static long init_pll_866 (long clk)
|
||||
|
||||
#endif /* CONFIG_MPC866_et_al */
|
||||
|
||||
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
|
||||
/*
|
||||
* Adjust sdram refresh rate to actual CPU clock
|
||||
* and set timebase source according to actual CPU clock
|
||||
*/
|
||||
int adjust_sdram_tbs_8xx (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
||||
long mamr;
|
||||
long sccr;
|
||||
|
||||
mamr = immr->im_memctl.memc_mamr;
|
||||
mamr &= ~MAMR_PTA_MSK;
|
||||
mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
|
||||
immr->im_memctl.memc_mamr = mamr;
|
||||
|
||||
if (gd->cpu_clk < 67000000) {
|
||||
sccr = immr->im_clkrst.car_sccr;
|
||||
sccr |= SCCR_TBS;
|
||||
immr->im_clkrst.car_sccr = sccr;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
#endif /* CONFIG_TQM8xxL/M, !TQM866M */
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
@ -372,6 +372,7 @@ int serial_tstc (void);
|
||||
int get_clocks (void);
|
||||
int get_clocks_866 (void);
|
||||
int sdram_adjust_866 (void);
|
||||
int adjust_sdram_tbs_8xx (void);
|
||||
#if defined(CONFIG_8260)
|
||||
int prt_8260_clks (void);
|
||||
#endif
|
||||
|
||||
@ -262,15 +262,8 @@
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
@ -279,17 +272,9 @@
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
@ -358,19 +343,8 @@
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
@ -431,13 +405,9 @@
|
||||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
||||
@ -254,15 +254,8 @@
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
@ -271,17 +264,9 @@
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
@ -350,19 +335,8 @@
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
@ -423,13 +397,9 @@
|
||||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
||||
@ -245,15 +245,8 @@
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
@ -262,17 +255,9 @@
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
@ -341,19 +326,8 @@
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
@ -414,13 +388,9 @@
|
||||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
||||
@ -244,15 +244,8 @@
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
@ -261,17 +254,9 @@
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
@ -340,19 +325,8 @@
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
@ -413,13 +387,9 @@
|
||||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
||||
@ -248,15 +248,8 @@
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
@ -265,17 +258,9 @@
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
@ -344,19 +329,8 @@
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
@ -417,13 +391,9 @@
|
||||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
||||
@ -283,15 +283,8 @@
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
@ -300,17 +293,9 @@
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
@ -379,19 +364,8 @@
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
@ -452,13 +426,9 @@
|
||||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
||||
@ -249,15 +249,8 @@
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
@ -266,17 +259,9 @@
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
@ -345,19 +330,8 @@
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
@ -418,13 +392,9 @@
|
||||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
||||
@ -250,15 +250,8 @@
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
@ -267,17 +260,9 @@
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
@ -346,19 +331,8 @@
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
@ -419,13 +393,9 @@
|
||||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
||||
@ -252,16 +252,8 @@
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz or 100 MHz CPU,
|
||||
* set PLL multiplication factor to 5 (5 * 16 = 80, 5 * 20 = 100)
|
||||
*/
|
||||
#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz)
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz | CONFIG_100MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
@ -270,17 +262,9 @@
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) /* use 16/20 MHz * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz | CONFIG_100MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
@ -349,24 +333,8 @@
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_100MHz)
|
||||
/* 100 MHz CPU - 50 MHz bus:
|
||||
* ACS = 01, TRLX = 0, CSNT = 0, SCY = 7, EHTR = 0 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV4 | OR_SCY_7_CLK | OR_BI)
|
||||
#elif defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus:
|
||||
* ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
@ -428,15 +396,9 @@
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
* 100 Mhz => 100.000.000 / Divider = 195
|
||||
*/
|
||||
#if defined(CONFIG_100MHz)
|
||||
#define CFG_MAMR_PTA 195
|
||||
#elif defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
||||
@ -253,16 +253,8 @@
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz or 100 MHz CPU,
|
||||
* set PLL multiplication factor to 5 (5 * 16 = 80, 5 * 20 = 100)
|
||||
*/
|
||||
#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz)
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz | CONFIG_100MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
@ -271,17 +263,9 @@
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) /* use 16/20 MHz * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz | CONFIG_100MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
@ -350,24 +334,8 @@
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_100MHz)
|
||||
/* 100 MHz CPU - 50 MHz bus:
|
||||
* ACS = 01, TRLX = 0, CSNT = 0, SCY = 7, EHTR = 0 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV4 | OR_SCY_7_CLK | OR_BI)
|
||||
#elif defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus:
|
||||
* ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
@ -429,15 +397,9 @@
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
* 100 Mhz => 100.000.000 / Divider = 195
|
||||
*/
|
||||
#if defined(CONFIG_100MHz)
|
||||
#define CFG_MAMR_PTA 195
|
||||
#elif defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
||||
@ -265,6 +265,9 @@ init_fnc_t *init_sequence[] = {
|
||||
|
||||
#if !defined(CONFIG_TQM866M)
|
||||
get_clocks, /* get CPU and bus clocks (etc.) */
|
||||
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
|
||||
adjust_sdram_tbs_8xx,
|
||||
#endif
|
||||
init_timebase,
|
||||
#endif
|
||||
#ifdef CFG_ALLOC_DPRAM
|
||||
|
||||
Loading…
Reference in New Issue
Block a user