net: ftgmac100: convert the RX/TX descriptor arrays
Use simple arrays under the device priv structure to hold the RX and TX descriptors and handle memory coherency by invalidating or flushing the d-cache when required. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Cédric Le Goater
Joe Hershberger
parent
538e75d3fc
commit
e766849713
@ -13,19 +13,17 @@
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#include <dm.h>
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#include <miiphy.h>
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#include <malloc.h>
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#include <net.h>
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#include <linux/io.h>
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#include <asm/dma-mapping.h>
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#include <linux/iopoll.h>
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#include "ftgmac100.h"
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#define ETH_ZLEN 60
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#define CFG_XBUF_SIZE 1536
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/* Min frame ethernet frame size without FCS */
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#define ETH_ZLEN 60
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/* RBSR - hw default init value is also 0x640 */
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#define RBSR_DEFAULT_VALUE 0x640
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/* Receive Buffer Size Register - HW default is 0x640 */
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#define FTGMAC100_RBSR_DEFAULT 0x640
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/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
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#define PKTBUFSTX 4 /* must be power of 2 */
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@ -57,10 +55,8 @@
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struct ftgmac100_data {
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struct ftgmac100 *iobase;
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ulong txdes_dma;
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struct ftgmac100_txdes *txdes;
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ulong rxdes_dma;
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struct ftgmac100_rxdes *rxdes;
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struct ftgmac100_txdes txdes[PKTBUFSTX];
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struct ftgmac100_rxdes rxdes[PKTBUFSRX];
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int tx_index;
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int rx_index;
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@ -266,10 +262,8 @@ static int ftgmac100_start(struct udevice *dev)
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struct ftgmac100_data *priv = dev_get_priv(dev);
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struct ftgmac100 *ftgmac100 = priv->iobase;
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struct phy_device *phydev = priv->phydev;
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struct ftgmac100_txdes *txdes;
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struct ftgmac100_rxdes *rxdes;
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unsigned int maccr;
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void *buf;
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ulong start, end;
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int ret;
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int i;
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@ -277,26 +271,6 @@ static int ftgmac100_start(struct udevice *dev)
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ftgmac100_reset(priv);
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if (!priv->txdes) {
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txdes = dma_alloc_coherent(
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sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma);
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if (!txdes)
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panic("ftgmac100: out of memory\n");
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memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
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priv->txdes = txdes;
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}
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txdes = priv->txdes;
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if (!priv->rxdes) {
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rxdes = dma_alloc_coherent(
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sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma);
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if (!rxdes)
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panic("ftgmac100: out of memory\n");
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memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
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priv->rxdes = rxdes;
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}
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rxdes = priv->rxdes;
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/* set the ethernet address */
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ftgmac100_set_mac(priv, plat->enetaddr);
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@ -307,42 +281,37 @@ static int ftgmac100_start(struct udevice *dev)
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priv->tx_index = 0;
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priv->rx_index = 0;
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txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
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rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
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for (i = 0; i < PKTBUFSTX; i++) {
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/* TXBUF_BADR */
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if (!txdes[i].txdes2) {
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buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
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if (!buf)
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panic("ftgmac100: out of memory\n");
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txdes[i].txdes3 = virt_to_phys(buf);
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txdes[i].txdes2 = (uint)buf;
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}
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txdes[i].txdes1 = 0;
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priv->txdes[i].txdes3 = 0;
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priv->txdes[i].txdes0 = 0;
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}
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priv->txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
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start = (ulong)&priv->txdes[0];
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end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
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flush_dcache_range(start, end);
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for (i = 0; i < PKTBUFSRX; i++) {
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/* RXBUF_BADR */
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if (!rxdes[i].rxdes2) {
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buf = net_rx_packets[i];
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rxdes[i].rxdes3 = virt_to_phys(buf);
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rxdes[i].rxdes2 = (uint)buf;
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}
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rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
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priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
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priv->rxdes[i].rxdes0 = 0;
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}
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priv->rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
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start = (ulong)&priv->rxdes[0];
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end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
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flush_dcache_range(start, end);
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/* transmit ring */
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writel(priv->txdes_dma, &ftgmac100->txr_badr);
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writel((u32)priv->txdes, &ftgmac100->txr_badr);
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/* receive ring */
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writel(priv->rxdes_dma, &ftgmac100->rxr_badr);
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writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
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/* poll receive descriptor automatically */
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writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
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/* config receive buffer size register */
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writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr);
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writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
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/* enable transmitter, receiver */
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maccr = FTGMAC100_MACCR_TXMAC_EN |
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@ -378,9 +347,13 @@ static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
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{
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struct ftgmac100_data *priv = dev_get_priv(dev);
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struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
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ulong des_start = (ulong)curr_des;
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ulong des_end = des_start +
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roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
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/* Release buffer to DMA */
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/* Release buffer to DMA and flush descriptor */
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curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
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flush_dcache_range(des_start, des_end);
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/* Move to next descriptor */
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priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
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@ -394,20 +367,25 @@ static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
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static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct ftgmac100_data *priv = dev_get_priv(dev);
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struct ftgmac100_rxdes *curr_des;
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struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
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unsigned short rxlen;
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ulong des_start = (ulong)curr_des;
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ulong des_end = des_start +
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roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
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ulong data_start = curr_des->rxdes3;
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ulong data_end;
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curr_des = &priv->rxdes[priv->rx_index];
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invalidate_dcache_range(des_start, des_end);
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if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
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return -1;
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return -EAGAIN;
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if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
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FTGMAC100_RXDES0_CRC_ERR |
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FTGMAC100_RXDES0_FTL |
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FTGMAC100_RXDES0_RUNT |
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FTGMAC100_RXDES0_RX_ODD_NB)) {
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return -1;
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return -EAGAIN;
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}
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rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
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@ -415,18 +393,12 @@ static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
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debug("%s(): RX buffer %d, %x received\n",
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__func__, priv->rx_index, rxlen);
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/* invalidate d-cache */
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dma_map_single((void *)curr_des->rxdes2, rxlen, DMA_FROM_DEVICE);
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/* Invalidate received data */
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data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
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invalidate_dcache_range(data_start, data_end);
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*packetp = (uchar *)data_start;
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/* pass the packet up to the protocol layers. */
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net_process_received_packet((void *)curr_des->rxdes2, rxlen);
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/* release buffer to DMA */
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curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
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priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
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return 0;
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return rxlen;
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}
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/*
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@ -437,31 +409,46 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length)
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struct ftgmac100_data *priv = dev_get_priv(dev);
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struct ftgmac100 *ftgmac100 = priv->iobase;
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struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
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ulong des_start = (ulong)curr_des;
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ulong des_end = des_start +
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roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
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ulong data_start;
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ulong data_end;
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invalidate_dcache_range(des_start, des_end);
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if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
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debug("%s(): no TX descriptor available\n", __func__);
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return -1;
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dev_err(dev, "no TX descriptor available\n");
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return -EPERM;
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}
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debug("%s(%x, %x)\n", __func__, (int)packet, length);
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length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
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memcpy((void *)curr_des->txdes2, (void *)packet, length);
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dma_map_single((void *)curr_des->txdes2, length, DMA_TO_DEVICE);
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curr_des->txdes3 = (unsigned int)packet;
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/* only one descriptor on TXBUF */
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/* Flush data to be sent */
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data_start = curr_des->txdes3;
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data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
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flush_dcache_range(data_start, data_end);
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/* Only one segment on TXBUF */
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curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
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curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
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FTGMAC100_TXDES0_LTS |
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FTGMAC100_TXDES0_TXBUF_SIZE(length) |
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FTGMAC100_TXDES0_TXDMA_OWN ;
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/* start transmit */
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/* Flush modified buffer descriptor */
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flush_dcache_range(des_start, des_end);
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/* Start transmit */
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writel(1, &ftgmac100->txpd);
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debug("%s(): packet sent\n", __func__);
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/* Move to next descriptor */
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priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
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return 0;
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