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Merge branch 'master' of git://git.denx.de/u-boot

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This commit is contained in:
Stefano Babic 2015-02-13 11:17:01 +01:00
commit e72d344386
1061 changed files with 48502 additions and 24941 deletions
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5
Kconfig
View File

@ -116,8 +116,9 @@ config FIT_VERBOSE
depends on FIT
config FIT_SIGNATURE
bool "Enabel signature verification of FIT uImages"
bool "Enable signature verification of FIT uImages"
depends on FIT
select RSA
help
This option enables signature verification of FIT uImages,
using a hash signed and verified using RSA.
@ -138,7 +139,7 @@ config SYS_EXTRA_OPTIONS
new boards should not use this option.
config SYS_TEXT_BASE
depends on SPARC
depends on SPARC || ARC
hex "Text Base"
help
TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture

2
MAINTAINERS
View File

@ -170,7 +170,7 @@ T: git git://git.denx.de/u-boot-uniphier.git
F: arch/arm/cpu/armv7/uniphier/
F: arch/arm/include/asm/arch-uniphier/
F: configs/ph1_*_defconfig
F: drivers/serial/serial_uniphier.c
N: uniphier
ARM ZYNQ
M: Michal Simek <monstr@monstr.eu>

24
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 2015
PATCHLEVEL = 01
PATCHLEVEL = 04
SUBLEVEL =
EXTRAVERSION =
EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
@ -729,8 +729,9 @@ ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
endif
ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
# We can't do this yet due to the need for binary blobs
# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
ifneq ($(BUILD_ROM),)
ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
endif
# enable combined SPL/u-boot/dtb rules for tegra
ifneq ($(CONFIG_TEGRA),)
@ -776,6 +777,13 @@ ifneq ($(CONFIG_SYS_GENERIC_BOARD),y)
@echo "See doc/README.generic-board for further information"
@echo "===================================================="
endif
ifeq ($(CONFIG_DM_I2C_COMPAT),y)
@echo "===================== WARNING ======================"
@echo "This board uses CONFIG_DM_I2C_COMPAT. Please remove"
@echo "(possibly in a subsequent patch in your series)"
@echo "before sending patches to the mailing list."
@echo "===================================================="
endif
PHONY += dtbs
dtbs dts/dt.dtb: checkdtc u-boot
@ -849,12 +857,18 @@ MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
$(call if_changed,mkimage)
u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
u-boot-dtb.img: u-boot-dtb.bin FORCE
@ -1278,7 +1292,7 @@ CLEAN_DIRS += $(MODVERDIR) \
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
u-boot* MLO* SPL System.map
boot* u-boot* MLO* SPL System.map
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated spl tpl \

17
README
View File

@ -1257,6 +1257,9 @@ The following options need to be configured:
SoC, then define this variable and provide board
specific code for the "hw_watchdog_reset" function.
CONFIG_AT91_HW_WDT_TIMEOUT
specify the timeout in seconds. default 2 seconds.
- U-Boot Version:
CONFIG_VERSION_VARIABLE
If this variable is defined, an environment variable
@ -3176,8 +3179,13 @@ CBFS (Coreboot Filesystem) support
This enables the RSA algorithm used for FIT image verification
in U-Boot. See doc/uImage.FIT/signature.txt for more information.
The Modular Exponentiation algorithm in RSA is implemented using
driver model. So CONFIG_DM needs to be enabled by default for this
library to function.
The signing part is build into mkimage regardless of this
option.
option. The software based modular exponentiation is built into
mkimage irrespective of this option.
- bootcount support:
CONFIG_BOOTCOUNT_LIMIT
@ -5899,9 +5907,10 @@ option performs the converse operation of the mkimage's second form (the "-d"
option). Given an image built by mkimage, the dumpimage extracts a "data file"
from the image:
tools/dumpimage -i image -p position data_file
-i ==> extract from the 'image' a specific 'data_file', \
indexed by 'position'
tools/dumpimage -i image -T type -p position data_file
-i ==> extract from the 'image' a specific 'data_file'
-T ==> set image type to 'type'
-p ==> 'position' (starting at 0) of the 'data_file' inside the 'image'
Installing a Linux Image:

1
arch/Kconfig
View File

@ -4,6 +4,7 @@ choice
config ARC
bool "ARC architecture"
select HAVE_PRIVATE_LIBGCC
config ARM
bool "ARM architecture"

74
arch/arc/Kconfig
View File

@ -4,6 +4,77 @@ menu "ARC architecture"
config SYS_ARCH
default "arc"
config USE_PRIVATE_LIBGCC
default y
config SYS_CPU
default "arcv1"
choice
prompt "CPU selection"
default CPU_ARC770D
config CPU_ARC750D
bool "ARC 750D"
select ARC_MMU_V2
help
Choose this option to build an U-Boot for ARC750D CPU.
config CPU_ARC770D
bool "ARC 770D"
select ARC_MMU_V3
help
Choose this option to build an U-Boot for ARC770D CPU.
endchoice
choice
prompt "MMU Version"
default ARC_MMU_V3 if CPU_ARC770D
default ARC_MMU_V2 if CPU_ARC750D
config ARC_MMU_V2
bool "MMU v2"
depends on CPU_ARC750D
help
Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
when 2 D-TLB and 1 I-TLB entries index into same 2way set.
config ARC_MMU_V3
bool "MMU v3"
depends on CPU_ARC770D
help
Introduced with ARC700 4.10: New Features
Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
Shared Address Spaces (SASID)
endchoice
config CPU_BIG_ENDIAN
bool "Enable Big Endian Mode"
default n
help
Build kernel for Big Endian Mode of ARC CPU
config SYS_ICACHE_OFF
bool "Do not use Instruction Cache"
default n
config SYS_DCACHE_OFF
bool "Do not use Data Cache"
default n
config ARC_CACHE_LINE_SHIFT
int "Cache Line Length (as power of 2)"
range 5 7
default "6"
depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF
help
Starting with ARC700 4.9, Cache line length is configurable,
This option specifies "N", with Line-len = 2 power N
So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
Linux only supports same line lengths for I and D caches.
choice
prompt "Target select"
@ -13,9 +84,6 @@ config TARGET_TB100
config TARGET_ARCANGEL4
bool "Support arcangel4"
config TARGET_ARCANGEL4_BE
bool "Support arcangel4-be"
config TARGET_AXS101
bool "Support axs101"

2
arch/arc/Makefile
View File

@ -2,8 +2,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
head-y := arch/arc/cpu/$(CPU)/start.o
libs-y += arch/arc/cpu/$(CPU)/
libs-y += arch/arc/lib/

19
arch/arc/config.mk
View File

@ -4,23 +4,40 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifndef CONFIG_SYS_BIG_ENDIAN
ifndef CONFIG_CPU_BIG_ENDIAN
CONFIG_SYS_LITTLE_ENDIAN = 1
else
CONFIG_SYS_BIG_ENDIAN = 1
endif
ifdef CONFIG_SYS_LITTLE_ENDIAN
ARC_CROSS_COMPILE := arc-buildroot-linux-uclibc-
PLATFORM_LDFLAGS += -EL
PLATFORM_CPPFLAGS += -mlittle-endian
endif
ifdef CONFIG_SYS_BIG_ENDIAN
ARC_CROSS_COMPILE := arceb-buildroot-linux-uclibc-
PLATFORM_LDFLAGS += -EB
PLATFORM_CPPFLAGS += -mbig-endian
endif
ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := $(ARC_CROSS_COMPILE)
endif
ifdef CONFIG_ARC_MMU_VER
CONFIG_MMU = 1
endif
ifdef CONFIG_CPU_ARC750D
PLATFORM_CPPFLAGS += -marc700
endif
ifdef CONFIG_CPU_ARC770D
PLATFORM_CPPFLAGS += -marc700 -mlock -mswape
endif
PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
# Needed for relocation

13
arch/arc/cpu/arc700/Makefile
View File

@ -1,13 +0,0 @@
#
# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: GPL-2.0+
#
extra-y += start.o
obj-y += cache.o
obj-y += cpu.o
obj-y += interrupts.o
obj-y += reset.o
obj-y += timer.o

2
arch/arc/cpu/arc700/config.mk → arch/arc/cpu/arcv1/Makefile
View File

@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_CPPFLAGS += -mA7
obj-y += start.o

77
arch/arc/cpu/arc700/start.S → arch/arc/cpu/arcv1/start.S
View File

@ -57,11 +57,13 @@
.endm
.macro SAVE_ALL_SYS
/* saving %r0 to reg->r0 in advance since we read %ecr into it */
st %r0, [%sp, -8]
lr %r0, [%ecr] /* all stack addressing is manual so far */
st %r0, [%sp]
lr %r0, [%ecr]
st %r0, [%sp, 8] /* ECR */
st %sp, [%sp, 4]
st %sp, [%sp, -4]
/* now move %sp to reg->r0 position so we can do "push" automatically */
sub %sp, %sp, 8
SAVE_R1_TO_R24
PUSH %r25
@ -76,11 +78,21 @@
PUSHAX %erbta
.endm
.macro SAVE_EXCEPTION_SOURCE
#ifdef CONFIG_MMU
/* If MMU exists exception faulting address is loaded in EFA reg */
lr %r0, [%efa]
#else
/* Otherwise in ERET (exception return) reg */
lr %r0, [%eret]
#endif
.endm
.section .ivt, "ax",@progbits
.align 4
.globl _start
_start:
_ivt:
/* Critical system events */
j reset /* 0 - 0x000 */
j _start /* 0 - 0x000 */
j memory_error /* 1 - 0x008 */
j instruction_error /* 2 - 0x010 */
@ -98,15 +110,37 @@ _start:
j EV_Trap /* 0x128, Trap exception (0x25) */
j EV_Extension /* 0x130, Extn Intruction Excp (0x26) */
.text
.globl _start
_start:
/* Setup interrupt vector base that matches "__text_start" */
sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
/* Setup stack pointer */
mov %sp, CONFIG_SYS_INIT_SP_ADDR
mov %fp, %sp
/* Clear bss */
mov %r0, __bss_start
mov %r1, __bss_end
clear_bss:
st.ab 0, [%r0, 4]
brlt %r0, %r1, clear_bss
/* Zero the one and only argument of "board_init_f" */
mov_s %r0, 0
j board_init_f
memory_error:
SAVE_ALL_SYS
lr %r0, [%efa]
SAVE_EXCEPTION_SOURCE
mov %r1, %sp
j do_memory_error
instruction_error:
SAVE_ALL_SYS
lr %r0, [%efa]
SAVE_EXCEPTION_SOURCE
mov %r1, %sp
j do_instruction_error
@ -117,7 +151,7 @@ interrupt_handler:
EV_MachineCheck:
SAVE_ALL_SYS
lr %r0, [%efa]
SAVE_EXCEPTION_SOURCE
mov %r1, %sp
j do_machine_check_fault
@ -133,7 +167,7 @@ EV_TLBMissD:
EV_TLBProtV:
SAVE_ALL_SYS
lr %r0, [%efa]
SAVE_EXCEPTION_SOURCE
mov %r1, %sp
j do_tlb_prot_violation
@ -152,27 +186,6 @@ EV_Extension:
mov %r0, %sp
j do_extension
reset:
/* Setup interrupt vector base that matches "__text_start" */
sr __text_start, [ARC_AUX_INTR_VEC_BASE]
/* Setup stack pointer */
mov %sp, CONFIG_SYS_INIT_SP_ADDR
mov %fp, %sp
/* Clear bss */
mov %r0, __bss_start
mov %r1, __bss_end
clear_bss:
st.ab 0, [%r0, 4]
brlt %r0, %r1, clear_bss
/* Zero the one and only argument of "board_init_f" */
mov_s %r0, 0
j board_init_f
/*
* void relocate_code (addr_sp, gd, addr_moni)
*

15
arch/arc/cpu/arc700/u-boot.lds → arch/arc/cpu/u-boot.lds
View File

@ -13,7 +13,6 @@ SECTIONS
.text : {
*(.__text_start)
*(.__image_copy_start)
CPUDIR/start.o (.text*)
*(.text*)
}
@ -23,6 +22,20 @@ SECTIONS
*(.__text_end)
}
. = ALIGN(1024);
.ivt_start : {
*(.__ivt_start)
}
.ivt :
{
*(.ivt)
}
.ivt_end : {
*(.__ivt_end)
}
. = ALIGN(4);
.rodata : {
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))

8
arch/arc/include/asm/arcregs.h
View File

@ -7,6 +7,8 @@
#ifndef _ASM_ARC_ARCREGS_H
#define _ASM_ARC_ARCREGS_H
#include <asm/cache.h>
/*
* ARC architecture has additional address space - auxiliary registers.
* These registers are mostly used for configuration purposes.
@ -21,9 +23,10 @@
#define ARC_AUX_IC_IVIC 0x10
#define ARC_AUX_IC_CTRL 0x11
#define ARC_AUX_IC_IVIL 0x19
#if (CONFIG_ARC_MMU_VER > 2)
#if (CONFIG_ARC_MMU_VER == 3)
#define ARC_AUX_IC_PTAG 0x1E
#endif
#define ARC_BCR_IC_BUILD 0x77
/* Timer related auxiliary registers */
#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
@ -39,9 +42,10 @@
#define ARC_AUX_DC_IVDL 0x4A
#define ARC_AUX_DC_FLSH 0x4B
#define ARC_AUX_DC_FLDL 0x4C
#if (CONFIG_ARC_MMU_VER > 2)
#if (CONFIG_ARC_MMU_VER == 3)
#define ARC_AUX_DC_PTAG 0x5C
#endif
#define ARC_BCR_DC_BUILD 0x72
#ifndef __ASSEMBLY__
/* Accessors for auxiliary registers */

19
arch/arc/include/asm/cache.h
View File

@ -9,15 +9,18 @@
#include <config.h>
/*
* The current upper bound for ARC L1 data cache line sizes is 128 bytes.
* We use that value for aligning DMA buffers unless the board config has
* specified an alternate cache line size.
*/
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#ifdef CONFIG_ARC_CACHE_LINE_SHIFT
#define CONFIG_SYS_CACHELINE_SIZE (1 << CONFIG_ARC_CACHE_LINE_SHIFT)
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN 128
/* Satisfy users of ARCH_DMA_MINALIGN */
#define ARCH_DMA_MINALIGN 128
#endif
#if defined(CONFIG_ARC_MMU_V2)
#define CONFIG_ARC_MMU_VER 2
#elif defined(CONFIG_ARC_MMU_V3)
#define CONFIG_ARC_MMU_VER 3
#endif
#endif /* __ASM_ARC_CACHE_H */

2
arch/arc/include/asm/config.h
View File

@ -7,8 +7,10 @@
#ifndef __ASM_ARC_CONFIG_H_
#define __ASM_ARC_CONFIG_H_
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_LMB

3
arch/arc/include/asm/sections.h
View File

@ -10,5 +10,8 @@
#include <asm-generic/sections.h>
extern ulong __text_end;
extern ulong __ivt_start;
extern ulong __ivt_end;
extern ulong __image_copy_start;
#endif /* __ASM_ARC_SECTIONS_H */

8
arch/arc/lib/Makefile
View File

@ -4,6 +4,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += cache.o
obj-y += cpu.o
obj-y += interrupts.o
obj-y += sections.o
obj-y += relocate.o
obj-y += strchr-700.o
@ -13,4 +16,9 @@ obj-y += strlen.o
obj-y += memcmp.o
obj-y += memcpy-700.o
obj-y += memset.o
obj-y += reset.o
obj-y += timer.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _millicodethunk.o libgcc2.o

226
arch/arc/lib/_millicodethunk.S Normal file
View File

@ -0,0 +1,226 @@
/*
* Copyright (C) 1995, 1997, 2007-2013 Free Software Foundation, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* ANSI concatenation macros. */
#define CONCAT1(a, b) CONCAT2(a, b)
#define CONCAT2(a, b) a ## b
/* Use the right prefix for global labels. */
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
#ifndef WORKING_ASSEMBLER
#define abs_l abs
#define asl_l asl
#define mov_l mov
#endif
#define FUNC(X) .type SYM(X),@function
#define HIDDEN_FUNC(X) FUNC(X)` .hidden X
#define ENDFUNC0(X) .Lfe_##X: .size X,.Lfe_##X-X
#define ENDFUNC(X) ENDFUNC0(X)
.section .text
.align 4
.global SYM(__st_r13_to_r15)
.global SYM(__st_r13_to_r16)
.global SYM(__st_r13_to_r17)
.global SYM(__st_r13_to_r18)
.global SYM(__st_r13_to_r19)
.global SYM(__st_r13_to_r20)
.global SYM(__st_r13_to_r21)
.global SYM(__st_r13_to_r22)
.global SYM(__st_r13_to_r23)
.global SYM(__st_r13_to_r24)
.global SYM(__st_r13_to_r25)
HIDDEN_FUNC(__st_r13_to_r15)
HIDDEN_FUNC(__st_r13_to_r16)
HIDDEN_FUNC(__st_r13_to_r17)
HIDDEN_FUNC(__st_r13_to_r18)
HIDDEN_FUNC(__st_r13_to_r19)
HIDDEN_FUNC(__st_r13_to_r20)
HIDDEN_FUNC(__st_r13_to_r21)
HIDDEN_FUNC(__st_r13_to_r22)
HIDDEN_FUNC(__st_r13_to_r23)
HIDDEN_FUNC(__st_r13_to_r24)
HIDDEN_FUNC(__st_r13_to_r25)
.align 4
SYM(__st_r13_to_r25):
st r25, [sp,48]
SYM(__st_r13_to_r24):
st r24, [sp,44]
SYM(__st_r13_to_r23):
st r23, [sp,40]
SYM(__st_r13_to_r22):
st r22, [sp,36]
SYM(__st_r13_to_r21):
st r21, [sp,32]
SYM(__st_r13_to_r20):
st r20, [sp,28]
SYM(__st_r13_to_r19):
st r19, [sp,24]
SYM(__st_r13_to_r18):
st r18, [sp,20]
SYM(__st_r13_to_r17):
st r17, [sp,16]
SYM(__st_r13_to_r16):
st r16, [sp,12]
SYM(__st_r13_to_r15):
#ifdef __ARC700__
st r15, [sp,8] ; minimum function size to avoid stall: 6 bytes.
#else
st_s r15, [sp,8]
#endif
st_s r14, [sp,4]
j_s.d [%blink]
st_s r13, [sp,0]
ENDFUNC(__st_r13_to_r15)
ENDFUNC(__st_r13_to_r16)
ENDFUNC(__st_r13_to_r17)
ENDFUNC(__st_r13_to_r18)
ENDFUNC(__st_r13_to_r19)
ENDFUNC(__st_r13_to_r20)
ENDFUNC(__st_r13_to_r21)
ENDFUNC(__st_r13_to_r22)
ENDFUNC(__st_r13_to_r23)
ENDFUNC(__st_r13_to_r24)
ENDFUNC(__st_r13_to_r25)
.section .text
.align 4
; ==================================
; the loads
.global SYM(__ld_r13_to_r15)
.global SYM(__ld_r13_to_r16)
.global SYM(__ld_r13_to_r17)
.global SYM(__ld_r13_to_r18)
.global SYM(__ld_r13_to_r19)
.global SYM(__ld_r13_to_r20)
.global SYM(__ld_r13_to_r21)
.global SYM(__ld_r13_to_r22)
.global SYM(__ld_r13_to_r23)
.global SYM(__ld_r13_to_r24)
.global SYM(__ld_r13_to_r25)
HIDDEN_FUNC(__ld_r13_to_r15)
HIDDEN_FUNC(__ld_r13_to_r16)
HIDDEN_FUNC(__ld_r13_to_r17)
HIDDEN_FUNC(__ld_r13_to_r18)
HIDDEN_FUNC(__ld_r13_to_r19)
HIDDEN_FUNC(__ld_r13_to_r20)
HIDDEN_FUNC(__ld_r13_to_r21)
HIDDEN_FUNC(__ld_r13_to_r22)
HIDDEN_FUNC(__ld_r13_to_r23)
HIDDEN_FUNC(__ld_r13_to_r24)
HIDDEN_FUNC(__ld_r13_to_r25)
SYM(__ld_r13_to_r25):
ld r25, [sp,48]
SYM(__ld_r13_to_r24):
ld r24, [sp,44]
SYM(__ld_r13_to_r23):
ld r23, [sp,40]
SYM(__ld_r13_to_r22):
ld r22, [sp,36]
SYM(__ld_r13_to_r21):
ld r21, [sp,32]
SYM(__ld_r13_to_r20):
ld r20, [sp,28]
SYM(__ld_r13_to_r19):
ld r19, [sp,24]
SYM(__ld_r13_to_r18):
ld r18, [sp,20]
SYM(__ld_r13_to_r17):
ld r17, [sp,16]
SYM(__ld_r13_to_r16):
ld r16, [sp,12]
SYM(__ld_r13_to_r15):
#ifdef __ARC700__
ld r15, [sp,8] ; minimum function size to avoid stall: 6 bytes.
#else
ld_s r15, [sp,8]
#endif
ld_s r14, [sp,4]
j_s.d [%blink]
ld_s r13, [sp,0]
ENDFUNC(__ld_r13_to_r15)
ENDFUNC(__ld_r13_to_r16)
ENDFUNC(__ld_r13_to_r17)
ENDFUNC(__ld_r13_to_r18)
ENDFUNC(__ld_r13_to_r19)
ENDFUNC(__ld_r13_to_r20)
ENDFUNC(__ld_r13_to_r21)
ENDFUNC(__ld_r13_to_r22)
ENDFUNC(__ld_r13_to_r23)
ENDFUNC(__ld_r13_to_r24)
ENDFUNC(__ld_r13_to_r25)
.global SYM(__ld_r13_to_r14_ret)
.global SYM(__ld_r13_to_r15_ret)
.global SYM(__ld_r13_to_r16_ret)
.global SYM(__ld_r13_to_r17_ret)
.global SYM(__ld_r13_to_r18_ret)
.global SYM(__ld_r13_to_r19_ret)
.global SYM(__ld_r13_to_r20_ret)
.global SYM(__ld_r13_to_r21_ret)
.global SYM(__ld_r13_to_r22_ret)
.global SYM(__ld_r13_to_r23_ret)
.global SYM(__ld_r13_to_r24_ret)
.global SYM(__ld_r13_to_r25_ret)
HIDDEN_FUNC(__ld_r13_to_r14_ret)
HIDDEN_FUNC(__ld_r13_to_r15_ret)
HIDDEN_FUNC(__ld_r13_to_r16_ret)
HIDDEN_FUNC(__ld_r13_to_r17_ret)
HIDDEN_FUNC(__ld_r13_to_r18_ret)
HIDDEN_FUNC(__ld_r13_to_r19_ret)
HIDDEN_FUNC(__ld_r13_to_r20_ret)
HIDDEN_FUNC(__ld_r13_to_r21_ret)
HIDDEN_FUNC(__ld_r13_to_r22_ret)
HIDDEN_FUNC(__ld_r13_to_r23_ret)
HIDDEN_FUNC(__ld_r13_to_r24_ret)
HIDDEN_FUNC(__ld_r13_to_r25_ret)
.section .text
.align 4
SYM(__ld_r13_to_r25_ret):
ld r25, [sp,48]
SYM(__ld_r13_to_r24_ret):
ld r24, [sp,44]
SYM(__ld_r13_to_r23_ret):
ld r23, [sp,40]
SYM(__ld_r13_to_r22_ret):
ld r22, [sp,36]
SYM(__ld_r13_to_r21_ret):
ld r21, [sp,32]
SYM(__ld_r13_to_r20_ret):
ld r20, [sp,28]
SYM(__ld_r13_to_r19_ret):
ld r19, [sp,24]
SYM(__ld_r13_to_r18_ret):
ld r18, [sp,20]
SYM(__ld_r13_to_r17_ret):
ld r17, [sp,16]
SYM(__ld_r13_to_r16_ret):
ld r16, [sp,12]
SYM(__ld_r13_to_r15_ret):
ld r15, [sp,8]
SYM(__ld_r13_to_r14_ret):
ld blink,[sp,r12]
ld_s r14, [sp,4]
ld.ab r13, [sp,r12]
j_s.d [%blink]
add_s sp,sp,4
ENDFUNC(__ld_r13_to_r14_ret)
ENDFUNC(__ld_r13_to_r15_ret)
ENDFUNC(__ld_r13_to_r16_ret)
ENDFUNC(__ld_r13_to_r17_ret)
ENDFUNC(__ld_r13_to_r18_ret)
ENDFUNC(__ld_r13_to_r19_ret)
ENDFUNC(__ld_r13_to_r20_ret)
ENDFUNC(__ld_r13_to_r21_ret)
ENDFUNC(__ld_r13_to_r22_ret)
ENDFUNC(__ld_r13_to_r23_ret)
ENDFUNC(__ld_r13_to_r24_ret)
ENDFUNC(__ld_r13_to_r25_ret)

36
arch/arc/cpu/arc700/cache.c → arch/arc/lib/cache.c
View File

@ -6,6 +6,7 @@
#include <config.h>
#include <asm/arcregs.h>
#include <asm/cache.h>
/* Bit values in IC_CTRL */
#define IC_CTRL_CACHE_DISABLE (1 << 0)
@ -14,21 +15,34 @@
#define DC_CTRL_CACHE_DISABLE (1 << 0)
#define DC_CTRL_INV_MODE_FLUSH (1 << 6)
#define DC_CTRL_FLUSH_STATUS (1 << 8)
#define CACHE_VER_NUM_MASK 0xF
int icache_status(void)
{
/* If no cache in CPU exit immediately */
if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
return 0;
return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
IC_CTRL_CACHE_DISABLE;
}
void icache_enable(void)
{
/* If no cache in CPU exit immediately */
if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
return;
write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
~IC_CTRL_CACHE_DISABLE);
}
void icache_disable(void)
{
/* If no cache in CPU exit immediately */
if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
return;
write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
IC_CTRL_CACHE_DISABLE);
}
@ -43,24 +57,40 @@ void invalidate_icache_all(void)
int dcache_status(void)
{
/* If no cache in CPU exit immediately */
if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
return 0;
return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
DC_CTRL_CACHE_DISABLE;
}
void dcache_enable(void)
{
/* If no cache in CPU exit immediately */
if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
return;
write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
}
void dcache_disable(void)
{
/* If no cache in CPU exit immediately */
if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
return;
write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
DC_CTRL_CACHE_DISABLE);
}
void flush_dcache_all(void)
{
/* If no cache in CPU exit immediately */
if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
return;
/* Do flush of entire cache */
write_aux_reg(ARC_AUX_DC_FLSH, 1);
@ -72,7 +102,7 @@ void flush_dcache_all(void)
#ifndef CONFIG_SYS_DCACHE_OFF
static void dcache_flush_line(unsigned addr)
{
#if (CONFIG_ARC_MMU_VER > 2)
#if (CONFIG_ARC_MMU_VER == 3)
write_aux_reg(ARC_AUX_DC_PTAG, addr);
#endif
write_aux_reg(ARC_AUX_DC_FLDL, addr);
@ -86,7 +116,7 @@ static void dcache_flush_line(unsigned addr)
* Invalidate I$ for addresses range just flushed from D$.
* If we try to execute data flushed above it will be valid/correct
*/
#if (CONFIG_ARC_MMU_VER > 2)
#if (CONFIG_ARC_MMU_VER == 3)
write_aux_reg(ARC_AUX_IC_PTAG, addr);
#endif
write_aux_reg(ARC_AUX_IC_IVIL, addr);
@ -116,7 +146,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
#if (CONFIG_ARC_MMU_VER > 2)
#if (CONFIG_ARC_MMU_VER == 3)
write_aux_reg(ARC_AUX_DC_PTAG, addr);
#endif
write_aux_reg(ARC_AUX_DC_IVDL, addr);

0
arch/arc/cpu/arc700/cpu.c → arch/arc/lib/cpu.c
View File

3
arch/arc/cpu/arc700/interrupts.c → arch/arc/lib/interrupts.c
View File

@ -23,7 +23,7 @@ int interrupt_init(void)
int disable_interrupts(void)
{
int status = read_aux_reg(ARC_AUX_STATUS32);
int state = (status | E1_MASK | E2_MASK) ? 1 : 0;
int state = (status & (E1_MASK | E2_MASK)) ? 1 : 0;
status &= ~(E1_MASK | E2_MASK);
/* STATUS32 register is updated indirectly with "FLAG" instruction */
@ -61,6 +61,7 @@ static void print_reg_file(long *reg_rev, int start_num)
void show_regs(struct pt_regs *regs)
{
printf("ECR:\t0x%08lx\n", regs->ecr);
printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n",
regs->ret, regs->blink, regs->status32);
printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25);

161
arch/arc/lib/libgcc2.c Normal file
View File

@ -0,0 +1,161 @@
/*
* Copyright (C) 1989-2013 Free Software Foundation, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "libgcc2.h"
DWtype
__ashldi3(DWtype u, shift_count_type b)
{
if (b == 0)
return u;
const DWunion uu = {.ll = u};
const shift_count_type bm = W_TYPE_SIZE - b;
DWunion w;
if (bm <= 0) {
w.s.low = 0;
w.s.high = (UWtype)uu.s.low << -bm;
} else {
const UWtype carries = (UWtype) uu.s.low >> bm;
w.s.low = (UWtype)uu.s.low << b;
w.s.high = ((UWtype)uu.s.high << b) | carries;
}
return w.ll;
}
DWtype
__ashrdi3(DWtype u, shift_count_type b)
{
if (b == 0)
return u;
const DWunion uu = {.ll = u};
const shift_count_type bm = W_TYPE_SIZE - b;
DWunion w;
if (bm <= 0) {
/* w.s.high = 1..1 or 0..0 */
w.s.high = uu.s.high >> (W_TYPE_SIZE - 1);
w.s.low = uu.s.high >> -bm;
} else {
const UWtype carries = (UWtype) uu.s.high << bm;
w.s.high = uu.s.high >> b;
w.s.low = ((UWtype)uu.s.low >> b) | carries;
}
return w.ll;
}
DWtype
__lshrdi3(DWtype u, shift_count_type b)
{
if (b == 0)
return u;
const DWunion uu = {.ll = u};
const shift_count_type bm = W_TYPE_SIZE - b;
DWunion w;
if (bm <= 0) {
w.s.high = 0;
w.s.low = (UWtype)uu.s.high >> -bm;
} else {
const UWtype carries = (UWtype)uu.s.high << bm;
w.s.high = (UWtype)uu.s.high >> b;
w.s.low = ((UWtype)uu.s.low >> b) | carries;
}
return w.ll;
}
unsigned long
udivmodsi4(unsigned long num, unsigned long den, int modwanted)
{
unsigned long bit = 1;
unsigned long res = 0;
while (den < num && bit && !(den & (1L<<31))) {
den <<= 1;
bit <<= 1;
}
while (bit) {
if (num >= den) {
num -= den;
res |= bit;
}
bit >>= 1;
den >>= 1;
}
if (modwanted)
return num;
return res;
}
long
__divsi3(long a, long b)
{
int neg = 0;
long res;
if (a < 0) {
a = -a;
neg = !neg;
}
if (b < 0) {
b = -b;
neg = !neg;
}
res = udivmodsi4(a, b, 0);
if (neg)
res = -res;
return res;
}
long
__modsi3(long a, long b)
{
int neg = 0;
long res;
if (a < 0) {
a = -a;
neg = 1;
}
if (b < 0)
b = -b;
res = udivmodsi4(a, b, 1);
if (neg)
res = -res;
return res;
}
long
__udivsi3(long a, long b)
{
return udivmodsi4(a, b, 0);
}
long
__umodsi3(long a, long b)
{
return udivmodsi4(a, b, 1);
}

132
arch/arc/lib/libgcc2.h Normal file
View File

@ -0,0 +1,132 @@
/*
* Copyright (C) 1989-2013 Free Software Foundation, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_LIBGCC_H
#define __ASM_LIBGCC_H
#define UNITS_PER_WORD 4 /* for ARC */
#define BITS_PER_UNIT 8 /* for ARC */
#define W_TYPE_SIZE (4 * BITS_PER_UNIT)
#define MIN_UNITS_PER_WORD UNITS_PER_WORD
/* Work out the largest "word" size that we can deal with on this target. */
#if MIN_UNITS_PER_WORD > 4
# define LIBGCC2_MAX_UNITS_PER_WORD 8
#elif (MIN_UNITS_PER_WORD > 2 \
|| (MIN_UNITS_PER_WORD > 1 && __SIZEOF_LONG_LONG__ > 4))
# define LIBGCC2_MAX_UNITS_PER_WORD 4
#else
# define LIBGCC2_MAX_UNITS_PER_WORD MIN_UNITS_PER_WORD
#endif
/* Work out what word size we are using for this compilation.
The value can be set on the command line. */
#ifndef LIBGCC2_UNITS_PER_WORD
#define LIBGCC2_UNITS_PER_WORD LIBGCC2_MAX_UNITS_PER_WORD
#endif
typedef int QItype __attribute__ ((mode (QI)));
typedef unsigned int UQItype __attribute__ ((mode (QI)));
typedef int HItype __attribute__ ((mode (HI)));
typedef unsigned int UHItype __attribute__ ((mode (HI)));
#if MIN_UNITS_PER_WORD > 1
/* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1. */
typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
#if __SIZEOF_LONG_LONG__ > 4
/* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2. */
typedef int DItype __attribute__ ((mode (DI)));
typedef unsigned int UDItype __attribute__ ((mode (DI)));
#if MIN_UNITS_PER_WORD > 4
/* These typedefs are usually forbidden on archs with UNITS_PER_WORD 4. */
typedef int TItype __attribute__ ((mode (TI)));
typedef unsigned int UTItype __attribute__ ((mode (TI)));
#endif
#endif
#endif
#if LIBGCC2_UNITS_PER_WORD == 8
#define W_TYPE_SIZE (8 * BITS_PER_UNIT)
#define Wtype DItype
#define UWtype UDItype
#define HWtype DItype
#define UHWtype UDItype
#define DWtype TItype
#define UDWtype UTItype
#ifdef LIBGCC2_GNU_PREFIX
#define __NW(a,b) __gnu_ ## a ## di ## b
#define __NDW(a,b) __gnu_ ## a ## ti ## b
#else
#define __NW(a,b) __ ## a ## di ## b
#define __NDW(a,b) __ ## a ## ti ## b
#endif
#elif LIBGCC2_UNITS_PER_WORD == 4
#define W_TYPE_SIZE (4 * BITS_PER_UNIT)
#define Wtype SItype
#define UWtype USItype
#define HWtype SItype
#define UHWtype USItype
#define DWtype DItype
#define UDWtype UDItype
#ifdef LIBGCC2_GNU_PREFIX
#define __NW(a,b) __gnu_ ## a ## si ## b
#define __NDW(a,b) __gnu_ ## a ## di ## b
#else
#define __NW(a,b) __ ## a ## si ## b
#define __NDW(a,b) __ ## a ## di ## b
#endif
#elif LIBGCC2_UNITS_PER_WORD == 2
#define W_TYPE_SIZE (2 * BITS_PER_UNIT)
#define Wtype HItype
#define UWtype UHItype
#define HWtype HItype
#define UHWtype UHItype
#define DWtype SItype
#define UDWtype USItype
#ifdef LIBGCC2_GNU_PREFIX
#define __NW(a,b) __gnu_ ## a ## hi ## b
#define __NDW(a,b) __gnu_ ## a ## si ## b
#else
#define __NW(a,b) __ ## a ## hi ## b
#define __NDW(a,b) __ ## a ## si ## b
#endif
#else
#define W_TYPE_SIZE BITS_PER_UNIT
#define Wtype QItype
#define UWtype UQItype
#define HWtype QItype
#define UHWtype UQItype
#define DWtype HItype
#define UDWtype UHItype
#ifdef LIBGCC2_GNU_PREFIX
#define __NW(a,b) __gnu_ ## a ## qi ## b
#define __NDW(a,b) __gnu_ ## a ## hi ## b
#else
#define __NW(a,b) __ ## a ## qi ## b
#define __NDW(a,b) __ ## a ## hi ## b
#endif
#endif
typedef int shift_count_type __attribute__((mode (__libgcc_shift_count__)));
#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
struct DWstruct {Wtype high, low;};
#else
struct DWstruct {Wtype low, high;};
#endif
/* We need this union to unpack/pack DImode values, since we don't have
any arithmetic yet. Incoming DImode parameters are stored into the
`ll' field, and the unpacked result is read from the struct `s'. */
typedef union {
struct DWstruct s;
DWtype ll;
} DWunion;
#endif /* __ASM_LIBGCC_H */

2
arch/arc/lib/memcmp.S
View File

@ -29,6 +29,7 @@ memcmp:
ld.a %r4, [%r0, 8]
ld.a %r5, [%r1, 8]
brne WORD2, %r12, .Lodd
nop
.Loop_end:
asl_s SHIFT, SHIFT, 3
bhs_s .Last_cmp
@ -105,6 +106,7 @@ memcmp:
ldb.a %r4, [%r0, 2]
ldb.a %r5, [%r1, 2]
brne %r3, %r12, .Lbyte_odd
nop
.Lbyte_end:
bcc .Lbyte_even
brne %r4, %r5, .Lbyte_even

19
arch/arc/lib/relocate.c
View File

@ -26,7 +26,7 @@ int do_elf_reloc_fixups(void)
offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
/* Check that the location of the relocation is in .text */
if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE &&
if (offset_ptr_rom >= (Elf32_Addr *)&__image_copy_start &&
offset_ptr_rom > last_offset) {
unsigned int val;
/* Switch to the in-RAM version */
@ -44,29 +44,22 @@ int do_elf_reloc_fixups(void)
#ifdef __LITTLE_ENDIAN__
/* If location in ".text" section swap value */
if ((unsigned int)offset_ptr_rom <
(unsigned int)&__text_end)
(unsigned int)&__ivt_end)
val = (val << 16) | (val >> 16);
#endif
/* Check that the target points into .text */
if (val >= CONFIG_SYS_TEXT_BASE && val <=
(unsigned int)&__bss_end) {
/* Check that the target points into executable */
if (val >= (unsigned int)&__image_copy_start && val <=
(unsigned int)&__image_copy_end) {
val += gd->reloc_off;
#ifdef __LITTLE_ENDIAN__
/* If location in ".text" section swap value */
if ((unsigned int)offset_ptr_rom <
(unsigned int)&__text_end)
(unsigned int)&__ivt_end)
val = (val << 16) | (val >> 16);
#endif
memcpy(offset_ptr_ram, &val, sizeof(int));
} else {
debug(" %p: rom reloc %x, ram %p, value %x, limit %x\n",
re_src, re_src->r_offset, offset_ptr_ram,
val, (unsigned int)&__bss_end);
}
} else {
debug(" %p: rom reloc %x, last %p\n", re_src,
re_src->r_offset, last_offset);
}
last_offset = offset_ptr_rom;

0
arch/arc/cpu/arc700/reset.c → arch/arc/lib/reset.c
View File

2
arch/arc/lib/sections.c
View File

@ -19,3 +19,5 @@ char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
char __text_start[0] __attribute__((section(".__text_start")));
char __text_end[0] __attribute__((section(".__text_end")));
char __init_end[0] __attribute__((section(".__init_end")));
char __ivt_start[0] __attribute__((section(".__ivt_start")));
char __ivt_end[0] __attribute__((section(".__ivt_end")));

0
arch/arc/cpu/arc700/timer.c → arch/arc/lib/timer.c
View File

22
arch/arm/Kconfig
View File

@ -51,6 +51,13 @@ config SYS_CPU
default "sa1100" if CPU_SA1100
default "armv8" if ARM64
config SEMIHOSTING
bool "support boot from semihosting"
help
In emulated environments, semihosting is a way for
the hosted environment to call out to the emulator to
retrieve files from the host machine.
choice
prompt "Target select"
@ -229,10 +236,12 @@ config KIRKWOOD
config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
select CPU_V7
select SUPPORT_SPL
config TARGET_MAXBCM
bool "Support maxbcm"
select CPU_V7
select SUPPORT_SPL
config TARGET_DEVKIT3250
bool "Support devkit3250"
@ -518,10 +527,12 @@ config TARGET_SAMA5D3XEK
config TARGET_SAMA5D4_XPLAINED
bool "Support sama5d4_xplained"
select CPU_V7
select SUPPORT_SPL
config TARGET_SAMA5D4EK
bool "Support sama5d4ek"
select CPU_V7
select SUPPORT_SPL
config TARGET_BCM28155_AP
bool "Support bcm28155_ap"
@ -732,10 +743,19 @@ config TEGRA
select CPU_ARM720T if SPL_BUILD
select CPU_V7 if !SPL_BUILD
config TARGET_VEXPRESS_AEMV8A
config TARGET_VEXPRESS64_AEMV8A
bool "Support vexpress_aemv8a"
select ARM64
config TARGET_VEXPRESS64_BASE_FVP
bool "Support Versatile Express ARMv8a FVP BASE model"
select ARM64
select SEMIHOSTING
config TARGET_VEXPRESS64_JUNO
bool "Support Versatile Express Juno Development Platform"
select ARM64
config TARGET_LS2085A_EMU
bool "Support ls2085a_emu"
select ARM64

1
arch/arm/cpu/arm926ejs/at91/Makefile
View File

@ -5,7 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_AT91CAP9) += at91cap9_devices.o
obj-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o
obj-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o
obj-$(CONFIG_AT91SAM9XE) += at91sam9260_devices.o

189
arch/arm/cpu/arm926ejs/at91/at91cap9_devices.c
View File

@ -1,189 +0,0 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2009
* Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
* esd electronic system design gmbh <www.esd.eu>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
void at91_serial0_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* RXD0 */
writel(1 << AT91CAP9_ID_US0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */
writel(1 << AT91CAP9_ID_US1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */
writel(1 << AT91CAP9_ID_US2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */
writel(1 << AT91_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
{
#ifdef CONFIG_USART0
at91_serial0_hw_init();
#endif
#ifdef CONFIG_USART1
at91_serial1_hw_init();
#endif
#ifdef CONFIG_USART2
at91_serial2_hw_init();
#endif
#ifdef CONFIG_USART3 /* DBGU */
at91_serial3_hw_init();
#endif
}
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */
at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */
at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */
/* Enable clock */
writel(1 << AT91CAP9_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_b_periph(AT91_PIO_PORTD, 0, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_b_periph(AT91_PIO_PORTD, 1, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_pio_output(AT91_PIO_PORTD, 0, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_pio_output(AT91_PIO_PORTD, 1, 1);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */
/* Enable clock */
writel(1 << AT91CAP9_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
}
}
#endif
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
at91_set_a_periph(AT91_PIO_PORTB, 21, 0); /* ETXCK_EREFCK */
at91_set_a_periph(AT91_PIO_PORTB, 22, 0); /* ERXDV */
at91_set_a_periph(AT91_PIO_PORTB, 25, 0); /* ERX0 */
at91_set_a_periph(AT91_PIO_PORTB, 26, 0); /* ERX1 */
at91_set_a_periph(AT91_PIO_PORTB, 27, 0); /* ERXER */
at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* ETXEN */
at91_set_a_periph(AT91_PIO_PORTB, 23, 0); /* ETX0 */
at91_set_a_periph(AT91_PIO_PORTB, 24, 0); /* ETX1 */
at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* EMDIO */
at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* EMDC */
#ifndef CONFIG_RMII
at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ECRS */
at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */
at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */
at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */
at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */
at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */
at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */
at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */
#endif
}
#endif
#ifdef CONFIG_AT91_CAN
void at91_can_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* CAN_TX */
at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* CAN_RX */
/* Enable clock */
writel(1 << AT91CAP9_ID_CAN, &pmc->pcer);
}
#endif

2
arch/arm/cpu/arm926ejs/cpu.c
View File

@ -45,7 +45,9 @@ int cleanup_before_linux (void)
/* flush I/D-cache */
static void cache_flush (void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
#endif
}

17
arch/arm/cpu/arm926ejs/davinci/spl.c
View File

@ -34,29 +34,14 @@ void putc(char c)
}
#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
void board_init_f(ulong dummy)
void spl_board_init(void)
{
/* First, setup our stack pointer. */
asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
/* Second, perform our low-level init. */
#ifdef CONFIG_SOC_DM365
dm36x_lowlevel_init(0);
#endif
#ifdef CONFIG_SOC_DA8XX
arch_cpu_init();
#endif
/* Third, we clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* Finally, setup gd and move to the next step. */
gd = &gdata;
board_init_r(NULL, 0);
}
void spl_board_init(void)
{
preloader_console_init();
}

11
arch/arm/cpu/arm926ejs/kirkwood/cpu.c
View File

@ -181,7 +181,7 @@ static void kw_sysrst_check(void)
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
char *rev;
char *rev = "??";
u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
@ -192,7 +192,13 @@ int print_cpuinfo(void)
switch (revid) {
case 0:
rev = "Z0";
if (devid == 0x6281)
rev = "Z0";
else if (devid == 0x6282)
rev = "A0";
break;
case 1:
rev = "A1";
break;
case 2:
rev = "A0";
@ -201,7 +207,6 @@ int print_cpuinfo(void)
rev = "A1";
break;
default:
rev = "??";
break;
}

11
arch/arm/cpu/armv7/am33xx/board.c
View File

@ -284,14 +284,6 @@ void s_init(void)
*/
#ifdef CONFIG_NOR_BOOT
enable_norboot_pin_mux();
#endif
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
* to prevent overwrites.
*/
#ifdef CONFIG_SPL_BUILD
save_omap_boot_params();
#endif
watchdog_disable();
set_uart_mux_conf();
@ -301,9 +293,6 @@ void s_init(void)
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
#elif defined(CONFIG_SPL_BUILD)
gd = &gdata;
preloader_console_init();
#endif
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
/* Enable RTC32K clock */

2
arch/arm/cpu/armv7/armada-xp/Makefile
View File

@ -5,3 +5,5 @@
#
obj-y = cpu.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o

62
arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S Normal file
View File

@ -0,0 +1,62 @@
/*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <version.h>
#include <linux/linkage.h>
ENTRY(save_boot_params)
bx lr
ENDPROC(save_boot_params)
/*
* cache_inv - invalidate Cache line
* r0 - dest
*/
.global cache_inv
.type cache_inv, %function
cache_inv:
stmfd sp!, {r1-r12}
mcr p15, 0, r0, c7, c6, 1
ldmfd sp!, {r1-r12}
bx lr
/*
* flush_l1_v6 - l1 cache clean invalidate
* r0 - dest
*/
.global flush_l1_v6
.type flush_l1_v6, %function
flush_l1_v6:
stmfd sp!, {r1-r12}
mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
ldmfd sp!, {r1-r12}
bx lr
/*
* flush_l1_v7 - l1 cache clean invalidate
* r0 - dest
*/
.global flush_l1_v7
.type flush_l1_v7, %function
flush_l1_v7:
stmfd sp!, {r1-r12}
dmb /* @data memory barrier */
mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
dsb /* @data sync barrier */
ldmfd sp!, {r1-r12}
bx lr

38
arch/arm/cpu/armv7/armada-xp/spl.c Normal file
View File

@ -0,0 +1,38 @@
/*
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
DECLARE_GLOBAL_DATA_PTR;
u32 spl_boot_device(void)
{
/* Right now only booting via SPI NOR flash is supported */
return BOOT_DEVICE_SPI;
}
void board_init_f(ulong dummy)
{
/* Set global data pointer */
gd = &gdata;
/* Linux expects the internal registers to be at 0xf1000000 */
arch_cpu_init();
preloader_console_init();
/* First init the serdes PHY's */
serdes_phy_config();
/* Setup DDR */
ddr3_init();
board_init_r(NULL, 0);
}

8
arch/arm/cpu/armv7/at91/clock.c
View File

@ -130,10 +130,18 @@ void at91_mck_init(u32 mckr)
AT91_PMC_MCKR_PRES_MASK |
AT91_PMC_MCKR_MDIV_MASK |
AT91_PMC_MCKR_PLLADIV_2);
#ifdef CPU_HAS_H32MXDIV
tmp &= ~AT91_PMC_MCKR_H32MXDIV;
#endif
tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK |
AT91_PMC_MCKR_PRES_MASK |
AT91_PMC_MCKR_MDIV_MASK |
AT91_PMC_MCKR_PLLADIV_2);
#ifdef CPU_HAS_H32MXDIV
tmp |= mckr & AT91_PMC_MCKR_H32MXDIV;
#endif
writel(tmp, &pmc->mckr);
while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))

63
arch/arm/cpu/armv7/at91/sama5d4_devices.c
View File

@ -6,6 +6,12 @@
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/sama5_matrix.h>
#include <asm/arch/sama5_sfr.h>
#include <asm/arch/sama5d4.h>
char *get_cpu_name()
@ -28,3 +34,60 @@ char *get_cpu_name()
else
return "Unknown CPU type";
}
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
void at91_udp_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/* Enable UPLL clock */
writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
/* Enable UDPHS clock */
at91_periph_clk_enable(ATMEL_ID_UDPHS);
}
#endif
#ifdef CONFIG_SPL_BUILD
void matrix_init(void)
{
struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0;
struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
int i;
/* Disable the write protect */
writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
/* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
for (i = 4; i <= 10; i++) {
writel(0x000f0f0f, &h64mx->ssr[i]);
writel(0x0000ffff, &h64mx->sassr[i]);
writel(0x0000000f, &h64mx->srtsr[i]);
}
/* CS3 */
writel(0x00c0c0c0, &h32mx->ssr[3]);
writel(0xff000000, &h32mx->sassr[3]);
writel(0xff000000, &h32mx->srtsr[3]);
/* NFC SRAM */
writel(0x00010101, &h32mx->ssr[4]);
writel(0x00000001, &h32mx->sassr[4]);
writel(0x00000001, &h32mx->srtsr[4]);
/* Enable the write protect */
writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
}
void redirect_int_from_saic_to_aic(void)
{
struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
u32 key32;
if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
}
}
#endif

2
arch/arm/cpu/armv7/cpu.c
View File

@ -53,7 +53,7 @@ int cleanup_before_linux(void)
* After D-cache is flushed and before it is disabled there may
* be some new valid entries brought into the cache. We are sure
* that these lines are not dirty and will not affect our execution.
* (because unwinding the call-stack and setting a bit in CP15 SCTRL
* (because unwinding the call-stack and setting a bit in CP15 SCTLR
* is all we did during this. We have not pushed anything on to the
* stack. Neither have we affected any static data)
* So just invalidate the entire d-cache again to avoid coherency

27
arch/arm/cpu/armv7/exynos/pinmux.c
View File

@ -266,22 +266,33 @@ static void exynos5_sromc_config(int flags)
static void exynos5_i2c_config(int peripheral, int flags)
{
int func01, func23;
/* High-Speed I2C */
if (flags & PINMUX_FLAG_HS_MODE) {
func01 = 4;
func23 = 4;
} else {
func01 = 2;
func23 = 3;
}
switch (peripheral) {
case PERIPH_ID_I2C0:
gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(func01));
gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(func01));
break;
case PERIPH_ID_I2C1:
gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(func01));
gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(func01));
break;
case PERIPH_ID_I2C2:
gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(func23));
gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(func23));
break;
case PERIPH_ID_I2C3:
gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(func23));
gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(func23));
break;
case PERIPH_ID_I2C4:
gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));

49
arch/arm/cpu/armv7/ls102xa/fdt.c
View File

@ -15,6 +15,8 @@
#include <fsl_esdhc.h>
#endif
#include <tsec.h>
#include <asm/arch/immap_ls102xa.h>
#include <fsl_sec.h>
DECLARE_GLOBAL_DATA_PTR;
@ -77,9 +79,24 @@ void ft_cpu_setup(void *blob, bd_t *bd)
int off;
int val;
const char *sysclk_path;
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
unsigned int svr;
svr = in_be32(&gur->svr);
unsigned long busclk = get_bus_freq(0);
/* delete crypto node if not on an E-processor */
if (!IS_E_PROCESSOR(svr))
fdt_fixup_crypto_node(blob, 0);
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
else {
ccsr_sec_t __iomem *sec;
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
fdt_fixup_ethernet(blob);
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
@ -107,6 +124,25 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
#define UBOOT_HEAD_LEN 0x1000
/*
* Reserved memory in SD boot deep sleep case.
* Second stage uboot binary and malloc space should be reserved.
* If the memory they occupied has not been reserved, then this
* space would be used by kernel and overwritten in uboot when
* deep sleep resume, which cause deep sleep failed.
* Since second uboot binary has a head, that space need to be
* reserved either(assuming its size is less than 0x1000).
*/
off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
UBOOT_HEAD_LEN);
if (off < 0)
printf("Failed to reserve memory for SD boot deep sleep: %s\n",
fdt_strerror(off));
#endif
#if defined(CONFIG_FSL_ESDHC)
fdt_fixup_esdhc(blob, bd);
#endif
@ -133,4 +169,17 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
"clock-frequency", busclk / 2, 1);
#ifdef CONFIG_QSPI_BOOT
off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
CONFIG_SYS_IFC_ADDR);
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
#else
off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
QSPI0_BASE_ADDR);
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
DSPI1_BASE_ADDR);
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
#endif
}

10
arch/arm/cpu/armv7/omap-common/boot-common.c
View File

@ -106,6 +106,16 @@ u32 spl_boot_mode(void)
void spl_board_init(void)
{
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
* to prevent overwrites.
*/
save_omap_boot_params();
/* Prepare console output */
preloader_console_init();
#ifdef CONFIG_SPL_NAND_SUPPORT
gpmc_init();
#endif

83
arch/arm/cpu/armv7/omap-common/clocks-common.c
View File

@ -437,12 +437,15 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
{
u32 offset_code;
u32 offset = volt_mv;
#ifndef CONFIG_DRA7XX
int ret = 0;
#endif
if (!volt_mv)
return;
pmic->pmic_bus_init();
#ifndef CONFIG_DRA7XX
/* See if we can first get the GPIO if needed */
if (pmic->gpio_en)
ret = gpio_request(pmic->gpio, "PMIC_GPIO");
@ -456,7 +459,7 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
/* Pull the GPIO low to select SET0 register, while we program SET1 */
if (pmic->gpio_en)
gpio_direction_output(pmic->gpio, 0);
#endif
/* convert to uV for better accuracy in the calculations */
offset *= 1000;
@ -467,9 +470,10 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
printf("Scaling voltage failed for 0x%x\n", vcore_reg);
#ifndef CONFIG_DRA7XX
if (pmic->gpio_en)
gpio_direction_output(pmic->gpio, 1);
#endif
}
static u32 optimize_vcore_voltage(struct volts const *v)
@ -505,13 +509,79 @@ static u32 optimize_vcore_voltage(struct volts const *v)
}
/*
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
* We set the maximum voltages allowed here because Smart-Reflex is not
* enabled in bootloader. Voltage initialization in the kernel will set
* these to the nominal values after enabling Smart-Reflex
* Setup the voltages for the main SoC core power domains.
* We start with the maximum voltages allowed here, as set in the corresponding
* vcores_data struct, and then scale (usually down) to the fused values that
* are retrieved from the SoC. The scaling happens only if the efuse.reg fields
* are initialised.
* Rail grouping is supported for the DRA7xx SoCs only, therefore the code is
* compiled conditionally. Note that the new code writes the scaled (or zeroed)
* values back to the vcores_data struct for eventual reuse. Zero values mean
* that the corresponding rails are not controlled separately, and are not sent
* to the PMIC.
*/
void scale_vcores(struct vcores_data const *vcores)
{
#if defined(CONFIG_DRA7XX)
int i;
struct volts *pv = (struct volts *)vcores;
struct volts *px;
for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) {
debug("%d -> ", pv->value);
if (pv->value) {
/* Handle non-empty members only */
pv->value = optimize_vcore_voltage(pv);
px = (struct volts *)vcores;
while (px < pv) {
/*
* Scan already handled non-empty members to see
* if we have a group and find the max voltage,
* which is set to the first occurance of the
* particular SMPS; the other group voltages are
* zeroed.
*/
if (px->value) {
if ((pv->pmic->i2c_slave_addr ==
px->pmic->i2c_slave_addr) &&
(pv->addr == px->addr)) {
/* Same PMIC, same SMPS */
if (pv->value > px->value)
px->value = pv->value;
pv->value = 0;
}
}
px++;
}
}
debug("%d\n", pv->value);
pv++;
}
debug("cor: %d\n", vcores->core.value);
do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic);
debug("mpu: %d\n", vcores->mpu.value);
do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic);
/* Configure MPU ABB LDO after scale */
abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
(*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
(*prcm)->prm_abbldo_mpu_setup,
(*prcm)->prm_abbldo_mpu_ctrl,
(*prcm)->prm_irqstatus_mpu_2,
OMAP_ABB_MPU_TXDONE_MASK,
OMAP_ABB_FAST_OPP);
/* The .mm member is not used for the DRA7xx */
debug("gpu: %d\n", vcores->gpu.value);
do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic);
debug("eve: %d\n", vcores->eve.value);
do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic);
debug("iva: %d\n", vcores->iva.value);
do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic);
/* Might need udelay(1000) here if debug is enabled to see all prints */
#else
u32 val;
val = optimize_vcore_voltage(&vcores->core);
@ -540,6 +610,7 @@ void scale_vcores(struct vcores_data const *vcores)
val = optimize_vcore_voltage(&vcores->iva);
do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
#endif
}
static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)

11
arch/arm/cpu/armv7/omap-common/hwinit-common.c
View File

@ -111,14 +111,6 @@ int arch_cpu_init(void)
*/
void s_init(void)
{
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
* to prevent overwrites.
*/
#ifdef CONFIG_SPL_BUILD
save_omap_boot_params();
#endif
init_omap_revision();
hw_data_init();
@ -133,9 +125,6 @@ void s_init(void)
srcomp_enable();
setup_clocks_for_console();
gd = &gdata;
preloader_console_init();
do_io_settings();
#endif
prcm_init();

9
arch/arm/cpu/armv7/omap3/board.c
View File

@ -119,6 +119,7 @@ int board_mmc_init(bd_t *bis)
void spl_board_init(void)
{
preloader_console_init();
#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
gpmc_init();
#endif
@ -264,14 +265,6 @@ void s_init(void)
ehci_clocks_enable();
#endif
#ifdef CONFIG_SPL_BUILD
gd = &gdata;
preloader_console_init();
timer_init();
#endif
if (!in_sdram)
mem_init();
}

9
arch/arm/cpu/armv7/omap3/clock.c
View File

@ -732,11 +732,20 @@ void per_clocks_enable(void)
setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */
setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */
/* Enable GP9 timer. */
setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */
setbits_le32(&prcm_base->iclken_per, 0x400); /* ICKen GPT9 */
setbits_le32(&prcm_base->fclken_per, 0x400); /* FCKen GPT9 */
#ifdef CONFIG_SYS_NS16550
/* Enable UART1 clocks */
setbits_le32(&prcm_base->fclken1_core, 0x00002000);
setbits_le32(&prcm_base->iclken1_core, 0x00002000);
/* Enable UART2 clocks */
setbits_le32(&prcm_base->fclken1_core, 0x00004000);
setbits_le32(&prcm_base->iclken1_core, 0x00004000);
/* UART 3 Clocks */
setbits_le32(&prcm_base->fclken_per, 0x00000800);
setbits_le32(&prcm_base->iclken_per, 0x00000800);

6
arch/arm/cpu/armv7/omap3/sdrc.c
View File

@ -135,6 +135,9 @@ void do_sdrc_init(u32 cs, u32 early)
sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
/* set some default timings */
timings.sharing = SDRC_SHARING;
/*
* When called in the early context this may be SPL and we will
* need to set all of the timings. This ends up being board
@ -145,6 +148,7 @@ void do_sdrc_init(u32 cs, u32 early)
* setup CS1.
*/
#ifdef CONFIG_SPL_BUILD
/* set/modify board-specific timings */
get_board_mem_timings(&timings);
#endif
if (early) {
@ -155,7 +159,7 @@ void do_sdrc_init(u32 cs, u32 early)
writel(0, &sdrc_base->sysconfig);
/* setup sdrc to ball mux */
writel(SDRC_SHARING, &sdrc_base->sharing);
writel(timings.sharing, &sdrc_base->sharing);
/* Disable Power Down of CKE because of 1 CKE on combo part */
writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,

45
arch/arm/cpu/armv7/omap5/hw_data.c
View File

@ -320,6 +320,7 @@ struct pmic_data palmas = {
.pmic_write = omap_vc_bypass_send_value,
};
/* The TPS659038 and TPS65917 are software-compatible, use common struct */
struct pmic_data tps659038 = {
.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
.step = 10000, /* 10 mV represented in uV */
@ -394,34 +395,38 @@ struct vcores_data dra752_volts = {
};
struct vcores_data dra722_volts = {
.mpu.value = 1000,
.mpu.value = VDD_MPU_DRA72x,
.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = 0x23,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS65917_REG_ADDR_SMPS1,
.mpu.pmic = &tps659038,
.eve.value = 1000,
.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = 0x2f,
.eve.pmic = &tps659038,
.gpu.value = 1000,
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = 0x2f,
.gpu.pmic = &tps659038,
.core.value = 1000,
.core.value = VDD_CORE_DRA72x,
.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = 0x27,
.core.addr = TPS65917_REG_ADDR_SMPS2,
.core.pmic = &tps659038,
.iva.value = 1000,
/*
* The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
* designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
*/
.gpu.value = VDD_GPU_DRA72x,
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic = &tps659038,
.eve.value = VDD_EVE_DRA72x,
.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS65917_REG_ADDR_SMPS3,
.eve.pmic = &tps659038,
.iva.value = VDD_IVA_DRA72x,
.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = 0x2f,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS65917_REG_ADDR_SMPS3,
.iva.pmic = &tps659038,
};

6
arch/arm/cpu/armv7/start.S
View File

@ -52,10 +52,10 @@ reset:
* Continue to use ROM code vector only in OMAP4 spl)
*/
#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
/* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
bic r0, #CR_V @ V = 0
mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
/* Set vector address in CP15 VBAR register */
ldr r0, =_start

3
arch/arm/cpu/armv7/sunxi/Makefile
View File

@ -15,13 +15,16 @@ obj-y += pinmux.o
obj-y += usbc.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
obj-$(CONFIG_MACH_SUN8I) += prcm.o
obj-$(CONFIG_MACH_SUN9I) += prcm.o
obj-$(CONFIG_MACH_SUN6I) += p2wi.o
obj-$(CONFIG_MACH_SUN8I) += rsb.o
obj-$(CONFIG_MACH_SUN9I) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o
ifndef CONFIG_SPL_BUILD
ifdef CONFIG_ARMV7_PSCI

114
arch/arm/cpu/armv7/sunxi/board.c
View File

@ -27,28 +27,7 @@
#include <linux/compiler.h>
#ifdef CONFIG_SPL_BUILD
/* Pointer to the global data structure for SPL */
DECLARE_GLOBAL_DATA_PTR;
/* The sunxi internal brom will try to loader external bootloader
* from mmc0, nand flash, mmc2.
* Unfortunately we can't check how SPL was loaded so assume
* it's always the first SD/MMC controller
*/
u32 spl_boot_device(void)
{
return BOOT_DEVICE_MMC1;
}
/* No confirmation data available in SPL yet. Hardcode bootmode */
u32 spl_boot_mode(void)
{
return MMCSD_MODE_RAW;
}
#endif
int gpio_init(void)
static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
@ -86,6 +65,62 @@ int gpio_init(void)
return 0;
}
void s_init(void)
{
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
/* Magic (undocmented) value taken from boot0, without this DRAM
* access gets messed up (seems cache related) */
setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
#endif
#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
"orr r0, r0, #1 << 6\n"
"mcr p15, 0, r0, c1, c0, 1\n");
#endif
clock_init();
timer_init();
gpio_init();
i2c_init_board();
}
#ifdef CONFIG_SPL_BUILD
/* The sunxi internal brom will try to loader external bootloader
* from mmc0, nand flash, mmc2.
* Unfortunately we can't check how SPL was loaded so assume
* it's always the first SD/MMC controller
*/
u32 spl_boot_device(void)
{
return BOOT_DEVICE_MMC1;
}
/* No confirmation data available in SPL yet. Hardcode bootmode */
u32 spl_boot_mode(void)
{
return MMCSD_MODE_RAW;
}
void board_init_f(ulong dummy)
{
preloader_console_init();
#ifdef CONFIG_SPL_I2C_SUPPORT
/* Needed early by sunxi_board_init if PMU is enabled */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
sunxi_board_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
board_init_r(NULL, 0);
}
#endif
void reset_cpu(ulong addr)
{
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
@ -111,41 +146,6 @@ void reset_cpu(ulong addr)
#endif
}
/* do some early init */
void s_init(void)
{
#if defined CONFIG_SPL_BUILD && \
(defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
/* Magic (undocmented) value taken from boot0, without this DRAM
* access gets messed up (seems cache related) */
setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
#endif
#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
"orr r0, r0, #1 << 6\n"
"mcr p15, 0, r0, c1, c0, 1\n");
#endif
clock_init();
timer_init();
gpio_init();
i2c_init_board();
#ifdef CONFIG_SPL_BUILD
gd = &gdata;
preloader_console_init();
#ifdef CONFIG_SPL_I2C_SUPPORT
/* Needed early by sunxi_board_init if PMU is enabled */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
sunxi_board_init();
#endif
}
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{

5
arch/arm/cpu/armv7/sunxi/clock_sun6i.c
View File

@ -45,10 +45,10 @@ void clock_init_safe(void)
void clock_init_uart(void)
{
#if CONFIG_CONS_INDEX < 5
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
#if CONFIG_CONS_INDEX < 5
/* uart clock source is apb2 */
writel(APB2_CLK_SRC_OSC24M|
APB2_CLK_RATE_N_1|
@ -68,9 +68,6 @@ void clock_init_uart(void)
/* enable R_PIO and R_UART clocks, and de-assert resets */
prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
#endif
/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
}
int clock_twi_onoff(int port, int state)

68
arch/arm/cpu/armv7/sunxi/clock_sun9i.c Normal file
View File

@ -0,0 +1,68 @@
/*
* sun9i specific clock code
*
* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/prcm.h>
#include <asm/arch/sys_proto.h>
void clock_init_uart(void)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* open the clock for uart */
setbits_le32(&ccm->apb1_gate,
CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
CONFIG_CONS_INDEX - 1));
/* deassert uart reset */
setbits_le32(&ccm->apb1_reset_cfg,
1 << (APB1_RESET_UART_SHIFT +
CONFIG_CONS_INDEX - 1));
/* Dup with clock_init_safe(), drop once sun9i SPL support lands */
writel(PLL4_CFG_DEFAULT, &ccm->pll4_periph0_cfg);
}
int clock_twi_onoff(int port, int state)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (port > 4)
return -1;
/* set the apb reset and clock gate for twi */
if (state) {
setbits_le32(&ccm->apb1_gate,
CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
setbits_le32(&ccm->apb1_reset_cfg,
1 << (APB1_RESET_UART_SHIFT + port));
} else {
clrbits_le32(&ccm->apb1_reset_cfg,
1 << (APB1_RESET_UART_SHIFT + port));
clrbits_le32(&ccm->apb1_gate,
CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
}
return 0;
}
unsigned int clock_get_pll4_periph0(void)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
uint32_t rval = readl(&ccm->pll4_periph0_cfg);
int n = ((rval & CCM_PLL4_CTRL_N_MASK) >> CCM_PLL4_CTRL_N_SHIFT);
int p = ((rval & CCM_PLL4_CTRL_P_MASK) >> CCM_PLL4_CTRL_P_SHIFT);
int m = ((rval & CCM_PLL4_CTRL_M_MASK) >> CCM_PLL4_CTRL_M_SHIFT) + 1;
const int k = 1;
return ((24000000 * n * k) >> p) / m;
}

22
arch/arm/cpu/armv7/sunxi/rsb.c
View File

@ -16,14 +16,27 @@
#include <asm/arch/prcm.h>
#include <asm/arch/rsb.h>
static int rsb_set_device_mode(void);
static void rsb_cfg_io(void)
{
#ifdef CONFIG_MACH_SUN8I
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
#elif defined CONFIG_MACH_SUN9I
sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN0_R_RSB_SCK);
sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN1_R_RSB_SDA);
sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
#else
#error unsupported MACH_SUNXI
#endif
}
static void rsb_set_clk(void)
@ -42,7 +55,7 @@ static void rsb_set_clk(void)
writel((cd_odly << 8) | div, &rsb->ccr);
}
void rsb_init(void)
int rsb_init(void)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
@ -54,6 +67,8 @@ void rsb_init(void)
writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
rsb_set_clk();
return rsb_set_device_mode();
}
static int rsb_await_trans(void)
@ -88,13 +103,14 @@ static int rsb_await_trans(void)
return ret;
}
int rsb_set_device_mode(u32 device_mode_data)
static int rsb_set_device_mode(void)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
unsigned long tmo = timer_get_us() + 1000000;
writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, &rsb->dmcr);
writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
&rsb->dmcr);
while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
if (timer_get_us() > tmo)

11
arch/arm/cpu/armv7/uniphier/Kconfig
View File

@ -50,21 +50,12 @@ endchoice
config CMD_PINMON
bool "Enable boot mode pins monitor command"
depends on !SPL_BUILD
default y
help
The command "pinmon" shows the state of the boot mode pins.
The boot mode pins are latched when the system reset is deasserted
and determine which device the system should load a boot image from.
config SOC_INIT
bool
default SPL_BUILD
config DRAM_INIT
bool
default SPL_BUILD
config CMD_DDRPHY_DUMP
bool "Enable dump command of DDR PHY parameters"
depends on !SPL_BUILD
@ -74,7 +65,7 @@ config CMD_DDRPHY_DUMP
choice
prompt "DDR3 Frequency select"
depends on DRAM_INIT
depends on SPL_BUILD
config DDR_FREQ_1600
bool "DDR3 1600"

27
arch/arm/cpu/armv7/uniphier/Makefile
View File

@ -2,23 +2,32 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_SPL_BUILD) += lowlevel_init.o init_page_table.o
obj-$(CONFIG_SPL_BUILD) += spl.o
ifdef CONFIG_SPL_BUILD
obj-y += timer.o
obj-y += reset.o
obj-y += cache_uniphier.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o
obj-y += dram_init.o
obj-$(CONFIG_DRAM_INIT) += ddrphy_training.o
obj-y += lowlevel_init.o
obj-y += init_page_table.o
obj-y += spl.o
obj-y += ddrphy_training.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o
obj-y += dram_init.o
obj-y += board_common.o
obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-y += reset.o
obj-y += cache_uniphier.o
obj-$(CONFIG_UNIPHIER_SMP) += smp.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
obj-y += board_common.o
endif
obj-y += timer.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o

22
arch/arm/cpu/armv7/uniphier/board_early_init_f.c Normal file
View File

@ -0,0 +1,22 @@
/*
* Copyright (C) 2012-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/led.h>
#include <asm/arch/board.h>
void pin_init(void);
int board_early_init_f(void)
{
led_write(U, 0, , );
pin_init();
led_write(U, 1, , );
return 0;
}

47
arch/arm/cpu/armv7/uniphier/board_postclk_init.c
View File

@ -1,47 +0,0 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/compiler.h>
#include <asm/arch/led.h>
#include <asm/arch/board.h>
void __weak bcu_init(void)
{
};
void sbc_init(void);
void sg_init(void);
void pll_init(void);
void pin_init(void);
void clkrst_init(void);
int board_postclk_init(void)
{
#ifdef CONFIG_SOC_INIT
bcu_init();
sbc_init();
sg_init();
uniphier_board_reset();
pll_init();
uniphier_board_init();
led_write(B, 1, , );
clkrst_init();
led_write(B, 2, , );
#endif
pin_init();
led_write(B, 3, , );
return 0;
}

15
arch/arm/cpu/armv7/uniphier/cmd_pinmon.c
View File

@ -11,20 +11,17 @@
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct boot_device_info *table;
u32 mode_sel, n = 0;
mode_sel = get_boot_mode_sel();
int mode_sel, i;
printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
mode_sel = get_boot_mode_sel();
puts("Boot Mode Pin:\n");
for (table = boot_device_table; strlen(table->info); table++) {
printf(" %c %02x %s\n", n == mode_sel ? '*' : ' ', n,
table->info);
n++;
}
for (i = 0; boot_device_table[i].info; i++)
printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
boot_device_table[i].info);
return 0;
}

23
arch/arm/cpu/armv7/uniphier/dram_init.c
View File

@ -1,37 +1,16 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Copyright (C) 2012-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/led.h>
int umc_init(void);
void enable_dpll_ssc(void);
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#ifdef CONFIG_DRAM_INIT
led_write(B, 4, , );
{
int res;
res = umc_init();
if (res < 0)
return res;
}
led_write(B, 5, , );
enable_dpll_ssc();
#endif
led_write(B, 6, , );
return 0;
}

26
arch/arm/cpu/armv7/uniphier/init_page_table.S Normal file
View File

@ -0,0 +1,26 @@
#include <config.h>
#include <linux/linkage.h>
/* page table */
#define NR_SECTIONS 4096
#define SECTION_SHIFT 20
#define DEVICE 0x00002002 /* Non-shareable Device */
#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
#define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT))
#define STACK_SECTION ((CONFIG_SYS_INIT_SP_ADDR) >> (SECTION_SHIFT))
.section ".rodata"
.align 14
ENTRY(init_page_table)
section = 0
.rept NR_SECTIONS
.if section == TEXT_SECTION || section == STACK_SECTION
attr = NORMAL
.else
attr = DEVICE
.endif
.word (section << SECTION_SHIFT) | attr
section = section + 1
.endr
END(init_page_table)

1069
arch/arm/cpu/armv7/uniphier/init_page_table.c
View File

File diff suppressed because it is too large Load Diff

16
arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
View File

@ -2,11 +2,13 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
clkrst_init.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o
obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
pll_spectrum.o umc_init.o ddrphy_init.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
endif
obj-y += boot-mode.o

6
arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
View File

@ -11,7 +11,7 @@
#undef DPLL_SSC_RATE_1PER
void dpll_init(void)
static void dpll_init(void)
{
u32 tmp;
@ -42,7 +42,7 @@ void dpll_init(void)
writel(tmp, SC_DPLLCTRL2);
}
void upll_init(void)
static void upll_init(void)
{
u32 tmp, clk_mode_upll, clk_mode_axosel;
@ -82,7 +82,7 @@ void upll_init(void)
writel(tmp, SC_UPLLCTRL);
}
void vpll_init(void)
static void vpll_init(void)
{
u32 tmp, clk_mode_axosel;

2
arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
View File

@ -21,7 +21,7 @@ void sg_init(void)
#endif
writel(tmp, SG_MEMCONF);
/* Input ports must be enabled deasserting reset of cores */
/* Input ports must be enabled before deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 0x1;
writel(tmp, SG_IECTRL);

8
arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c
View File

@ -9,7 +9,7 @@
#include <asm/arch/umc-regs.h>
#include <asm/arch/ddrphy-regs.h>
static inline void umc_start_ssif(void __iomem *ssif_base)
static void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000000, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
@ -43,8 +43,8 @@ static inline void umc_start_ssif(void __iomem *ssif_base)
writel(0x00000001, ssif_base + UMC_DMDRST);
}
void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
{
if (freq == 1333) {
writel(0x45990b11, dramcont + UMC_CMDCTLA);
@ -119,7 +119,7 @@ void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
}
static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
static int umc_init_sub(int freq, int size_ch0, int size_ch1)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);

15
arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
View File

@ -2,10 +2,13 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o
obj-y += sbc_init.o sg_init.o pll_init.o clkrst_init.o \
pll_spectrum.o umc_init.o ddrphy_init.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
endif
obj-y += boot-mode.o

16
arch/arm/cpu/armv7/uniphier/ph1-pro4/board_info.c
View File

@ -1,16 +0,0 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/board.h>
int checkboard(void)
{
puts("Board: PH1-Pro4 Board\n");
return check_support_card();
}

6
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c
View File

@ -45,17 +45,17 @@ struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, ""}
{ /* sentinel */ }
};
u32 get_boot_mode_sel(void)
int get_boot_mode_sel(void)
{
return (readl(SG_PINMON0) >> 1) & 0x1f;
}
u32 spl_boot_device(void)
{
u32 boot_mode;
int boot_mode;
if (boot_is_swapped())
return BOOT_DEVICE_NOR;

6
arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c
View File

@ -11,7 +11,7 @@
#undef DPLL_SSC_RATE_1PER
void dpll_init(void)
static void dpll_init(void)
{
u32 tmp;
@ -46,7 +46,7 @@ void dpll_init(void)
writel(tmp, SC_DPLLCTRL2);
}
void stop_mpll(void)
static void stop_mpll(void)
{
u32 tmp;
@ -62,7 +62,7 @@ void stop_mpll(void)
;
}
void vpll_init(void)
static void vpll_init(void)
{
u32 tmp, clk_mode_axosel;

4
arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
View File

@ -21,8 +21,8 @@ void sg_init(void)
#endif
writel(tmp, SG_MEMCONF);
/* Input ports must be enabled deasserting reset of cores */
/* Input ports must be enabled before deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 0x1;
tmp |= 1 << 6;
writel(tmp, SG_IECTRL);
}

8
arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c
View File

@ -9,7 +9,7 @@
#include <asm/arch/umc-regs.h>
#include <asm/arch/ddrphy-regs.h>
static inline void umc_start_ssif(void __iomem *ssif_base)
static void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000001, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
@ -52,8 +52,8 @@ static inline void umc_start_ssif(void __iomem *ssif_base)
writel(0x00000001, ssif_base + UMC_DMDRST);
}
void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
{
writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
@ -88,7 +88,7 @@ void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
}
static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
static int umc_init_sub(int freq, int size_ch0, int size_ch1)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);

16
arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
View File

@ -2,11 +2,13 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
obj-y += boot-mode.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
clkrst_init.o
obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o
obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
pll_spectrum.o umc_init.o ddrphy_init.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
endif
obj-y += boot-mode.o

16
arch/arm/cpu/armv7/uniphier/ph1-sld8/board_info.c
View File

@ -1,16 +0,0 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/board.h>
int checkboard(void)
{
puts("Board: PH1-sLD8 Board\n");
return check_support_card();
}

9
arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c
View File

@ -26,6 +26,15 @@ void pin_init(void)
sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
#endif
#ifdef CONFIG_SYS_I2C_UNIPHIER
{
u32 tmp;
tmp = readl(SG_IECTRL);
tmp |= 0xc00; /* enable SCL0, SDA0, SCL1, SDA1 */
writel(tmp, SG_IECTRL);
}
#endif
#ifdef CONFIG_NAND_DENALI
sg_set_pinsel(15, 0); /* XNFRE_GB -> XNFRE_GB */
sg_set_pinsel(16, 0); /* XNFWE_GB -> XNFWE_GB */

6
arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c
View File

@ -9,7 +9,7 @@
#include <asm/arch/sc-regs.h>
#include <asm/arch/sg-regs.h>
void dpll_init(void)
static void dpll_init(void)
{
u32 tmp;
/*
@ -54,7 +54,7 @@ void dpll_init(void)
writel(tmp, SC_DPLLCTRL2);
}
void upll_init(void)
static void upll_init(void)
{
u32 tmp, clk_mode_upll, clk_mode_axosel;
@ -94,7 +94,7 @@ void upll_init(void)
writel(tmp, SC_UPLLCTRL);
}
void vpll_init(void)
static void vpll_init(void)
{
u32 tmp, clk_mode_axosel;

8
arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c
View File

@ -9,7 +9,7 @@
#include <asm/arch/umc-regs.h>
#include <asm/arch/ddrphy-regs.h>
static inline void umc_start_ssif(void __iomem *ssif_base)
static void umc_start_ssif(void __iomem *ssif_base)
{
writel(0x00000000, ssif_base + 0x0000b004);
writel(0xffffffff, ssif_base + 0x0000c004);
@ -43,8 +43,8 @@ static inline void umc_start_ssif(void __iomem *ssif_base)
writel(0x00000001, ssif_base + UMC_DMDRST);
}
void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
int size, int freq)
{
#ifdef CONFIG_DDR_STANDARD
writel(0x55990b11, dramcont + UMC_CMDCTLA);
@ -99,7 +99,7 @@ void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
}
static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
static int umc_init_sub(int freq, int size_ch0, int size_ch1)
{
void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);

7
arch/arm/cpu/armv7/uniphier/ph1-ld4/board_info.c → arch/arm/cpu/armv7/uniphier/print_misc_info.c
View File

@ -1,16 +1,13 @@
/*
* Copyright (C) 2012-2014 Panasonic Corporation
* Copyright (C) 2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/board.h>
int checkboard(void)
int misc_init_f(void)
{
puts("Board: PH1-LD4 Board\n");
return check_support_card();
}

52
arch/arm/cpu/armv7/uniphier/spl.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2013-2014 Panasonic Corporation
* Copyright (C) 2013-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
@ -7,11 +7,53 @@
#include <common.h>
#include <spl.h>
#include <linux/compiler.h>
#include <asm/arch/led.h>
#include <asm/arch/board.h>
void __weak bcu_init(void)
{
};
void sbc_init(void);
void sg_init(void);
void pll_init(void);
void pin_init(void);
void clkrst_init(void);
int umc_init(void);
void enable_dpll_ssc(void);
void spl_board_init(void)
{
#if defined(CONFIG_BOARD_POSTCLK_INIT)
board_postclk_init();
#endif
dram_init();
bcu_init();
sbc_init();
sg_init();
uniphier_board_reset();
pll_init();
uniphier_board_init();
led_write(L, 0, , );
clkrst_init();
led_write(L, 1, , );
{
int res;
res = umc_init();
if (res < 0) {
while (1)
;
}
}
led_write(L, 2, , );
enable_dpll_ssc();
led_write(L, 3, , );
}

9
arch/arm/cpu/armv7/virt-v7.c
View File

@ -15,8 +15,6 @@
#include <asm/io.h>
#include <asm/secure.h>
unsigned long gic_dist_addr;
static unsigned int read_id_pfr1(void)
{
unsigned int reg;
@ -68,6 +66,12 @@ static void kick_secondary_cpus_gic(unsigned long gicdaddr)
void __weak smp_kick_all_cpus(void)
{
unsigned long gic_dist_addr;
gic_dist_addr = get_gicd_base_address();
if (gic_dist_addr == -1)
return;
kick_secondary_cpus_gic(gic_dist_addr);
}
@ -75,6 +79,7 @@ int armv7_init_nonsec(void)
{
unsigned int reg;
unsigned itlinesnr, i;
unsigned long gic_dist_addr;
/* check whether the CPU supports the security extensions */
reg = read_id_pfr1();

1
arch/arm/cpu/armv7/zynq/Makefile
View File

@ -13,4 +13,5 @@ obj-y += cpu.o
obj-y += ddrc.o
obj-y += slcr.o
obj-y += clk.o
obj-y += lowlevel_init.o
obj-$(CONFIG_SPL_BUILD) += spl.o

7
arch/arm/cpu/armv7/zynq/config.mk Normal file
View File

@ -0,0 +1,7 @@
#
# Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
#
# SPDX-License-Identifier: GPL-2.0
#
# Allow NEON instructions (needed for lowlevel_init.S with GNU toolchain)
PLATFORM_RELFLAGS += -mfpu=neon

4
arch/arm/cpu/armv7/zynq/cpu.c
View File

@ -10,10 +10,6 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
void lowlevel_init(void)
{
}
#define ZYNQ_SILICON_VER_MASK 0xF0000000
#define ZYNQ_SILICON_VER_SHIFT 28

2
arch/arm/cpu/armv7/zynq/ddrc.c
View File

@ -42,6 +42,8 @@ void zynq_ddrc_init(void)
*/
/* cppcheck-suppress nullPointer */
memset((void *)0, 0, 1 * 1024 * 1024);
gd->ram_size /= 2;
} else {
puts("ECC disabled ");
}

26
arch/arm/cpu/armv7/zynq/lowlevel_init.S Normal file
View File

@ -0,0 +1,26 @@
/*
* Copyright (C) 2013 Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
ENTRY(lowlevel_init)
/* Enable the the VFP */
mrc p15, 0, r1, c1, c0, 2
orr r1, r1, #(0x3 << 20)
orr r1, r1, #(0x3 << 20)
mcr p15, 0, r1, c1, c0, 2
isb
fmrx r1, FPEXC
orr r1,r1, #(1<<30)
fmxr FPEXC, r1
/* Move back to caller */
mov pc, lr
ENDPROC(lowlevel_init)

2
arch/arm/cpu/armv7/zynq/slcr.c
View File

@ -132,7 +132,7 @@ void zynq_slcr_devcfg_disable(void)
zynq_slcr_unlock();
/* Disable AXI interface by asserting FPGA resets */
writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
writel(0xF, &slcr_base->fpga_rst_ctrl);
/* Set Level Shifters DT618760 */
writel(0xA, &slcr_base->lvl_shftr_en);

12
arch/arm/cpu/armv7/zynq/spl.c
View File

@ -20,9 +20,6 @@ void board_init_f(ulong dummy)
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* Set global data pointer. */
gd = &gdata;
preloader_console_init();
arch_cpu_init();
board_init_r(NULL, 0);
@ -46,12 +43,21 @@ u32 spl_boot_device(void)
mode = BOOT_DEVICE_SPI;
break;
#endif
case ZYNQ_BM_NAND:
mode = BOOT_DEVICE_NAND;
break;
case ZYNQ_BM_NOR:
mode = BOOT_DEVICE_NOR;
break;
#ifdef CONFIG_SPL_MMC_SUPPORT
case ZYNQ_BM_SD:
puts("mmc boot\n");
mode = BOOT_DEVICE_MMC1;
break;
#endif
case ZYNQ_BM_JTAG:
mode = BOOT_DEVICE_RAM;
break;
default:
puts("Unsupported boot mode selected\n");
hang();

1
arch/arm/cpu/at91-common/Makefile
View File

@ -13,5 +13,6 @@ ifneq ($(CONFIG_SPL_BUILD),)
obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
obj-y += spl.o
endif

2
arch/arm/cpu/at91-common/mpddrc.c
View File

@ -19,7 +19,7 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
static int ddr2_decodtype_is_seq(u32 cr)
{
#if defined(CONFIG_SAMA5D3)
#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
return 0;
#endif

4
arch/arm/cpu/at91-common/spl.c
View File

@ -12,12 +12,16 @@
#include <asm/arch/clk.h>
#include <spl.h>
#if defined(CONFIG_AT91SAM9_WATCHDOG)
void at91_disable_wdt(void) { }
#else
void at91_disable_wdt(void)
{
struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT;
writel(AT91_WDT_MR_WDDIS, &wdt->mr);
}
#endif
u32 spl_boot_device(void)
{

16
arch/arm/cpu/at91-common/spl_atmel.c
View File

@ -51,11 +51,23 @@ static void switch_to_main_crystal_osc(void)
while (!(readl(&pmc->mcfr) & AT91_PMC_MAINRDY))
;
#ifndef CONFIG_SAMA5D4
tmp = readl(&pmc->mor);
tmp &= ~AT91_PMC_MOR_MOSCRCEN;
tmp &= ~AT91_PMC_MOR_KEY(0xff);
tmp |= AT91_PMC_MOR_KEY(0x37);
writel(tmp, &pmc->mor);
#endif
}
__weak void matrix_init(void)
{
/* This only be used for sama5d4 soc now */
}
__weak void redirect_int_from_saic_to_aic(void)
{
/* This only be used for sama5d4 soc now */
}
void s_init(void)
@ -70,6 +82,10 @@ void s_init(void)
at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
matrix_init();
redirect_int_from_saic_to_aic();
timer_init();
board_early_init_f();

2
arch/arm/cpu/tegra20-common/pmu.c
View File

@ -52,7 +52,7 @@ int pmu_set_nominal(void)
debug("%s: Cannot find DVC I2C bus\n", __func__);
return ret;
}
ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, &dev);
ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, 1, &dev);
if (ret) {
debug("%s: Cannot find DVC I2C chip\n", __func__);
return ret;

31
arch/arm/dts/exynos4.dtsi
View File

@ -51,56 +51,64 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <0 0 0>;
reg = <0x13860000 0x100>;
interrupts = <0 56 0>;
};
i2c@13870000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <1 1 0>;
reg = <0x13870000 0x100>;
interrupts = <1 57 0>;
};
i2c@13880000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <2 2 0>;
reg = <0x13880000 0x100>;
interrupts = <2 58 0>;
};
i2c@13890000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <3 3 0>;
reg = <0x13890000 0x100>;
interrupts = <3 59 0>;
};
i2c@138a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <4 4 0>;
reg = <0x138a0000 0x100>;
interrupts = <4 60 0>;
};
i2c@138b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <5 5 0>;
reg = <0x138b0000 0x100>;
interrupts = <5 61 0>;
};
i2c@138c0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <6 6 0>;
reg = <0x138c0000 0x100>;
interrupts = <6 62 0>;
};
i2c@138d0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <7 7 0>;
reg = <0x138d0000 0x100>;
interrupts = <7 63 0>;
};
sdhci@12510000 {
@ -143,11 +151,4 @@
interrupts = <0 131 0>;
};
gpio: gpio {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

2
arch/arm/dts/exynos4210-origen.dts
View File

@ -36,7 +36,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 0xA2 0>;
cd-gpios = <&gpk2 2 0>;
};
sdhci@12540000 {

4
arch/arm/dts/exynos4210-trats.dts
View File

@ -101,7 +101,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 146 0>;
pwr-gpios = <&gpk0 2 0>;
};
sdhci@12520000 {
@ -111,7 +111,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 284 0>;
cd-gpios = <&gpx3 4 0>;
};
sdhci@12540000 {

12
arch/arm/dts/exynos4210-universal_c210.dts
View File

@ -24,7 +24,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 146 0>;
pwr-gpios = <&gpk0 2 0>;
};
sdhci@12520000 {
@ -34,7 +34,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 284 0>;
cd-gpios = <&gpx3 4 0>;
};
sdhci@12540000 {
@ -43,10 +43,10 @@
soft-spi {
compatible = "u-boot,soft-spi";
cs-gpio = <&gpio 235 0>; /* Y43 */
sclk-gpio = <&gpio 225 0>; /* Y31 */
mosi-gpio = <&gpio 227 0>; /* Y33 */
miso-gpio = <&gpio 224 0>; /* Y30 */
cs-gpio = <&gpy4 3 0>;
sclk-gpio = <&gpy3 1 0>;
mosi-gpio = <&gpy3 3 0>;
miso-gpio = <&gpy3 0 0>;
spi-delay-us = <1>;
#address-cells = <1>;
#size-cells = <0>;

9
arch/arm/dts/exynos4412-odroid.dts
View File

@ -16,6 +16,13 @@
aliases {
i2c0 = "/i2c@13860000";
i2c1 = "/i2c@13870000";
i2c2 = "/i2c@13880000";
i2c3 = "/i2c@13890000";
i2c4 = "/i2c@138a0000";
i2c5 = "/i2c@138b0000";
i2c6 = "/i2c@138c0000";
i2c7 = "/i2c@138d0000";
serial0 = "/serial@13800000";
console = "/serial@13810000";
mmc2 = "sdhci@12530000";
@ -51,7 +58,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 122 0>;
cd-gpios = <&gpk2 2 0>;
};
sdhci@12540000 {

6
arch/arm/dts/exynos4412-trats2.dts
View File

@ -416,7 +416,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 0x6a 0>;
pwr-gpios = <&gpk0 4 0>;
status = "disabled";
};
@ -427,7 +427,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 0x7a 0>;
cd-gpios = <&gpk2 2 0>;
};
sdhci@12540000 {
@ -437,7 +437,7 @@
dwmmc@12550000 {
samsung,bus-width = <8>;
samsung,timing = <2 1 0>;
pwr-gpios = <&gpio 0x6a 0>;
pwr-gpios = <&gpk0 4 0>;
fifoth_val = <0x203f0040>;
bus_hz = <400000000>;
div = <0x3>;

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