powerpc: P4080: Remove macro CONFIG_PPC_P4080
Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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@ -46,6 +46,7 @@ config TARGET_P3041DS
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config TARGET_P4080DS
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bool "Support P4080DS"
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select PHYS_64BIT
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select ARCH_P4080
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config TARGET_P5020DS
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bool "Support P5020DS"
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@ -320,6 +321,9 @@ config ARCH_P2041
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config ARCH_P3041
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bool
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config ARCH_P4080
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bool
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source "board/freescale/b4860qds/Kconfig"
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source "board/freescale/bsc9131rdb/Kconfig"
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source "board/freescale/bsc9132qds/Kconfig"
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@ -41,7 +41,7 @@ obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
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# various SoC specific assignments
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obj-$(CONFIG_ARCH_P2041) += p2041_ids.o
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obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
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obj-$(CONFIG_PPC_P4080) += p4080_ids.o
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obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
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obj-$(CONFIG_PPC_P5020) += p5020_ids.o
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obj-$(CONFIG_PPC_P5040) += p5040_ids.o
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obj-$(CONFIG_PPC_T4240) += t4240_ids.o
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@ -83,7 +83,7 @@ obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o
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obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o
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obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o
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obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
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obj-$(CONFIG_PPC_P4080) += p4080_serdes.o
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obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
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obj-$(CONFIG_PPC_P5020) += p5020_serdes.o
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obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
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obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
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@ -31,7 +31,7 @@ static void check_erratum_a4849(uint32_t svr)
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0x50, 0x54, 0x58, 0x90, 0x94, 0x98
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};
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#endif
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#ifdef CONFIG_PPC_P4080
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#ifdef CONFIG_ARCH_P4080
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static const uint8_t offsets[] = {
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0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
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};
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@ -49,7 +49,7 @@ static void check_erratum_a4849(uint32_t svr)
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x108 = 0x12;
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#endif
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#ifdef CONFIG_PPC_P4080
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#ifdef CONFIG_ARCH_P4080
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/*
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* For P4080, the erratum document says that the value at offset 0x108
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* should be 0x12 on rev2, or 0x1c on rev3.
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@ -490,7 +490,7 @@ static void ft_fixup_qe_snum(void *blob)
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}
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#endif
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#if defined(CONFIG_PPC_P4080)
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#if defined(CONFIG_ARCH_P4080)
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static void fdt_fixup_usb(void *fdt)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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@ -76,7 +76,7 @@ static const struct {
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{ 17, 163, FSL_SRDS_BANK_2 },
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{ 18, 164, FSL_SRDS_BANK_2 },
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{ 19, 165, FSL_SRDS_BANK_2 },
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#ifdef CONFIG_PPC_P4080
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#ifdef CONFIG_ARCH_P4080
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{ 20, 170, FSL_SRDS_BANK_3 },
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{ 21, 171, FSL_SRDS_BANK_3 },
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{ 22, 172, FSL_SRDS_BANK_3 },
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@ -378,7 +378,7 @@
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#define CONFIG_SYS_FSL_ERRATUM_A006261
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#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
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#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
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#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
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#define CONFIG_MAX_CPUS 8
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@ -59,7 +59,7 @@
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#endif
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#if defined(CONFIG_ARCH_P3041) || \
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defined(CONFIG_PPC_P4080) || \
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defined(CONFIG_ARCH_P4080) || \
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defined(CONFIG_PPC_P5020) || \
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defined(CONFIG_PPC_P5040) || \
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defined(CONFIG_ARCH_P2041)
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@ -1848,7 +1848,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
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#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
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#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
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#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
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#ifdef CONFIG_PPC_P4080
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#ifdef CONFIG_ARCH_P4080
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#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
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#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
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#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
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@ -21,7 +21,7 @@ obj-$(CONFIG_ARCH_P1023) += p1023.o
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# The P204x, P304x, and P5020 are the same
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obj-$(CONFIG_ARCH_P2041) += p5020.o
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obj-$(CONFIG_ARCH_P3041) += p5020.o
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obj-$(CONFIG_PPC_P4080) += p4080.o
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obj-$(CONFIG_ARCH_P4080) += p4080.o
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obj-$(CONFIG_PPC_P5020) += p5020.o
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obj-$(CONFIG_PPC_P5040) += p5040.o
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obj-$(CONFIG_PPC_T1040) += t1040.o
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@ -9,7 +9,6 @@
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* Also supports P4040 DS
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*/
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#define CONFIG_P4080DS
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#define CONFIG_PPC_P4080
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#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
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@ -3645,7 +3645,6 @@ CONFIG_PPC64BRIDGE
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CONFIG_PPC_B4420
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CONFIG_PPC_B4860
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CONFIG_PPC_CLUSTER_START
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CONFIG_PPC_P4080
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CONFIG_PPC_P5020
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CONFIG_PPC_P5040
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CONFIG_PPC_SPINTABLE_COMPATIBLE
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