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TI OMAP3 SDP3430: Initial Support

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Start of support of
Texas Instruments Software Development Platform(SDP)
for OMAP3430 - SDP3430

Highlights of this platform are:
Flash Memory devices:
	Sibley NOR, Micron 8bit NAND and OneNAND
Connectivity:
	3 UARTs and expanded 4 UART ports + IrDA
	Ethernet, USB
Other peripherals:
	TWL5030 PMIC+Audio+Keypad
	VGA display
Expansion ports:
	Memory devices plugin boards (PISMO)
	Connectivity board for GPS,WLAN etc.
Completely configurable boot sequence and device mapping
etc.

Support default jumpering and:
 - UART1/ttyS0 console(legacy sdp3430 u-boot)
 - UART3/ttyS2 console (matching other boards,
		 and SDP HW docs)
 - Ethernet
 - mmc0
 - NOR boot

Currently the UART1 is enabled by default.  for
compatibility with other OMAP3 u-boot platforms,
enable the #define of CONSOLE_J9.

Conflicts:

	Makefile

Fixed the conflict with smdkc100_config by moving omap_sdp3430_config
to it is alphabetically sorted location above zoom1.

Signed-off-by: David Brownell <david-b@pacbell.net>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
This commit is contained in:
Tom Rix 2009-10-17 12:41:06 -05:00
parent a4474ff862
commit e63e5904b4
8 changed files with 1077 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
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@ -635,6 +635,7 @@ Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Nishanth Menon <nm@ti.com>
omap3_sdp3430 ARM CORTEX-A8 (OMAP3xx SoC)
omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC)
David Müller <d.mueller@elsoft.ch>

1
MAKEALL
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@ -605,6 +605,7 @@ LIST_ARM_CORTEX_A8=" \
omap3_overo \
omap3_evm \
omap3_pandora \
omap3_sdp3430 \
omap3_zoom1 \
omap3_zoom2 \
smdkc100 \

3
Makefile
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@ -3144,6 +3144,9 @@ omap3_evm_config : unconfig
omap3_pandora_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 pandora NULL omap3
omap3_sdp3430_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 sdp3430 ti omap3
omap3_zoom1_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 logicpd omap3

49
board/ti/sdp3430/Makefile Normal file
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@ -0,0 +1,49 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := sdp.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

33
board/ti/sdp3430/config.mk Normal file
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@ -0,0 +1,33 @@
#
# (C) Copyright 2006-2009
# Texas Instruments Incorporated, <www.ti.com>
#
# OMAP 3430 SDP uses OMAP3 (ARM-CortexA8) cpu
# see http://www.ti.com/ for more information on Texas Instruments
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# Physical Address:
# 8000'0000 (bank0)
# A000/0000 (bank1)
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
# For use with external or internal boots.
TEXT_BASE = 0x80e80000

204
board/ti/sdp3430/sdp.c Normal file
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@ -0,0 +1,204 @@
/*
* (C) Copyright 2004-2009
* Texas Instruments Incorporated, <www.ti.com>
* Richard Woodruff <r-woodruff2@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-types.h>
#include "sdp.h"
const omap3_sysinfo sysinfo = {
DDR_DISCRETE,
"OMAP3 SDP3430 board",
#if defined(CONFIG_ENV_IS_IN_ONENAND)
"OneNAND",
#elif defined(CONFIG_ENV_IS_IN_NAND)
"NAND",
#else
"NOR",
#endif
};
/* Timing definitions for GPMC controller for Sibley NOR */
static const u32 gpmc_sdp_nor[] = {
SDP3430_NOR_GPMC_CONF1,
SDP3430_NOR_GPMC_CONF2,
SDP3430_NOR_GPMC_CONF3,
SDP3430_NOR_GPMC_CONF4,
SDP3430_NOR_GPMC_CONF5,
SDP3430_NOR_GPMC_CONF6,
/*CONF7- computed as params */
};
/*
* Timing definitions for GPMC controller for Debug Board
* Debug board contains access to ethernet and DIP Switch setting
* information etc.
*/
static const u32 gpmc_sdp_debug[] = {
SDP3430_DEBUG_GPMC_CONF1,
SDP3430_DEBUG_GPMC_CONF2,
SDP3430_DEBUG_GPMC_CONF3,
SDP3430_DEBUG_GPMC_CONF4,
SDP3430_DEBUG_GPMC_CONF5,
SDP3430_DEBUG_GPMC_CONF6,
/*CONF7- computed as params */
};
/* Timing defintions for GPMC OneNAND */
static const u32 gpmc_sdp_onenand[] = {
SDP3430_ONENAND_GPMC_CONF1,
SDP3430_ONENAND_GPMC_CONF2,
SDP3430_ONENAND_GPMC_CONF3,
SDP3430_ONENAND_GPMC_CONF4,
SDP3430_ONENAND_GPMC_CONF5,
SDP3430_ONENAND_GPMC_CONF6,
/*CONF7- computed as params */
};
/* GPMC definitions for GPMC NAND */
static const u32 gpmc_sdp_nand[] = {
SDP3430_NAND_GPMC_CONF1,
SDP3430_NAND_GPMC_CONF2,
SDP3430_NAND_GPMC_CONF3,
SDP3430_NAND_GPMC_CONF4,
SDP3430_NAND_GPMC_CONF5,
SDP3430_NAND_GPMC_CONF6,
/*CONF7- computed as params */
};
/* gpmc_cfg is initialized by gpmc_init and we use it here */
extern struct gpmc *gpmc_cfg;
/**
* @brief board_init - gpmc and basic setup as phase1 of boot sequence
*
* @return 0
*/
int board_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* TODO: Dynamically pop out CS mapping and program accordingly */
/* Configure devices for default ON ON ON settings */
enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0],
CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M);
enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000,
GPMC_SIZE_16M);
enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000,
GPMC_SIZE_16M);
enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE,
GPMC_SIZE_16M);
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
return 0;
}
#define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c)
#define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b)
/**
* @brief ether_init Take the Ethernet controller out of reset and wait
* for the EEPROM load to complete.
*/
static void ether_init(void)
{
#ifdef CONFIG_DRIVER_LAN91C96
int cnt = 20;
writew(0x0, LAN_RESET_REGISTER);
do {
writew(0x1, LAN_RESET_REGISTER);
udelay(100);
if (cnt == 0)
goto reset_err_out;
--cnt;
} while (readw(LAN_RESET_REGISTER) != 0x1);
cnt = 20;
do {
writew(0x0, LAN_RESET_REGISTER);
udelay(100);
if (cnt == 0)
goto reset_err_out;
--cnt;
} while (readw(LAN_RESET_REGISTER) != 0x0000);
udelay(1000);
writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG);
udelay(1000);
reset_err_out:
return;
#endif
}
/**
* @brief misc_init_r - Configure SDP board specific configurations
* such as power configurations, ethernet initialization as phase2 of
* boot sequence
*
* @return 0
*/
int misc_init_r(void)
{
/* Partial setup:
* VAUX3 - 2.8V for DVI
* VPLL1 - 1.8V
* VDAC - 1.8V
* and turns on LEDA/LEDB (not needed ... NOP?)
*/
twl4030_power_init();
/* FIXME finish setup:
* VAUX1 - 2.8V for mainboard I/O
* VAUX2 - 2.8V for camera
* VAUX4 - 1.8V for OMAP3 CSI
* VMMC1 - 3.15V (init, variable) for MMC1
* VMMC2 - 1.85V for MMC2
* VSIM - off (init, variable) for MMC1.DAT[3..7], SIM
* VPLL2 - 1.8V
*/
ether_init();
return 0;
}
/**
* @brief set_muxconf_regs Setting up the configuration Mux registers
* specific to the hardware. Many pins need to be moved from protect
* to primary mode.
*/
void set_muxconf_regs(void)
{
/* platform specific muxes */
MUX_SDP3430();
}

417
board/ti/sdp3430/sdp.h Normal file
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@ -0,0 +1,417 @@
/*
* (C) Copyright 2004-2009
* Texas Instruments Incorporated
* Richard Woodruff <r-woodruff2@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _BOARD_SDP_H_
#define _BOARD_SDP_H_
#define OFF_IN_PD 0
#define OFF_OUT_PD 0
/*
* IEN - Input Enable
* IDIS - Input Disable
* PTD - Pull type Down
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
* M0 - Mode 0
* The commented string gives the final mux configuration for that pin
*/
#define MUX_SDP3430()\
/*SDRC*/\
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\
/*GPMC*/\
MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_NCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
MUX_VAL(CP(GPMC_NCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
MUX_VAL(CP(GPMC_NCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
MUX_VAL(CP(GPMC_NCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
MUX_VAL(CP(GPMC_NCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G55-F_DIS*/\
MUX_VAL(CP(GPMC_NCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G56T_EN*/\
MUX_VAL(CP(GPMC_NCS6), (OFF_IN_PD | IEN | PTD | DIS | M4))/*G57-AGPSP*/\
MUX_VAL(CP(GPMC_NCS7), (OFF_IN_PD | IEN | PTU | EN | M4))/*G58-WLNIQ*/\
MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_NADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_NOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_NWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_NBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_NBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*G61-BTST*/\
MUX_VAL(CP(GPMC_NWP), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\
MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\
/*DSS*/\
MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
/*CAMERA*/\
MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G98-C_RST*/\
MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\
MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\
MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\
MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
/*Audio InterfACe */\
MUX_VAL(CP(MCBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MCBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MCBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MCBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
/*Expansion Card */\
MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0))\
/*Wireless LAN */\
MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD0*/\
MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD1*/\
MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DCMD*/\
MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1))/*CLKIN*/\
/*Bluetooth*/\
MUX_VAL(CP(MCBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(MCBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MCBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MCBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
/*Modem Interface */\
MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MCBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1DRX*/\
MUX_VAL(CP(MCBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1FLGRX*/\
MUX_VAL(CP(MCBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1RDYRX*/\
MUX_VAL(CP(MCBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1WAKE*/\
MUX_VAL(CP(MCBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MCBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4))/*G157BWP*/\
MUX_VAL(CP(MCBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(MCBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MCBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
MUX_VAL(CP(MCBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MCBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
/*Serial Interface*/\
MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
/* NOTE db: removed off-mode from I2C 1/2/3 ... external pullups!! */\
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0))\
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0))\
MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(MCSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MCSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MCSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MCSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(MCSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0))\
MUX_VAL(CP(MCSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G176*/\
MUX_VAL(CP(MCSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(MCSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MCSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MCSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(MCSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(MCSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0))\
/*Control and debug */\
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SYS_NIRQ), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G2PENIRQ*/\
MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*GPIO_3 */\
MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G4MMC1WP*/\
MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G5LCDENV*/\
MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G6LANINT*/\
MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G7MMC2WP*/\
MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G8ENBKL*/\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD0*/\
MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SPI3_CS0*/\
MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M1))/*USB1TLD2*/\
MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD7*/\
MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
/*Die to Die */\
MUX_VAL(CP(D2D_MCAD0), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD1), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD2), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD3), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD4), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD5), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD6), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD7), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD8), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD9), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD10), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD11), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD12), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD13), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD14), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD15), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD16), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD17), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD18), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD19), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD20), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD21), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD22), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD23), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD24), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD25), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD26), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD27), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD28), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD29), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD30), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD31), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD32), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD33), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD34), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD35), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_MCAD36), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_CLK26MI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_NRESPWRON), (OFF_OUT_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_NRESWARM), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(D2D_ARM9NIRQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_UMA2P6FIQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_SPINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_FRINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_DMAREQ0), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_DMAREQ1), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_DMAREQ2), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_DMAREQ3), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_N3GTRST), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_N3GTDI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_N3GTDO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_N3GTMS), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_N3GTCK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_N3GRTCK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_MSTDBY), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\
MUX_VAL(CP(D2D_IDLEREQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_IDLEACK), (OFF_IN_PD | IEN | PTU | EN | M0))\
MUX_VAL(CP(D2D_MWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_SWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_MREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_SREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_MBUSFLAG), (OFF_IN_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(D2D_SBUSFLAG), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0))\
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*SDRC_CKE1 NOT USED*/
/*
* GPMC Timing definitions for SDP3430
* at L3 = 166Mhz
*/
/* Timing definitions for GPMC controller for Sibley NOR */
#define SDP3430_NOR_GPMC_CONF1 0x00001200
#define SDP3430_NOR_GPMC_CONF2 0x001F1F00
#define SDP3430_NOR_GPMC_CONF3 0x00080802
#define SDP3430_NOR_GPMC_CONF4 0x1C091C09
#define SDP3430_NOR_GPMC_CONF5 0x01131F1F
#define SDP3430_NOR_GPMC_CONF6 0x1F0F03C2
/*
* Timing definitions for GPMC controller for Debug Board
* Debug board contains access to ethernet and DIP Switch setting
* information etc.
*/
#define SDP3430_DEBUG_GPMC_CONF1 0x00611200
#define SDP3430_DEBUG_GPMC_CONF2 0x001F1F01
#define SDP3430_DEBUG_GPMC_CONF3 0x00080803
#define SDP3430_DEBUG_GPMC_CONF4 0x1D091D09
#define SDP3430_DEBUG_GPMC_CONF5 0x041D1F1F
#define SDP3430_DEBUG_GPMC_CONF6 0x1D0904C4
/* Timing defintions for GPMC OneNAND */
#define SDP3430_ONENAND_GPMC_CONF1 0x00001200
#define SDP3430_ONENAND_GPMC_CONF2 0x000F0F01
#define SDP3430_ONENAND_GPMC_CONF3 0x00030301
#define SDP3430_ONENAND_GPMC_CONF4 0x0F040F04
#define SDP3430_ONENAND_GPMC_CONF5 0x010F1010
#define SDP3430_ONENAND_GPMC_CONF6 0x1F060000
/* GPMC definitions for GPMC NAND */
#define SDP3430_NAND_GPMC_CONF1 0x00000800
#define SDP3430_NAND_GPMC_CONF2 0x00141400
#define SDP3430_NAND_GPMC_CONF3 0x00141400
#define SDP3430_NAND_GPMC_CONF4 0x0F010F01
#define SDP3430_NAND_GPMC_CONF5 0x010C1414
#define SDP3430_NAND_GPMC_CONF6 0x1F040A80
#endif /* _BOARD_SDP_H_ */

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/*
* (C) Copyright 2006-2009
* Texas Instruments Incorporated.
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <x0khasim@ti.com>
* Nishanth Menon <nm@ti.com>
*
* Configuration settings for the 3430 TI SDP3430 board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* TODO: REMOVE THE FOLLOWING
* Retained the following till size.h is removed in u-boot
*/
#include <asm/sizes.h>
/*
* High Level Configuration Options
*/
#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
/*
* NOTE: these #defines presume standard SDP jumper settings.
* In particular:
* - 26 MHz clock (not 19.2 or 38.4 MHz)
* - Boot from 128MB NOR, not NAND or OneNAND
*
* At this writing, OMAP3 U-Boot support doesn't permit concurrent
* support for all the flash types the board supports.
*/
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
/*
* Size of malloc() pool
* Total Size Environment - 256k
* Malloc - add 256k
*/
#define CONFIG_ENV_SIZE (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
/* initial data */
/*--------------------------------------------------------------------------*/
/*
* Hardware drivers
*/
/*
* TWL4030
*/
#define CONFIG_TWL4030_POWER 1
/*
* serial port - NS16550 compatible
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
* swapped with UART2 via jumpering. Downsides of using J8: it doesn't
* support UART boot (that's only for UART3); it prevents sharing a Linux
* kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
*
* UART boot uses UART3 on J9, and the SDP user's guide says to use
* that for console. Downsides of using J9: you can't use IRDA too;
* since UART3 isn't in the CORE power domain, it may be a bit less
* usable in certain PM-sensitive debug scenarios.
*/
#undef CONSOLE_J9 /* else J8/UART1 (innermost) */
#ifdef CONSOLE_J9
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3 /* UART3 */
#else
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
#define CONFIG_SERIAL1 1 /* UART1 */
#endif
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
/*
* I2C for power management setup
*/
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/* OMITTED: single 1 Gbit MT29F1G NAND flash */
/*
* NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
*/
#define CONFIG_SYS_FLASH_BASE 0x10000000
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_CFI_WIDTH 2
#define PHYS_FLASH_SIZE (128 << 20)
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
/* timeout values are in milliseconds */
#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10)
#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
/*--------------------------------------------------------------------------*/
/* commands to include */
#include <config_cmd_default.h>
/* Enabled commands */
#define CONFIG_CMD_DHCP /* DHCP Support */
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NET
/* Disabled commands */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMLS /* List all found images */
/*--------------------------------------------------------------------------*/
/*
* MMC boot support
*/
#if defined(CONFIG_CMD_MMC)
#define CONFIG_MMC 1
#define CONFIG_OMAP3_MMC 1
#define CONFIG_DOS_PARTITION 1
#endif
/*----------------------------------------------------------------------------
* SMSC9115 Ethernet from SMSC9118 family
*----------------------------------------------------------------------------
*/
#if defined(CONFIG_CMD_NET)
#define CONFIG_DRIVER_LAN91C96
#define CONFIG_LAN91C96_BASE DEBUG_BASE
#define CONFIG_LAN91C96_EXT_PHY
#define CONFIG_BOOTP_SEND_HOSTNAME
/*
* BOOTP fields
*/
#define CONFIG_BOOTP_SUBNETMASK 0x00000001
#define CONFIG_BOOTP_GATEWAY 0x00000002
#define CONFIG_BOOTP_HOSTNAME 0x00000004
#define CONFIG_BOOTP_BOOTPATH 0x00000010
#endif /* (CONFIG_CMD_NET) */
/*
* Environment setup
*
* Default boot order: mmc bootscript, MMC uImage, NOR image.
* Network booting environment must be configured at site.
*/
/* allow overwriting serial config and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"console=ttyS0,115200n8\0" \
"mmcargs=setenv bootargs console=${console} " \
"root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait\0" \
"norargs=setenv bootargs console=${console} " \
"root=/dev/mtdblock3 rw " \
"rootfstype=jffs2\0" \
"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from MMC/SD ...; " \
"autoscr ${loadaddr}\0" \
"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
"mmcboot=echo Booting from MMC/SD ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"norboot=echo Booting from NOR ...; " \
"run norargs; " \
"bootm 0x80000\0" \
#define CONFIG_BOOTCOMMAND \
"if mmcinit; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run norboot; " \
"fi; " \
"fi; " \
"else run norboot; fi"
#define CONFIG_AUTO_COMPLETE 1
/*--------------------------------------------------------------------------*/
/*
* Miscellaneous configurable options
*/
#define V_PROMPT "OMAP34XX SDP # "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT V_PROMPT
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
* a basic sanity check ONLY
* IF you would like to increase coverage, increase the end address
* or run the test with custom options
*/
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000)
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20))
/* Default load address */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
/*--------------------------------------------------------------------------*/
/*
* 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
* 32KHz clk, or from external sig. This rate is divided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
/*
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
#endif
/*
* SDRAM Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/* SDRAM Bank Allocation method */
#define SDRC_R_B_C 1
/*--------------------------------------------------------------------------*/
/*
* NOR FLASH usage ... default nCS0:
* - one 256KB sector for U-Boot
* - one 256KB sector for its parameters (not all used)
* - eight sectors (2 MB) for kernel
* - rest for JFFS2
*/
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
/*
* NAND FLASH usage ... default nCS1:
* - four 128KB sectors for X-Loader
* - four 128KB sectors for U-Boot
* - two 128KB sector for its parameters
* - 32 sectors (4 MB) for kernel
* - rest for filesystem
*/
/*
* OneNAND FLASH usage ... default nCS2:
* - four 128KB sectors for X-Loader
* - two 128KB sectors for U-Boot
* - one 128KB sector for its parameters
* - sixteen sectors (2 MB) for kernel
* - rest for filesystem
*/
/*--------------------------------------------------------------------------*/
#ifndef __ASSEMBLY__
extern struct gpmc *gpmc_cfg;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
extern unsigned int boot_flash_off;
extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif
#endif /* __CONFIG_H */