Patch by Sam Song, 09 Jun 2004:
- Add support for RPXlite_DW board - Update FLASH driver for 4*AM29DL323DB90VI - Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board
This commit is contained in:
wdenk
parent
36c728774e
commit
e63c8ee3dc
@ -2,6 +2,11 @@
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Changes since U-Boot 1.1.1:
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======================================================================
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* Patch by Sam Song, 09 Jun 2004:
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- Add support for RPXlite_DW board
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- Update FLASH driver for 4*AM29DL323DB90VI
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- Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board
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* Patch by Mark Jonas, 08 June 2004:
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- Make MPC5200 boards evaluate the SVR to print processor name and
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version in checkcpu() (cpu/mpc5xxx/cpu.c).
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4
CREDITS
4
CREDITS
@ -199,6 +199,10 @@ N: Yoo. Jonghoon
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E: yooth@ipone.co.kr
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D: Added port to the RPXlite board
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N: Sam Song
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E: samsongshu@yahoo.com.cn
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D: Port to the RPXlite_DW board
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N: Brad Kemp
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E: Brad.Kemp@seranoa.com
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D: Port to Windriver ppmc8260 board
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34
MAKEALL
34
MAKEALL
@ -33,23 +33,23 @@ LIST_5xxx=" \
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#########################################################################
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LIST_8xx=" \
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ADS860 ICU862_100MHz NETPHONE SPD823TS \
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AMX860 IP860 NETTA SXNI855T \
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AdderII IVML24 NETTA2 TOP860 \
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CCM IVML24_128 NETTA_ISDN TQM823L \
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ELPT860 IVML24_256 NETVIA TQM823L_LCD \
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ESTEEM192E IVMS8 NETVIA_V2 TQM850L \
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ETX094 IVMS8_128 NX823 TQM855L \
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FADS823 IVMS8_256 QS823 TQM860L \
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FADS850SAR KUP4K QS850 c2mon \
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FADS860T KUP4X QS860T cogent_mpc8xx \
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FLAGADM LANTEC R360MPI hermes \
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FPS850L MBX RBC823 lwmon \
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GEN860T MBX860T RPXClassic pcu_e \
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GEN860T_SC MHPC RPXlite rmu \
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GENIETV MPC86xADS RRvision svm_sc8xx \
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GTH MPC885ADS SM850 v37 \
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IAD210 MVS1
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AdderII GTH MHPC rmu \
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ADS860 hermes MPC86xADS RPXClassic \
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AMX860 IAD210 MPC885ADS RPXlite \
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c2mon ICU862_100MHz MVS1 RPXlite_DW \
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CCM IP860 NETPHONE RRvision \
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cogent_mpc8xx IVML24 NETTA SM850 \
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ELPT860 IVML24_128 NETTA2 SPD823TS \
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ESTEEM192E IVML24_256 NETTA_ISDN svm_sc8xx \
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ETX094 IVMS8 NETVIA SXNI855T \
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FADS823 IVMS8_128 NETVIA_V2 TOP860 \
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FADS850SAR IVMS8_256 NX823 TQM823L \
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FADS860T KUP4K pcu_e TQM823L_LCD \
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FLAGADM KUP4X QS823 TQM850L \
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FPS850L LANTEC QS850 TQM855L \
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GEN860T lwmon QS860T TQM860L \
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GEN860T_SC MBX R360MPI v37 \
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GENIETV MBX860T RBC823 \
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"
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#########################################################################
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24
Makefile
24
Makefile
@ -488,6 +488,30 @@ RPXClassic_config: unconfig
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RPXlite_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8xx RPXlite
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RPXlite_DW_64_config \
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RPXlite_DW_LCD_config \
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RPXlite_DW_64_LCD_config \
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RPXlite_DW_NVRAM_config \
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RPXlite_DW_NVRAM_64_config \
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RPXlite_DW_NVRAM_LCD_config \
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RPXlite_DW_NVRAM_64_LCD_config \
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RPXlite_DW_config: unconfig
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@ >include/config.h
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@[ -z "$(findstring _64,$@)" ] || \
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{ echo "#define RPXlite_64MHz" >>include/config.h ; \
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echo "... with 64MHz system clock ..."; \
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}
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@[ -z "$(findstring _LCD,$@)" ] || \
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{ echo "#define CONFIG_LCD" >>include/config.h ; \
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echo "#define CONFIG_NEC_NL6448BC20" >>include/config.h ; \
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echo "... with LCD display ..."; \
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}
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@[ -z "$(findstring _NVRAM,$@)" ] || \
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{ echo "#define CFG_ENV_IS_IN_NVRAM" >>include/config.h ; \
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echo "... with ENV in NVRAM ..."; \
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}
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@./mkconfig -a RPXlite_DW ppc mpc8xx RPXlite_dw
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rmu_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8xx rmu
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30
README
30
README
@ -2086,21 +2086,21 @@ configurations; the following names are supported:
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CANBT_config hermes_config QS850_config
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cmi_mpc5xx_config hymod_config QS860T_config
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cogent_common_config IP860_config RPXlite_config
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cogent_mpc8260_config IVML24_config RPXsuper_config
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cogent_mpc8xx_config IVMS8_config rsdproto_config
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CPCI405_config JSE_config Sandpoint8240_config
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CPCIISER4_config LANTEC_config sbc8260_config
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csb272_config lwmon_config SM850_config
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CU824_config MBX860T_config SPD823TS_config
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DUET_ADS_config MBX_config stxgp3_config
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EBONY_config MPC8260ADS_config SXNI855T_config
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ELPT860_config MPC8540ADS_config TQM823L_config
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ESTEEM192E_config MPC8560ADS_config TQM850L_config
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ETX094_config NETVIA_config TQM855L_config
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FADS823_config omap1510inn_config TQM860L_config
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FADS850SAR_config omap1610h2_config WALNUT405_config
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FADS860T_config omap1610inn_config ZPC1900_config
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FPS850L_config omap5912osk_config
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cogent_mpc8260_config IVML24_config RPXlite_DW_config
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cogent_mpc8xx_config IVMS8_config RPXsuper_config
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CPCI405_config JSE_config rsdproto_config
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CPCIISER4_config LANTEC_config Sandpoint8240_config
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csb272_config lwmon_config sbc8260_config
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CU824_config MBX860T_config SM850_config
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DUET_ADS_config MBX_config SPD823TS_config
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EBONY_config MPC8260ADS_config stxgp3_config
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ELPT860_config MPC8540ADS_config SXNI855T_config
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ESTEEM192E_config MPC8560ADS_config TQM823L_config
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ETX094_config NETVIA_config TQM850L_config
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FADS823_config omap1510inn_config TQM855L_config
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FADS850SAR_config omap1610h2_config TQM860L_config
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FADS860T_config omap1610inn_config WALNUT405_config
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FPS850L_config omap5912osk_config ZPC1900_config
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Note: for some board special configuration names may exist; check if
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additional information is available from the board vendor; for
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40
board/RPXlite_dw/Makefile
Normal file
40
board/RPXlite_dw/Makefile
Normal file
@ -0,0 +1,40 @@
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#
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o
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$(LIB): .depend $(OBJS)
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$(AR) crv $@ $(OBJS)
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend
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#########################################################################
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96
board/RPXlite_dw/README
Normal file
96
board/RPXlite_dw/README
Normal file
@ -0,0 +1,96 @@
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After following the step of Yoo. Jonghoon and Wolfgang Denk,
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I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW.
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There are three differences between the Yoo-ported RPXlite and the RPXlite_DW.
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Board(in U-BOOT) version(in EmbeddedPlanet) CPU SDRAM FLASH
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RPXlite RPXlite CW 850 16MB 4MB
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RPXlite_DW RPXlite DW 823e 64MB 16MB
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This fireware is specially coded for EmbeddedPlanet Co. Software Development
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Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel.
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It has the following three features:
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1. 64MHz/48MHz system frequence setting options.
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The default setting is 48MHz.To get a 64MHz u-boot,just add
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'64' in make command,like
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make RPXlite_DW_64_config
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make all
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2. CFG_ENV_IS_IN_FLASH/CFG_ENV_IS_IN_NVRAM
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The default environment parameter is stored in FLASH because it is a common choice for
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environment parameter.So I make NVRAM as backup parameter storeage.The reason why I
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didn't use EEPROM for ENV is that PlanetCore V2.0 use EEPROM as environment parameter
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home.Because of the possibility of using two firewares on this board,I didn't
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'disturb' EEPROM.To get NVRAM support,you may use the following build command:
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make RPXlite_DW_NVRAM_config
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make all
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3. LCD panel support
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To support the Platform better,I added LCD panel(NL6448BC20-08) function.But bewear of
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the fact that once you build this support and program it to FLASH,you should make sure
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you put workable kernel and ramdisk at the right place in FLASH or through NFS.
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Otherwise, you must erase this fireware manually via BDI2000 or ICE tools.So this
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function is used for deployment and demo only.Pls look before you leap.
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To get a LCD support u-boot,you can do the following:
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make RPXlite_DW_LCD_config
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make all
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The basic make commands could be:
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make RPXlite_DW_config
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make RPXlite_DW_64_config
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make RPXlite_DW_LCD_config
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make RPXlite_DW_NVRAM_config
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BTW,you can combine the above features together and get a workable u-boot to meet your need.
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For example,to get a 64MHZ && ENV_IS_IN_FLASH && LCD panel support u-boot,you can type:
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make RPXlite_DW_NVRAM_64_LCD_config
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make all
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So other combining make commands could be:
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make RPXlite_DW_NVRAM_64_config
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make RPXlite_DW_NVRAM_LCD_config
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make RPXlite_DW_64_LCD_config
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The boot process by "make RPXlite_DW_config" could be:
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U-Boot 1.1.1 (Jun 8 2004 - 11:16:30)
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CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache
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Board: RPXlite_DW
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DRAM: 64 MB
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FLASH: 16 MB
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*** Warning - bad CRC, using default environment
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In: serial
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Out: serial
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Err: serial
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Net: SCC ETHERNET
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u-boot>
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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I'd like to extend my heartfelt gratitute to kind people for helping me work it out.
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I would particually thank Wolfgang Denk for his nice help.
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Enjoy,
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Sam Song, samsongshu@yahoo.com.cn
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Institute of Electrical Machinery and Controls
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Shanghai University
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June 8,2004
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180
board/RPXlite_dw/RPXlite_dw.c
Normal file
180
board/RPXlite_dw/RPXlite_dw.c
Normal file
@ -0,0 +1,180 @@
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/*
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* (C) Copyright 2004
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* Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Sam Song
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* U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW
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* Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz
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* with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75.
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*/
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#include <common.h>
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#include <mpc8xx.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFCC25
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const uint sdram_table[] =
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{
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/*
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* Single Read. (Offset 00h in UPMA RAM)
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*/
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0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_,
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/*
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* Burst Read. (Offset 08h in UPMA RAM)
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*/
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0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
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0x01FFCC20, 0x1FF74C20, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18h in UPMA RAM)
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*/
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0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */
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_NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35,
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_NOT_USED_,
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/*
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* Burst Write. (Offset 20h in UPMA RAM)
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*/
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0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
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0x01FFFC24, 0x1FF74C25, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_,
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/*
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* Refresh. (Offset 30h in UPMA RAM)
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*/
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0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
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0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4,
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/* INIT sequence RAM WORDS
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* SDRAM Initialization (offset 0x36 in UPMA RAM)
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* The above definition uses the remaining space
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* to establish an initialization sequence,
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* which is executed by a RUN command.
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* The sequence is COMMAND INHIBIT(NOP),Precharge,
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* Load Mode Register,NOP,Auto Refresh.
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*/
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/*
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* Exception. (Offset 3Ch in UPMA RAM)
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*/
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0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
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};
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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puts ("Board: RPXlite_DW\n") ;
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return (0) ;
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size9;
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upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
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/* Refresh clock prescalar */
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memctl->memc_mptpr = CFG_MPTPR ;
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memctl->memc_mar = 0x00000088;
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/* Map controller banks 1 to the SDRAM bank */
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memctl->memc_or1 = CFG_OR1_PRELIM;
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memctl->memc_br1 = CFG_BR1_PRELIM;
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memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
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/*Disable Periodic timer A. */
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udelay(200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80002236; /* SDRAM bank 0 - refresh twice */
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udelay(1);
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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/*Enable Periodic timer A */
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udelay (1000);
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/* Check Bank 0 Memory Size
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* try 9 column mode
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*/
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size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
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/*
|
||||
* Final mapping:
|
||||
*/
|
||||
|
||||
memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
|
||||
|
||||
udelay (1000);
|
||||
|
||||
return (size9);
|
||||
}
|
||||
|
||||
void rpxlite_init (void)
|
||||
{
|
||||
/* Enable NVRAM */
|
||||
*((uchar *) BCSR0) |= BCSR0_ENNVRAM;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check memory range for valid RAM. A simple memory test determines
|
||||
* the actually available RAM size between addresses `base' and
|
||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
||||
* - short between address lines
|
||||
* - short between data lines
|
||||
*/
|
||||
static long int dram_size (long int mamr_value, long int *base,
|
||||
long int maxsize)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
|
||||
memctl->memc_mamr = mamr_value;
|
||||
|
||||
return (get_ram_size (base, maxsize));
|
||||
}
|
||||
29
board/RPXlite_dw/config.mk
Normal file
29
board/RPXlite_dw/config.mk
Normal file
@ -0,0 +1,29 @@
|
||||
#
|
||||
# (C) Copyright 2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
# Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# RPXlite dw boards : lite_dw
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xff000000
|
||||
490
board/RPXlite_dw/flash.c
Normal file
490
board/RPXlite_dw/flash.c
Normal file
@ -0,0 +1,490 @@
|
||||
/*
|
||||
* (C) Copyright 2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
|
||||
* U-Boot port on RPXlite board
|
||||
*
|
||||
* Some of flash control words are modified. (from 2x16bit device
|
||||
* to 4x8bit device)
|
||||
* RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
|
||||
* are not tested.
|
||||
*
|
||||
* (?) Does an RPXLite board which
|
||||
* does not use AM29LV800 flash memory exist ?
|
||||
* I don't know...
|
||||
*/
|
||||
|
||||
/* Yes,Yoo.They do use other FLASH for the board.
|
||||
*
|
||||
* Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
|
||||
* U-Boot port on RPXlite DW version board
|
||||
*
|
||||
* By now,it uses 4 AM29DL323DB90VI devices(4x8bit).
|
||||
* The total FLASH has 16MB(4x4MB).
|
||||
* I just made some necessary changes on the basis of Wolfgang and Yoo's job.
|
||||
*
|
||||
* June 8, 2004 */
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc8xx.h>
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions vu_long : volatile unsigned long IN include/common.h
|
||||
*/
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data);
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info);
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0 ;
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
|
||||
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
|
||||
|
||||
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
|
||||
/* If Monitor is in the cope of FLASH,then
|
||||
* protect this area by default in case for
|
||||
* other occupation. [SAM] */
|
||||
|
||||
/* monitor protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_MONITOR_BASE,
|
||||
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
flash_info[0].size = size_b0;
|
||||
return (size_b0);
|
||||
}
|
||||
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* set up sector start address table */
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00008000;
|
||||
info->start[2] = base + 0x00010000;
|
||||
info->start[3] = base + 0x00018000;
|
||||
info->start[4] = base + 0x00020000;
|
||||
info->start[5] = base + 0x00028000;
|
||||
info->start[6] = base + 0x00030000;
|
||||
info->start[7] = base + 0x00038000;
|
||||
|
||||
for (i = 8; i < info->sector_count; i++) {
|
||||
info->start[i] = base + ((i-7) * 0x00040000);
|
||||
}
|
||||
} else {
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = base + info->size - 0x00010000;
|
||||
info->start[i--] = base + info->size - 0x00018000;
|
||||
info->start[i--] = base + info->size - 0x00020000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = base + i * 0x00040000;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void flash_print_info (flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD: printf ("AMD "); break;
|
||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
|
||||
default: printf ("Unknown Vendor "); break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sector)\n");
|
||||
break;
|
||||
/* I just add the FLASH_AMDL323B for RPXlite_DW BOARD. [SAM] */
|
||||
default: printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
printf (" Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i=0; i<info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s",info->start[i],info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
|
||||
{
|
||||
short i;
|
||||
ulong value;
|
||||
ulong base = (ulong)addr;
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
addr[0xAAA] = 0x00AA00AA ;
|
||||
addr[0x555] = 0x00550055 ;
|
||||
addr[0xAAA] = 0x00900090 ;
|
||||
|
||||
value = addr[0] ;
|
||||
switch (value & 0x00FF00FF) {
|
||||
case AMD_MANUFACT: /* AMD_MANUFACT=0x00010001 in flash.h. */
|
||||
info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h.*/
|
||||
break;
|
||||
case FUJ_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_FUJ;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
value = addr[2] ; /* device ID */
|
||||
switch (value & 0x00FF00FF) {
|
||||
case (AMD_ID_LV400T & 0x00FF00FF):
|
||||
info->flash_id += FLASH_AM400T;
|
||||
info->sector_count = 11;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
case (AMD_ID_LV400B & 0x00FF00FF):
|
||||
info->flash_id += FLASH_AM400B;
|
||||
info->sector_count = 11;
|
||||
info->size = 0x00100000;
|
||||
break; /* => 1 MB */
|
||||
case (AMD_ID_LV800T & 0x00FF00FF):
|
||||
info->flash_id += FLASH_AM800T;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00200000;
|
||||
break; /* => 2 MB */
|
||||
case (AMD_ID_LV800B & 0x00FF00FF):
|
||||
info->flash_id += FLASH_AM800B;
|
||||
info->sector_count = 19;
|
||||
info->size = 0x00400000; /* Size doubled by yooth */
|
||||
break; /* => 4 MB */
|
||||
case (AMD_ID_LV160T & 0x00FF00FF):
|
||||
info->flash_id += FLASH_AM160T;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 4 MB */
|
||||
case (AMD_ID_LV160B & 0x00FF00FF):
|
||||
info->flash_id += FLASH_AM160B;
|
||||
info->sector_count = 35;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 4 MB */
|
||||
case (AMD_ID_DL323B & 0x00FF00FF):
|
||||
info->flash_id += FLASH_AMDL323B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x01000000;
|
||||
break; /* => 16 MB(4x4MB) */
|
||||
/* AMD_ID_DL323B= 0x22532253 FLASH_AMDL323B= 0x0013
|
||||
* AMD_ID_DL323B could be found in <flash.h>.[SAM]
|
||||
* So we could get : flash_id = 0x00000013.
|
||||
* The first four-bit represents VEDOR ID,leaving others for FLASH ID. */
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* => no or unknown flash */
|
||||
|
||||
}
|
||||
/* set up sector start address table */
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
/* FLASH_BTYPE=0x0001 mask for bottom boot sector type.If the last bit equals 1,
|
||||
* it means bottom boot flash. GOOD IDEA! [SAM]
|
||||
*/
|
||||
|
||||
/* set sector offsets for bottom boot block type */
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00008000;
|
||||
info->start[2] = base + 0x00010000;
|
||||
info->start[3] = base + 0x00018000;
|
||||
info->start[4] = base + 0x00020000;
|
||||
info->start[5] = base + 0x00028000;
|
||||
info->start[6] = base + 0x00030000;
|
||||
info->start[7] = base + 0x00038000;
|
||||
|
||||
for (i = 8; i < info->sector_count; i++) {
|
||||
info->start[i] = base + ((i-7) * 0x00040000) ;
|
||||
}
|
||||
} else {
|
||||
/* set sector offsets for top boot block type */
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = base + info->size - 0x00010000;
|
||||
info->start[i--] = base + info->size - 0x00018000;
|
||||
info->start[i--] = base + info->size - 0x00020000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = base + i * 0x00040000;
|
||||
}
|
||||
}
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
addr = (volatile unsigned long *)(info->start[i]);
|
||||
/* info->protect[i] = addr[4] & 1 ; */
|
||||
/* Mask it for disorder FLASH protection **[Sam]** */
|
||||
}
|
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH.
|
||||
*/
|
||||
if (info->flash_id != FLASH_UNKNOWN) {
|
||||
addr = (volatile unsigned long *)info->start[0];
|
||||
|
||||
*addr = 0xF0F0F0F0; /* reset bank */
|
||||
}
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
vu_long *addr = (vu_long*)(info->start[0]);
|
||||
int flag, prot, sect, l_sect;
|
||||
ulong start, now, last;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if ((info->flash_id == FLASH_UNKNOWN) ||
|
||||
(info->flash_id > FLASH_AMD_COMP)) {
|
||||
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
||||
info->flash_id);
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0xAAA] = 0xAAAAAAAA;
|
||||
addr[0x555] = 0x55555555;
|
||||
addr[0xAAA] = 0x80808080;
|
||||
addr[0xAAA] = 0xAAAAAAAA;
|
||||
addr[0x555] = 0x55555555;
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr = (vu_long *)(info->start[sect]) ;
|
||||
addr[0] = 0x30303030 ;
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
addr = (vu_long *)(info->start[l_sect]);
|
||||
while ((addr[0] & 0x80808080) != 0x80808080) {
|
||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
addr = (vu_long *)info->start[0];
|
||||
addr[0] = 0xF0F0F0F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<4 && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i=0; i<4; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
return (write_word(info, wp, data));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
vu_long *addr = (vu_long *)(info->start[0]);
|
||||
ulong start;
|
||||
int flag;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((vu_long *)dest) & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0xAAA] = 0xAAAAAAAA;
|
||||
addr[0x555] = 0x55555555;
|
||||
addr[0xAAA] = 0xA0A0A0A0;
|
||||
|
||||
*((vu_long *)dest) = data;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
139
board/RPXlite_dw/u-boot.lds
Normal file
139
board/RPXlite_dw/u-boot.lds
Normal file
@ -0,0 +1,139 @@
|
||||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mpc8xx/start.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_ppc/ppcstring.o (.text)
|
||||
lib_generic/vsprintf.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
/* XXX ?
|
||||
. = env_offset;
|
||||
*/
|
||||
common/environment.o(.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
135
board/RPXlite_dw/u-boot.lds.debug
Normal file
135
board/RPXlite_dw/u-boot.lds.debug
Normal file
@ -0,0 +1,135 @@
|
||||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mpc8xx/start.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/vsprintf.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
|
||||
. = env_offset;
|
||||
common/environment.o(.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
@ -240,6 +240,10 @@ void cpu_init_f (volatile immap_t * immr)
|
||||
rpxclassic_init ();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RPXLITE) && defined(CFG_ENV_IS_IN_NVRAM)
|
||||
rpxlite_init ();
|
||||
#endif
|
||||
|
||||
#ifdef CFG_RCCR /* must be done before cpm_load_patch() */
|
||||
/* write config value */
|
||||
immr->im_cpm.cp_rccr = CFG_RCCR;
|
||||
|
||||
@ -828,6 +828,11 @@ static void lcd_ctrl_init (void *lcdbase)
|
||||
* the controller.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_RPXLITE
|
||||
/* This is special for RPXlite_DW Software Development Platform **[Sam]** */
|
||||
panel_info.vl_dp = CFG_LOW;
|
||||
#endif
|
||||
|
||||
lccrtmp = LCDBIT (LCCR_BNUM_BIT,
|
||||
(((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));
|
||||
|
||||
|
||||
@ -272,6 +272,8 @@ extern ssize_t spi_write (uchar *, int, uchar *, int);
|
||||
void rpxclassic_init (void);
|
||||
#endif
|
||||
|
||||
void rpxlite_init (void);
|
||||
|
||||
#ifdef CONFIG_MBX
|
||||
/* $(BOARD)/mbx8xx.c */
|
||||
void mbx_init (void);
|
||||
|
||||
421
include/configs/RPXlite_DW.h
Normal file
421
include/configs/RPXlite_DW.h
Normal file
@ -0,0 +1,421 @@
|
||||
/*
|
||||
* (C) Copyright 2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
|
||||
* U-BOOT port on RPXlite board
|
||||
*/
|
||||
|
||||
/*
|
||||
* Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
|
||||
* U-BOOT port on RPXlite DW version board--RPXlite_DW
|
||||
* June 8 ,2004
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
/* #define DEBUG 1 */
|
||||
|
||||
#undef CONFIG_MPC860
|
||||
#define CONFIG_MPC823 1 /* This is a MPC823e CPU. */
|
||||
#define CONFIG_RPXLITE 1 /* RPXlite DW version board */
|
||||
|
||||
#ifdef CONFIG_LCD /* with LCD controller ? */
|
||||
#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
|
||||
#endif
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
#undef CONFIG_8xx_CONS_SMC2
|
||||
#undef CONFIG_8xx_CONS_NONE
|
||||
#define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */
|
||||
|
||||
#ifdef CONFIG_LCD
|
||||
#define CONFIG_BOOTDELAY 12 /* autoboot after 12 seconds */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#endif
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs console=ttyS0,9600 root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ramargs=setenv bootargs console=tty0 console=ttyS0,9600 " \
|
||||
"root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):$(netdev):off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm $(kernel_addr)\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
|
||||
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
|
||||
"gatewayip=172.16.115.254\0" \
|
||||
"netmask=255.255.255.0\0" \
|
||||
"kernel_addr=ff880000\0" \
|
||||
"ramdisk_addr=ff980000\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
#undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "u-boot>" /* Monitor Command Prompt */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0040000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CFG_IMMR 0xFA200000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
|
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_FLASH_BASE 0xFF000000
|
||||
|
||||
#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#else
|
||||
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
|
||||
#endif
|
||||
#define CFG_MONITOR_BASE 0xFF000000
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_NVRAM
|
||||
#define CFG_ENV_ADDR 0xFA000100
|
||||
#define CFG_ENV_SIZE 0x1000
|
||||
#else
|
||||
#define CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 32-bit 12-35
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
#else
|
||||
#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
||||
#endif /* We can get SYPCR: 0xFFFF0689. */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 32-bit 12-30
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
#define CFG_SIUMCR (SIUMCR_MLRC10) /* SIUMCR:0x00000800 */
|
||||
|
||||
/*---------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 16-bit 12-16
|
||||
*---------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
|
||||
/* TBSCR: 0x00C3 [SAM] */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 16-bit 12-18
|
||||
*-----------------------------------------------------------------------
|
||||
* [RTC enabled but not stopped on FRZ]
|
||||
*/
|
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 16-bit 12-23
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
* [Periodic timer enabled,Periodic timer interrupt disable. ]
|
||||
*/
|
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) /* PISCR:0x0083 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 32-bit 5-7
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*/
|
||||
/* up to 64 MHz we use a 1:2 clock */
|
||||
#if defined(RPXlite_64MHz)
|
||||
#define CFG_PLPRCR ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) /*PLPRCR: 0x00700000. */
|
||||
#else
|
||||
#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 5-3
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF00
|
||||
/* Up to 64MHz system clock, we use 1:2 SYSTEM/BUS ratio */
|
||||
#define CFG_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
|
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
|
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
|
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
|
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CFG_ATA_ALT_OFFSET 0x0100
|
||||
|
||||
#define CFG_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0 and OR0 (FLASH)
|
||||
*/
|
||||
#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base */
|
||||
#define CFG_PRELIM_OR_AM 0xFC000000 /* OR addr mask */
|
||||
|
||||
/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
|
||||
|
||||
/*
|
||||
* BR1 and OR1 (SDRAM)
|
||||
*
|
||||
*/
|
||||
#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
|
||||
#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB in system */
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||
#define CFG_OR_TIMING_SDRAM 0x00000E00
|
||||
#define CFG_OR_AM_SDRAM (-(SDRAM_MAX_SIZE & OR_AM_MSK))
|
||||
#define CFG_OR1_PRELIM ( CFG_OR_AM_SDRAM | CFG_OR_TIMING_SDRAM )
|
||||
#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||
|
||||
/* RPXlite mem setting */
|
||||
#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */
|
||||
#define CFG_OR3_PRELIM 0xFF7F8900
|
||||
#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
|
||||
#define CFG_OR4_PRELIM 0xFFFE0040
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*/
|
||||
/* periodic timer for refresh */
|
||||
#if defined(RPXlite_64MHz)
|
||||
#define CFG_MAMR_PTA 32
|
||||
#else
|
||||
#define CFG_MAMR_PTA 20
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Refresh clock Prescalar
|
||||
*/
|
||||
#define CFG_MPTPR MPTPR_PTP_DIV2
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 9 column SDRAM */
|
||||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10)
|
||||
/* CFG_MAMR_9COL:0x20904000 @ 64MHz */
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
|
||||
/* Configuration variable added by yooth. */
|
||||
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
|
||||
/*
|
||||
* BCSRx
|
||||
*
|
||||
* Board Status and Control Registers
|
||||
*
|
||||
*/
|
||||
#define BCSR0 0xFA400000
|
||||
#define BCSR1 0xFA400001
|
||||
#define BCSR2 0xFA400002
|
||||
#define BCSR3 0xFA400003
|
||||
|
||||
#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
|
||||
#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
|
||||
#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
|
||||
#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
|
||||
#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
|
||||
#define BCSR0_COLTEST 0x20
|
||||
#define BCSR0_ETHLPBK 0x40
|
||||
#define BCSR0_ETHEN 0x80
|
||||
|
||||
#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
|
||||
#define BCSR1_PCVCTL6 0x02
|
||||
#define BCSR1_PCVCTL5 0x04
|
||||
#define BCSR1_PCVCTL4 0x08
|
||||
#define BCSR1_IPB5SEL 0x10
|
||||
|
||||
#define BCSR1_SMC1CTS 0x40 /* Added by SAM. */
|
||||
#define BCSR1_SMC1TRS 0x80 /* Added by SAM. */
|
||||
|
||||
#define BCSR2_ENRTCIRQ 0x01 /* Added by SAM. */
|
||||
#define BCSR2_ENBRG1 0x04 /* Added by SAM. */
|
||||
|
||||
#define BCSR2_ENPA5HDR 0x08 /* USB Control */
|
||||
#define BCSR2_ENUSBCLK 0x10
|
||||
#define BCSR2_USBPWREN 0x20
|
||||
#define BCSR2_USBSPD 0x40
|
||||
#define BCSR2_USBSUSP 0x80
|
||||
|
||||
#define BCSR3_BWKAPWR 0x01 /* Changed by SAM. Backup battery situation */
|
||||
#define BCSR3_IRQRTC 0x02 /* Changed by SAM. NVRAM Battery */
|
||||
#define BCSR3_RDY_BSY 0x04 /* Changed by SAM. Flash Operation */
|
||||
#define BCSR3_MPLX_LIN 0x08 /* Changed by SAM. Linear or Multiplexed address Mode */
|
||||
|
||||
#define BCSR3_D27 0x10 /* Dip Switch settings */
|
||||
#define BCSR3_D26 0x20
|
||||
#define BCSR3_D25 0x40
|
||||
#define BCSR3_D24 0x80
|
||||
|
||||
/*
|
||||
* Environment setting
|
||||
*/
|
||||
#define CONFIG_ETHADDR 00:10:EC:00:37:5B
|
||||
#define CONFIG_IPADDR 172.16.115.7
|
||||
#define CONFIG_SERVERIP 172.16.115.6
|
||||
#define CONFIG_ROOTPATH /workspace/myfilesystem/target/
|
||||
#define CONFIG_BOOTFILE uImage.rpxusb
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user