ARM: at91: Remove hardware.h included in configs
As said in READRE.kconfig, include/configs/*.h will be removed after all options are switched to Kconfig. As the first step, remove the follow line from include/configs/*.h. #include <asm/hardware.h> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
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@ -6,6 +6,7 @@
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*/
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#include <common.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/arch/sama5_sfr.h>
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@ -6,6 +6,7 @@
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*/
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#include <common.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/arch/sama5_matrix.h>
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@ -13,6 +13,7 @@
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*/
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#include <common.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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#include <asm/arch/at91_rstc.h>
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@ -10,6 +10,7 @@
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#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <asm/hardware.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <mach/at91_pio.h>
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@ -10,8 +10,6 @@
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#ifndef __AT91_SAMA5_COMMON_H
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#define __AT91_SAMA5_COMMON_H
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#include <asm/hardware.h>
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#define CONFIG_SYS_TEXT_BASE 0x26f00000
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/* ARM asynchronous clock */
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@ -11,8 +11,6 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/hardware.h>
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#define CONFIG_SYS_TEXT_BASE 0x73f00000
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#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
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@ -52,7 +50,7 @@
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
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#define CONFIG_SYS_SDRAM_BASE 0x70000000
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#define CONFIG_SYS_SDRAM_SIZE 0x08000000
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#define CONFIG_SYS_INIT_SP_ADDR \
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@ -10,12 +10,6 @@
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#ifndef __AT91SAM9N12_CONFIG_H_
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#define __AT91SAM9N12_CONFIG_H_
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/*
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* SoC must be defined first, before hardware.h is included.
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* In this case SoC is defined in boards.cfg.
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*/
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#include <asm/hardware.h>
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#define CONFIG_SYS_TEXT_BASE 0x26f00000
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/* ARM asynchronous clock */
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@ -55,7 +49,7 @@
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* that address while providing maximum stack area below.
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*/
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# define CONFIG_SYS_INIT_SP_ADDR \
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(ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
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(0x00300000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
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/* DataFlash */
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#ifdef CONFIG_CMD_SF
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@ -9,8 +9,6 @@
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#ifndef __CONFIG_H__
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#define __CONFIG_H__
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#include <asm/hardware.h>
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#define CONFIG_SYS_TEXT_BASE 0x26f00000
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/* ARM asynchronous clock */
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@ -14,11 +14,14 @@
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#define CONFIG_SYS_USE_SERIALFLASH 1
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#define CONFIG_BOARD_LATE_INIT
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/* Timer */
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#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
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/*
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* Memory configurations
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x10000000
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#ifdef CONFIG_SPL_BUILD
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@ -45,8 +48,8 @@
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* Serial Driver
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*/
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_USART0
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#define CONFIG_USART_ID ATMEL_ID_USART0
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#define CONFIG_USART_BASE 0xf802c000
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#define CONFIG_USART_ID 6
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/*
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* Ethernet
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@ -14,12 +14,14 @@
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/* serial console */
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_UART0
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#define CONFIG_USART_ID ATMEL_ID_UART0
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#define CONFIG_USART_BASE 0xf801c000
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#define CONFIG_USART_ID 24
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x20000000
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#define CONFIG_SYS_TIMER_COUNTER 0xf804803c
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_INIT_SP_ADDR 0x210000
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#else
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@ -48,7 +50,7 @@
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_BASE 0x80000000
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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@ -16,7 +16,7 @@
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x20000000
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#ifdef CONFIG_SPL_BUILD
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* This needs to be defined for the OHCI code to work but it is defined as
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* ATMEL_ID_UHPHS in the CPU specific header files.
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*/
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#define ATMEL_ID_UHP ATMEL_ID_UHPHS
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#define ATMEL_ID_UHP 32
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/*
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* Specify the clock enable bit in the PMC_SCER register.
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*/
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#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
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#define ATMEL_PMC_UHP (1 << 6)
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x10000000
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#ifdef CONFIG_SPL_BUILD
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@ -39,7 +39,7 @@
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_BASE 0x60000000
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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@ -62,7 +62,7 @@
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#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
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#endif
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* This needs to be defined for the OHCI code to work but it is defined as
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* ATMEL_ID_UHPHS in the CPU specific header files.
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*/
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#define ATMEL_ID_UHP ATMEL_ID_UHPHS
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#define ATMEL_ID_UHP 32
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/*
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* Specify the clock enable bit in the PMC_SCER register.
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*/
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#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
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#define ATMEL_PMC_UHP (1 << 6)
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/* LCD */
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#define LCD_BPP LCD_COLOR16
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@ -52,7 +52,7 @@
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x20000000
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#ifdef CONFIG_SPL_BUILD
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@ -72,7 +72,7 @@
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_BASE 0x60000000
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x20000000
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#ifdef CONFIG_SPL_BUILD
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@ -36,7 +36,7 @@
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_BASE 0x80000000
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x20000000
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#ifdef CONFIG_SPL_BUILD
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@ -34,7 +34,7 @@
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_BASE 0x80000000
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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/* serial console */
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_USART3
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#define CONFIG_USART_ID ATMEL_ID_USART3
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#define CONFIG_USART_BASE 0xfc00c000
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#define CONFIG_USART_ID 30
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/* Timer */
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#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x4000000
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#define CONFIG_SYS_INIT_SP_ADDR \
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@ -55,7 +58,7 @@
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#ifdef CONFIG_CMD_MMC
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#define CONFIG_SUPPORT_EMMC_BOOT
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#define CONFIG_GENERIC_ATMEL_MCI
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#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1
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#define ATMEL_BASE_MMCI 0xfc000000
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#define CONFIG_SYS_MMC_CLK_OD 500000
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/* For generating MMC partitions */
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