powerpc/ppc4xx: Support gdsys multichannel iocon hardware
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Dirk Eibach
Stefan Roese
parent
869b550ea3
commit
e50e8968d9
@ -7,6 +7,7 @@
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#include <common.h>
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#include <command.h>
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#include <errno.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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@ -15,6 +16,15 @@
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#include <gdsys_fpga.h>
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#include "../common/osd.h"
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#include "../common/mclink.h"
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#include <i2c.h>
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#include <pca953x.h>
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#include <pca9698.h>
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#include <miiphy.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
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#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
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@ -31,11 +41,20 @@ enum {
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HWVER_100 = 0,
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HWVER_104 = 1,
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HWVER_110 = 2,
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HWVER_120 = 3,
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HWVER_200 = 4,
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HWVER_210 = 5,
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};
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enum {
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FPGA_HWVER_200 = 0,
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FPGA_HWVER_210 = 1,
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};
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enum {
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COMPRESSION_NONE = 0,
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COMPRESSION_TYPE1_DELTA,
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COMPRESSION_TYPE1_DELTA = 1,
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COMPRESSION_TYPE1_TYPE2_DELTA = 3,
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};
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enum {
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@ -51,10 +70,71 @@ enum {
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enum {
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RAM_DDR2_32 = 0,
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RAM_DDR3_32 = 1,
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};
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enum {
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MCFPGA_DONE = 1 << 0,
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MCFPGA_INIT_N = 1 << 1,
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MCFPGA_PROGRAM_N = 1 << 2,
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MCFPGA_UPDATE_ENABLE_N = 1 << 3,
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MCFPGA_RESET_N = 1 << 4,
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};
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enum {
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GPIO_MDC = 1 << 14,
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GPIO_MDIO = 1 << 15,
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};
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unsigned int mclink_fpgacount;
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struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
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static int setup_88e1518(const char *bus, unsigned char addr);
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static int verify_88e1518(const char *bus, unsigned char addr);
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int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
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{
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int res;
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switch (fpga) {
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case 0:
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out_le16(reg, data);
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break;
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default:
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res = mclink_send(fpga - 1, regoff, data);
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if (res < 0) {
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printf("mclink_send reg %02lx data %04x returned %d\n",
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regoff, data, res);
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return res;
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}
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break;
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}
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return 0;
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}
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int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
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{
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int res;
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switch (fpga) {
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case 0:
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*data = in_le16(reg);
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break;
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default:
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if (fpga > mclink_fpgacount)
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return -EINVAL;
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res = mclink_receive(fpga - 1, regoff, data);
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if (res < 0) {
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printf("mclink_receive reg %02lx returned %d\n",
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regoff, res);
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return res;
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}
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}
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return 0;
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}
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/*
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* Check Board Identity:
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*/
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@ -76,7 +156,7 @@ int checkboard(void)
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return 0;
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}
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static void print_fpga_info(void)
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static void print_fpga_info(unsigned int fpga)
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{
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u16 versions;
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u16 fpga_version;
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@ -90,13 +170,13 @@ static void print_fpga_info(void)
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unsigned feature_ramconfig;
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unsigned feature_carriers;
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unsigned feature_video_channels;
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int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
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FPGA_GET_REG(0, versions, &versions);
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FPGA_GET_REG(0, fpga_version, &fpga_version);
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FPGA_GET_REG(0, fpga_features, &fpga_features);
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unit_type = (versions & 0xf000) >> 12;
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hardware_version = versions & 0x000f;
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feature_compression = (fpga_features & 0xe000) >> 13;
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feature_osd = fpga_features & (1<<11);
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feature_audio = (fpga_features & 0x0600) >> 9;
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@ -105,6 +185,9 @@ static void print_fpga_info(void)
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feature_carriers = (fpga_features & 0x000c) >> 2;
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feature_video_channels = fpga_features & 0x0003;
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if (legacy)
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printf("legacy ");
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switch (unit_type) {
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case UNITTYPE_MAIN_USER:
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printf("Mainchannel");
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@ -119,27 +202,68 @@ static void print_fpga_info(void)
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break;
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}
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switch (hardware_version) {
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case HWVER_100:
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printf(" HW-Ver 1.00\n");
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break;
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if (unit_type == UNITTYPE_MAIN_USER) {
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if (legacy)
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hardware_version =
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(in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
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else
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hardware_version =
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(!!pca9698_get_value(0x20, 24) << 0)
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| (!!pca9698_get_value(0x20, 25) << 1)
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| (!!pca9698_get_value(0x20, 26) << 2)
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| (!!pca9698_get_value(0x20, 27) << 3);
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switch (hardware_version) {
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case HWVER_100:
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printf(" HW-Ver 1.00,");
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break;
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case HWVER_104:
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printf(" HW-Ver 1.04\n");
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break;
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case HWVER_104:
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printf(" HW-Ver 1.04,");
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break;
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case HWVER_110:
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printf(" HW-Ver 1.10\n");
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break;
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case HWVER_110:
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printf(" HW-Ver 1.10,");
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break;
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default:
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printf(" HW-Ver %d(not supported)\n",
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hardware_version);
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break;
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case HWVER_120:
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printf(" HW-Ver 1.20-1.21,");
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break;
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case HWVER_200:
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printf(" HW-Ver 2.00,");
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break;
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case HWVER_210:
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printf(" HW-Ver 2.10,");
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break;
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default:
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printf(" HW-Ver %d(not supported),",
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hardware_version);
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break;
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}
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}
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printf(" FPGA V %d.%02d, features:",
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fpga_version / 100, fpga_version % 100);
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if (unit_type == UNITTYPE_VIDEO_USER) {
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hardware_version = versions & 0x000f;
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switch (hardware_version) {
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case FPGA_HWVER_200:
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printf(" HW-Ver 2.00,");
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break;
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case FPGA_HWVER_210:
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printf(" HW-Ver 2.10,");
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break;
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default:
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printf(" HW-Ver %d(not supported),",
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hardware_version);
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break;
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}
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}
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printf(" FPGA V %d.%02d\n features:",
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fpga_version / 100, fpga_version % 100);
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switch (feature_compression) {
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@ -151,6 +275,10 @@ static void print_fpga_info(void)
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printf(" type1-deltacompression");
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break;
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case COMPRESSION_TYPE1_TYPE2_DELTA:
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printf(" type1-deltacompression, type2-inlinecompression");
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break;
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default:
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printf(" compression %d(not supported)", feature_compression);
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break;
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@ -197,6 +325,10 @@ static void print_fpga_info(void)
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printf(", RAM 32 bit DDR2");
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break;
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case RAM_DDR3_32:
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printf(", RAM 32 bit DDR3");
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break;
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default:
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printf(", RAM %d(not supported)", feature_ramconfig);
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break;
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@ -209,46 +341,117 @@ static void print_fpga_info(void)
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int last_stage_init(void)
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{
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print_fpga_info();
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int slaves;
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unsigned int k;
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unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
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int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
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return osd_probe(0);
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print_fpga_info(0);
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osd_probe(0);
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/* wait for FPGA done */
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for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
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unsigned int ctr = 0;
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if (i2c_probe(mclink_controllers[k]))
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continue;
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while (!(pca953x_get_val(mclink_controllers[k])
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& MCFPGA_DONE)) {
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udelay(100000);
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if (ctr++ > 5) {
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printf("no done for mclink_controller %d\n", k);
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break;
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}
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}
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}
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if (!legacy) {
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miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
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bb_miiphy_write);
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if (!verify_88e1518(bb_miiphy_buses[0].name, 0)) {
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printf("Fixup 88e1518 erratum on %s\n",
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bb_miiphy_buses[0].name);
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setup_88e1518(bb_miiphy_buses[0].name, 0);
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}
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}
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/* wait for slave-PLLs to be up and running */
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udelay(500000);
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mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
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slaves = mclink_probe();
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mclink_fpgacount = 0;
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if (slaves <= 0)
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return 0;
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mclink_fpgacount = slaves;
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for (k = 1; k <= slaves; ++k) {
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print_fpga_info(k);
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osd_probe(k);
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miiphy_register(bb_miiphy_buses[k].name,
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bb_miiphy_read, bb_miiphy_write);
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if (!verify_88e1518(bb_miiphy_buses[k].name, 0)) {
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printf("Fixup 88e1518 erratum on %s\n",
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bb_miiphy_buses[k].name);
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setup_88e1518(bb_miiphy_buses[k].name, 0);
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}
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}
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return 0;
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}
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/*
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* provide access to fpga gpios (for I2C bitbang)
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* (these may look all too simple but make iocon.h much more readable)
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*/
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void fpga_gpio_set(int pin)
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void fpga_gpio_set(unsigned int bus, int pin)
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{
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FPGA_SET_REG(0, gpio.set, pin);
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FPGA_SET_REG(bus, gpio.set, pin);
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}
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void fpga_gpio_clear(int pin)
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void fpga_gpio_clear(unsigned int bus, int pin)
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{
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FPGA_SET_REG(0, gpio.clear, pin);
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FPGA_SET_REG(bus, gpio.clear, pin);
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}
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int fpga_gpio_get(int pin)
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int fpga_gpio_get(unsigned int bus, int pin)
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{
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u16 val;
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FPGA_GET_REG(0, gpio.read, &val);
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FPGA_GET_REG(bus, gpio.read, &val);
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return val & pin;
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}
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void gd405ep_init(void)
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{
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unsigned int k;
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if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
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gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
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} else {
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pca9698_direction_output(0x20, 4, 1);
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}
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}
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void gd405ep_set_fpga_reset(unsigned state)
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{
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if (state) {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
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int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
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if (legacy) {
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if (state) {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
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} else {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
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}
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} else {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
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pca9698_set_value(0x20, 4, state ? 0 : 1);
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}
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}
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@ -263,5 +466,200 @@ void gd405ep_setup_hw(void)
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int gd405ep_get_fpga_done(unsigned fpga)
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{
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return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
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int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
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if (legacy)
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return in_le16((void *)LATCH2_BASE)
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& CONFIG_SYS_FPGA_DONE(fpga);
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else
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return pca9698_get_value(0x20, 20);
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}
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/*
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* FPGA MII bitbang implementation
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*/
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struct fpga_mii {
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unsigned fpga;
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int mdio;
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} fpga_mii[] = {
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{ 0, 1},
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{ 1, 1},
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{ 2, 1},
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{ 3, 1},
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};
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static int mii_dummy_init(struct bb_miiphy_bus *bus)
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{
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return 0;
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}
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static int mii_mdio_active(struct bb_miiphy_bus *bus)
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{
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struct fpga_mii *fpga_mii = bus->priv;
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if (fpga_mii->mdio)
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FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
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else
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FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
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return 0;
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}
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static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
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{
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struct fpga_mii *fpga_mii = bus->priv;
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FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
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return 0;
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}
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static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
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{
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struct fpga_mii *fpga_mii = bus->priv;
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if (v)
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FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
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else
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FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
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fpga_mii->mdio = v;
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return 0;
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}
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static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
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{
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u16 gpio;
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struct fpga_mii *fpga_mii = bus->priv;
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FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
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*v = ((gpio & GPIO_MDIO) != 0);
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return 0;
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}
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static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
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{
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struct fpga_mii *fpga_mii = bus->priv;
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if (v)
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FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
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else
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FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
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return 0;
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}
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static int mii_delay(struct bb_miiphy_bus *bus)
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{
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udelay(1);
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return 0;
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}
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struct bb_miiphy_bus bb_miiphy_buses[] = {
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{
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.name = "trans1",
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.init = mii_dummy_init,
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.mdio_active = mii_mdio_active,
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.mdio_tristate = mii_mdio_tristate,
|
||||
.set_mdio = mii_set_mdio,
|
||||
.get_mdio = mii_get_mdio,
|
||||
.set_mdc = mii_set_mdc,
|
||||
.delay = mii_delay,
|
||||
.priv = &fpga_mii[0],
|
||||
},
|
||||
{
|
||||
.name = "trans2",
|
||||
.init = mii_dummy_init,
|
||||
.mdio_active = mii_mdio_active,
|
||||
.mdio_tristate = mii_mdio_tristate,
|
||||
.set_mdio = mii_set_mdio,
|
||||
.get_mdio = mii_get_mdio,
|
||||
.set_mdc = mii_set_mdc,
|
||||
.delay = mii_delay,
|
||||
.priv = &fpga_mii[1],
|
||||
},
|
||||
{
|
||||
.name = "trans3",
|
||||
.init = mii_dummy_init,
|
||||
.mdio_active = mii_mdio_active,
|
||||
.mdio_tristate = mii_mdio_tristate,
|
||||
.set_mdio = mii_set_mdio,
|
||||
.get_mdio = mii_get_mdio,
|
||||
.set_mdc = mii_set_mdc,
|
||||
.delay = mii_delay,
|
||||
.priv = &fpga_mii[2],
|
||||
},
|
||||
{
|
||||
.name = "trans4",
|
||||
.init = mii_dummy_init,
|
||||
.mdio_active = mii_mdio_active,
|
||||
.mdio_tristate = mii_mdio_tristate,
|
||||
.set_mdio = mii_set_mdio,
|
||||
.get_mdio = mii_get_mdio,
|
||||
.set_mdc = mii_set_mdc,
|
||||
.delay = mii_delay,
|
||||
.priv = &fpga_mii[3],
|
||||
},
|
||||
};
|
||||
|
||||
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
|
||||
sizeof(bb_miiphy_buses[0]);
|
||||
|
||||
/*
|
||||
* Workaround for erratum mentioned in 88E1518 release notes
|
||||
*/
|
||||
|
||||
static int verify_88e1518(const char *bus, unsigned char addr)
|
||||
{
|
||||
u16 phy_id1, phy_id2;
|
||||
|
||||
if (miiphy_read(bus, addr, 2, &phy_id1) ||
|
||||
miiphy_read(bus, addr, 3, &phy_id2)) {
|
||||
printf("Error reading from the PHY addr=%02x\n", addr);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if ((phy_id1 != 0x0141) || ((phy_id2 & 0xfff0) != 0x0dd0))
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct regfix_88e1518 {
|
||||
u8 reg;
|
||||
u16 data;
|
||||
} regfix_88e1518[] = {
|
||||
{ 22, 0x00ff },
|
||||
{ 17, 0x214b },
|
||||
{ 16, 0x2144 },
|
||||
{ 17, 0x0c28 },
|
||||
{ 16, 0x2146 },
|
||||
{ 17, 0xb233 },
|
||||
{ 16, 0x214d },
|
||||
{ 17, 0xcc0c },
|
||||
{ 16, 0x2159 },
|
||||
{ 22, 0x00fb },
|
||||
{ 7, 0xc00d },
|
||||
{ 22, 0x0000 },
|
||||
};
|
||||
|
||||
static int setup_88e1518(const char *bus, unsigned char addr)
|
||||
{
|
||||
unsigned int k;
|
||||
|
||||
for (k = 0; k < ARRAY_SIZE(regfix_88e1518); ++k) {
|
||||
if (miiphy_write(bus, addr,
|
||||
regfix_88e1518[k].reg,
|
||||
regfix_88e1518[k].data)) {
|
||||
printf("Error writing to the PHY addr=%02x\n", addr);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -17,7 +17,7 @@ COBJS-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
|
||||
|
||||
COBJS-$(CONFIG_IO) += miiphybb.o
|
||||
COBJS-$(CONFIG_IO64) += miiphybb.o
|
||||
COBJS-$(CONFIG_IOCON) += osd.o
|
||||
COBJS-$(CONFIG_IOCON) += osd.o mclink.o
|
||||
COBJS-$(CONFIG_DLVISION_10G) += osd.o
|
||||
COBJS-$(CONFIG_CONTROLCENTERD) += dp501.o
|
||||
|
||||
|
||||
@ -6,8 +6,8 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <i2c.h>
|
||||
#include <malloc.h>
|
||||
|
||||
#include <gdsys_fpga.h>
|
||||
|
||||
@ -51,6 +51,12 @@ enum {
|
||||
CH7301_DSP = 0x56, /* DVI Sync polarity Register */
|
||||
};
|
||||
|
||||
unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
|
||||
|
||||
#ifdef CONFIG_SYS_CH7301
|
||||
int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
|
||||
static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
|
||||
{
|
||||
@ -270,7 +276,7 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
unsigned screen;
|
||||
|
||||
for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
|
||||
for (screen = 0; screen <= max_osd_screen; ++screen) {
|
||||
unsigned x;
|
||||
unsigned y;
|
||||
unsigned charcount;
|
||||
@ -311,6 +317,9 @@ int osd_probe(unsigned screen)
|
||||
unsigned width;
|
||||
unsigned height;
|
||||
u8 value;
|
||||
#ifdef CONFIG_SYS_CH7301
|
||||
int old_bus = i2c_get_bus_num();
|
||||
#endif
|
||||
|
||||
FPGA_GET_REG(0, osd.version, &version);
|
||||
FPGA_GET_REG(0, osd.features, &features);
|
||||
@ -322,9 +331,11 @@ int osd_probe(unsigned screen)
|
||||
screen, version/100, version%100, width, height);
|
||||
|
||||
#ifdef CONFIG_SYS_CH7301
|
||||
i2c_set_bus_num(ch7301_i2c[screen]);
|
||||
value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
|
||||
if (value != 0x17) {
|
||||
printf(" Probing CH7301 failed, DID %02x\n", value);
|
||||
i2c_set_bus_num(old_bus);
|
||||
return -1;
|
||||
}
|
||||
i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
|
||||
@ -332,6 +343,7 @@ int osd_probe(unsigned screen)
|
||||
i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
|
||||
i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
|
||||
i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
|
||||
i2c_set_bus_num(old_bus);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_MPC92469AC
|
||||
@ -368,6 +380,8 @@ int osd_probe(unsigned screen)
|
||||
FPGA_SET_REG(screen, osd.x_pos, 0x007f);
|
||||
FPGA_SET_REG(screen, osd.y_pos, 0x005f);
|
||||
|
||||
if (screen > max_osd_screen)
|
||||
max_osd_screen = screen;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -376,7 +390,7 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
unsigned screen;
|
||||
|
||||
for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
|
||||
for (screen = 0; screen <= max_osd_screen; ++screen) {
|
||||
unsigned x;
|
||||
unsigned y;
|
||||
unsigned k;
|
||||
|
||||
@ -63,6 +63,7 @@
|
||||
* Commands additional to the ones defined in amcc-common.h
|
||||
*/
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_FPGAD
|
||||
#undef CONFIG_CMD_EEPROM
|
||||
|
||||
/*
|
||||
@ -100,23 +101,53 @@
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
|
||||
|
||||
#define CONFIG_SYS_I2C_SPEED 400000
|
||||
|
||||
#define CONFIG_PCA953X /* NXP PCA9554 */
|
||||
#define CONFIG_PCA9698 /* NXP PCA9698 */
|
||||
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_SOFT
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
|
||||
#define I2C_SOFT_DECLARATIONS2
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
|
||||
#define I2C_SOFT_DECLARATIONS3
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
|
||||
#define I2C_SOFT_DECLARATIONS4
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
|
||||
|
||||
#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
void fpga_gpio_set(int pin);
|
||||
void fpga_gpio_clear(int pin);
|
||||
int fpga_gpio_get(int pin);
|
||||
void fpga_gpio_set(unsigned int bus, int pin);
|
||||
void fpga_gpio_clear(unsigned int bus, int pin);
|
||||
int fpga_gpio_get(unsigned int bus, int pin);
|
||||
#endif
|
||||
|
||||
#define I2C_ACTIVE { }
|
||||
#define I2C_TRISTATE { }
|
||||
#define I2C_READ fpga_gpio_get(0x0040) ? 1 : 0
|
||||
#define I2C_SDA(bit) if (bit) fpga_gpio_set(0x0040); \
|
||||
else fpga_gpio_clear(0x0040)
|
||||
#define I2C_SCL(bit) if (bit) fpga_gpio_set(0x0020); \
|
||||
else fpga_gpio_clear(0x0020)
|
||||
#define I2C_READ \
|
||||
(fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
|
||||
#define I2C_SDA(bit) \
|
||||
do { \
|
||||
if (bit) \
|
||||
fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
|
||||
else \
|
||||
fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
|
||||
} while (0)
|
||||
#define I2C_SCL(bit) \
|
||||
do { \
|
||||
if (bit) \
|
||||
fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
|
||||
else \
|
||||
fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
|
||||
} while (0)
|
||||
#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
|
||||
|
||||
/*
|
||||
@ -236,10 +267,10 @@ int fpga_gpio_get(int pin);
|
||||
|
||||
#define CONFIG_SYS_FPGA_COUNT 1
|
||||
|
||||
#define CONFIG_SYS_FPGA_PTR \
|
||||
{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
|
||||
#define CONFIG_SYS_MCLINK_MAX 3
|
||||
|
||||
#define CONFIG_SYS_FPGA_COMMON
|
||||
#define CONFIG_SYS_FPGA_PTR \
|
||||
{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
|
||||
|
||||
/* Memory Bank 3 (Latches) initialization */
|
||||
#define CONFIG_SYS_LATCH_BASE 0x7f200000
|
||||
@ -256,6 +287,9 @@ int fpga_gpio_get(int pin);
|
||||
*/
|
||||
#define CONFIG_SYS_MPC92469AC
|
||||
#define CONFIG_SYS_CH7301
|
||||
#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
|
||||
#define CONFIG_SYS_OSD_SCREENS 1
|
||||
|
||||
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
@ -123,10 +123,21 @@ struct ihs_fpga {
|
||||
u16 mpc3w_control; /* 0x001a */
|
||||
u16 reserved_1[19]; /* 0x001c */
|
||||
u16 videocontrol; /* 0x0042 */
|
||||
u16 reserved_2[93]; /* 0x0044 */
|
||||
u16 reserved_2[14]; /* 0x0044 */
|
||||
u16 mc_int; /* 0x0060 */
|
||||
u16 mc_int_en; /* 0x0062 */
|
||||
u16 mc_status; /* 0x0064 */
|
||||
u16 mc_control; /* 0x0066 */
|
||||
u16 mc_tx_data; /* 0x0068 */
|
||||
u16 mc_tx_address; /* 0x006a */
|
||||
u16 mc_tx_cmd; /* 0x006c */
|
||||
u16 mc_res; /* 0x006e */
|
||||
u16 mc_rx_cmd_status; /* 0x0070 */
|
||||
u16 mc_rx_data; /* 0x0072 */
|
||||
u16 reserved_3[69]; /* 0x0074 */
|
||||
u16 reflection_high; /* 0x00fe */
|
||||
struct ihs_osd osd; /* 0x0100 */
|
||||
u16 reserved_3[889]; /* 0x010e */
|
||||
u16 reserved_4[889]; /* 0x010e */
|
||||
u16 videomem[31736]; /* 0x0800 */
|
||||
};
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user