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armv8/fsl-lsch2: fix sdhc clock frequency value

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The eSDHC could select to use platform clock or peripheral clock to
generate SD clock. The default selection is platform clock. So, fix
the clock frequency value that's calculated for eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Yangbo Lu 2016-02-16 10:54:41 +08:00 committed by York Sun
parent 0f4b82a555
commit e477f4bdd4
1 changed files with 4 additions and 0 deletions
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4
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
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@ -106,9 +106,13 @@ void get_sys_info(struct sys_info *sys_info)
#define HWA_CGA_M2_CLK_SEL 0x00000007
#define HWA_CGA_M2_CLK_SHIFT 0
#ifdef CONFIG_FSL_ESDHC
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
rcw_tmp = in_be32(&gur->rcwsr[15]);
rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
#else
sys_info->freq_sdhc = sys_info->freq_systembus;
#endif
#endif
#if defined(CONFIG_FSL_IFC)