arm: ls1021a: improve the core frequency to 1.2GHZ
Change core clock to 1.2GHz in the configurations for SD and NAND boot. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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@ -1,7 +1,7 @@
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#PBL preamble and RCW header
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aa55aa55 01ee0100
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# serdes protocol
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0608000a 00000000 00000000 00000000
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0608000c 00000000 00000000 00000000
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60000000 00407900 e0106a00 21046000
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00000000 00000000 00000000 00038000
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00000000 001b7200 00000000 00000000
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@ -2,13 +2,13 @@
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aa55aa55 01ee0100
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#enable IFC, disable QSPI and DSPI
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0608000a 00000000 00000000 00000000
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0608000c 00000000 00000000 00000000
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60000000 00407900 60040a00 21046000
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00000000 00000000 00000000 00038000
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00000000 001b7200 00000000 00000000
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#disable IFC, enable QSPI and DSPI
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#0608000a 00000000 00000000 00000000
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#0608000c 00000000 00000000 00000000
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#60000000 00407900 60040a00 21046000
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#00000000 00000000 00000000 00038000
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#20024800 001b7200 00000000 00000000
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@ -2,13 +2,13 @@
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aa55aa55 01ee0100
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#enable IFC, disable QSPI and DSPI
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#0608000a 00000000 00000000 00000000
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#0608000c 00000000 00000000 00000000
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#60000000 00407900 60040a00 21046000
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#00000000 00000000 00000000 00038000
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#00000000 001b7200 00000000 00000000
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#disable IFC, enable QSPI and DSPI
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0608000a 00000000 00000000 00000000
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0608000c 00000000 00000000 00000000
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60000000 00407900 60040a00 21046000
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00000000 00000000 00000000 00038000
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20024800 001b7200 00000000 00000000
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@ -2,7 +2,7 @@
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aa55aa55 01ee0100
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#enable IFC, disable QSPI and DSPI
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0608000a 00000000 00000000 00000000
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0608000c 00000000 00000000 00000000
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30000000 00007900 60040a00 21046000
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00000000 00000000 00000000 20000000
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00080000 881b7340 00000000 00000000
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@ -2,7 +2,7 @@
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aa55aa55 01ee0100
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#disable IFC, enable QSPI and DSPI
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0608000a 00000000 00000000 00000000
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0608000c 00000000 00000000 00000000
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30000000 00007900 60040a00 21046000
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00000000 00000000 00000000 20000000
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20024800 881b7340 00000000 00000000
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