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ppc4xx: Fix 460EX/GT PCIe port initialization

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This patch fixes a bug where the 460EX/GT PCIe UTLSET1 register was
configured incorrectly. Thanks to Olga Buchonina from AMCC for pointing
this out.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2008-07-01 17:03:19 +02:00
parent 745d8a0d3c
commit dd1c5523d6
1 changed files with 5 additions and 7 deletions
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12
cpu/ppc4xx/4xx_pcie.c
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@ -615,22 +615,20 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
int __ppc4xx_init_pcie_port_hw(int port, int rootport)
{
u32 val = 1 << 24;
u32 val;
u32 utlset1;
if (rootport) {
if (rootport)
val = PTYPE_ROOT_PORT << 20;
utlset1 = 0x21222222;
} else {
else
val = PTYPE_LEGACY_ENDPOINT << 20;
utlset1 = 0x20222222;
}
if (port == 0) {
val |= LNKW_X1 << 12;
utlset1 = 0x20000000;
} else {
val |= LNKW_X4 << 12;
utlset1 |= 0x00101101;
utlset1 = 0x20101101;
}
SDR_WRITE(SDRN_PESDR_DLPSET(port), val);