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Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze

Browse Source
This commit is contained in:
Tom Rini 2015-12-07 08:13:02 -05:00
commit dcf4cb068e
37 changed files with 286 additions and 328 deletions
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4
arch/arm/Kconfig
View File

@ -551,7 +551,9 @@ config ARCH_ZYNQ
select OF_CONTROL
select SPL_OF_CONTROL
select DM
select DM_ETH
select SPL_DM
select DM_MMC
select DM_SPI
select DM_SERIAL
select DM_SPI_FLASH
@ -562,6 +564,8 @@ config ARCH_ZYNQMP
select ARM64
select DM
select OF_CONTROL
select DM_ETH
select DM_MMC
select DM_SERIAL
config TEGRA

3
arch/arm/dts/zynq-zc702.dts
View File

@ -18,6 +18,7 @@
i2c0 = &i2c0;
serial0 = &uart1;
spi0 = &qspi;
mmc0 = &sdhci0;
};
memory {
@ -370,6 +371,7 @@
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
@ -383,6 +385,7 @@
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};

6
arch/arm/include/asm/arch-zynqmp/hardware.h
View File

@ -8,9 +8,6 @@
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
#define ZYNQ_SERIAL_BASEADDR0 0xFF000000
#define ZYNQ_SERIAL_BASEADDR1 0xFF001000
#define ZYNQ_GEM_BASEADDR0 0xFF0B0000
#define ZYNQ_GEM_BASEADDR1 0xFF0C0000
#define ZYNQ_GEM_BASEADDR2 0xFF0D0000
@ -22,9 +19,6 @@
#define ZYNQ_I2C_BASEADDR0 0xFF020000
#define ZYNQ_I2C_BASEADDR1 0xFF030000
#define ZYNQ_SDHCI_BASEADDR0 0xFF160000
#define ZYNQ_SDHCI_BASEADDR1 0xFF170000
#define ZYNQMP_SATA_BASEADDR 0xFD0C0000
#define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000

1
arch/arm/include/asm/arch-zynqmp/sys_proto.h
View File

@ -13,7 +13,6 @@ static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
{
}
int zynq_sdhci_init(phys_addr_t regbase);
int zynq_slcr_get_mio_pin_status(const char *periph);
unsigned int zynqmp_get_silicon_version(void);

4
arch/arm/mach-zynq/include/mach/hardware.h
View File

@ -7,15 +7,11 @@
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
#define ZYNQ_SERIAL_BASEADDR0 0xE0000000
#define ZYNQ_SERIAL_BASEADDR1 0xE0001000
#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
#define ZYNQ_SCU_BASEADDR 0xF8F00000
#define ZYNQ_GEM_BASEADDR0 0xE000B000
#define ZYNQ_GEM_BASEADDR1 0xE000C000
#define ZYNQ_SDHCI_BASEADDR0 0xE0100000
#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
#define ZYNQ_I2C_BASEADDR0 0xE0004000
#define ZYNQ_I2C_BASEADDR1 0xE0005000
#define ZYNQ_SPI_BASEADDR0 0xE0006000

3
arch/arm/mach-zynq/include/mach/sys_proto.h
View File

@ -20,9 +20,6 @@ extern void zynq_ddrc_init(void);
extern unsigned int zynq_get_silicon_version(void);
/* Driver extern functions */
extern int zynq_sdhci_init(phys_addr_t regbase);
extern int zynq_sdhci_of_init(const void *blob);
extern void ps7_init(void);
#endif /* _SYS_PROTO_H_ */

30
board/xilinx/zynq/board.c
View File

@ -118,40 +118,10 @@ int board_eth_init(bd_t *bis)
# endif
ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
txpp, rxpp);
#endif
#if defined(CONFIG_ZYNQ_GEM)
# if defined(CONFIG_ZYNQ_GEM0)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
CONFIG_ZYNQ_GEM_PHY_ADDR0,
CONFIG_ZYNQ_GEM_EMIO0);
# endif
# if defined(CONFIG_ZYNQ_GEM1)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
CONFIG_ZYNQ_GEM_PHY_ADDR1,
CONFIG_ZYNQ_GEM_EMIO1);
# endif
#endif
return ret;
}
#ifdef CONFIG_CMD_MMC
int board_mmc_init(bd_t *bd)
{
int ret = 0;
#if defined(CONFIG_ZYNQ_SDHCI)
# if defined(CONFIG_ZYNQ_SDHCI0)
ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
# endif
# if defined(CONFIG_ZYNQ_SDHCI1)
ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
# endif
#endif
return ret;
}
#endif
int dram_init(void)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)

47
board/xilinx/zynqmp/zynqmp.c
View File

@ -65,53 +65,6 @@ void scsi_init(void)
}
#endif
int board_eth_init(bd_t *bis)
{
u32 ret = 0;
#if defined(CONFIG_ZYNQ_GEM)
# if defined(CONFIG_ZYNQ_GEM0)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
# endif
# if defined(CONFIG_ZYNQ_GEM1)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
# endif
# if defined(CONFIG_ZYNQ_GEM2)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2,
CONFIG_ZYNQ_GEM_PHY_ADDR2, 0);
# endif
# if defined(CONFIG_ZYNQ_GEM3)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3,
CONFIG_ZYNQ_GEM_PHY_ADDR3, 0);
# endif
#endif
return ret;
}
#ifdef CONFIG_CMD_MMC
int board_mmc_init(bd_t *bd)
{
int ret = 0;
u32 ver = zynqmp_get_silicon_version();
if (ver != ZYNQMP_CSU_VERSION_VELOCE) {
#if defined(CONFIG_ZYNQ_SDHCI)
# if defined(CONFIG_ZYNQ_SDHCI0)
ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
# endif
# if defined(CONFIG_ZYNQ_SDHCI1)
ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
# endif
#endif
}
return ret;
}
#endif
int board_late_init(void)
{
u32 reg = 0;

16
common/cmd_i2c.c
View File

@ -1944,11 +1944,15 @@ static cmd_tbl_t cmd_i2c_sub[] = {
U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
};
#ifdef CONFIG_NEEDS_MANUAL_RELOC
void i2c_reloc(void) {
fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
static __maybe_unused void i2c_reloc(void)
{
static int relocated;
if (!relocated) {
fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
relocated = 1;
};
}
#endif
/**
* do_i2c() - Handle the "i2c" command-line command
@ -1964,6 +1968,10 @@ static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
cmd_tbl_t *c;
#ifdef CONFIG_NEEDS_MANUAL_RELOC
i2c_reloc();
#endif
if (argc < 2)
return CMD_RET_USAGE;

3
configs/xilinx_zynqmp_ep_defconfig
View File

@ -3,6 +3,8 @@ CONFIG_ARCH_ZYNQMP=y
CONFIG_ZYNQMP_USB=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
@ -22,4 +24,5 @@ CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ZYNQ_GEM=y
# CONFIG_REGEX is not set

2
configs/zynq_microzed_defconfig
View File

@ -15,4 +15,6 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_QSPI=y

2
configs/zynq_picozed_defconfig
View File

@ -8,3 +8,5 @@ CONFIG_SPL=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_PHYLIB=y
CONFIG_ZYNQ_GEM=y

6
configs/zynq_zc702_defconfig
View File

@ -14,4 +14,10 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_ZYNQ_QSPI=y

2
configs/zynq_zc706_defconfig
View File

@ -15,4 +15,6 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_QSPI=y

2
configs/zynq_zc770_xm010_defconfig
View File

@ -17,5 +17,7 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQ_QSPI=y

2
configs/zynq_zc770_xm011_defconfig
View File

@ -12,3 +12,5 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_PHYLIB=y
CONFIG_ZYNQ_GEM=y

2
configs/zynq_zc770_xm012_defconfig
View File

@ -10,3 +10,5 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_PHYLIB=y
CONFIG_ZYNQ_GEM=y

2
configs/zynq_zc770_xm013_defconfig
View File

@ -12,3 +12,5 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_PHYLIB=y
CONFIG_ZYNQ_GEM=y

2
configs/zynq_zed_defconfig
View File

@ -15,4 +15,6 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHYLIB=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_QSPI=y

2
configs/zynq_zybo_defconfig
View File

@ -11,6 +11,8 @@ CONFIG_FIT_SIGNATURE=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_PHYLIB=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000

2
drivers/core/Kconfig
View File

@ -134,7 +134,7 @@ config SIMPLE_BUS
config SPL_SIMPLE_BUS
bool "Support simple-bus driver in SPL"
depends on SPL_DM && SPL_OF_CONTROL
default n
default y
help
Supports the 'simple-bus' driver, which is used on some systems
in SPL.

63
drivers/mmc/zynq_sdhci.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2013 Inc.
* (C) Copyright 2013 - 2015 Xilinx, Inc.
*
* Xilinx Zynq SD Host Controller Interface
*
@ -7,55 +7,48 @@
*/
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <malloc.h>
#include <sdhci.h>
#include <asm/arch/sys_proto.h>
int zynq_sdhci_init(phys_addr_t regbase)
static int arasan_sdhci_probe(struct udevice *dev)
{
struct sdhci_host *host = NULL;
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
if (!host) {
printf("zynq_sdhci_init: sdhci_host malloc fail\n");
return 1;
}
host->name = "zynq_sdhci";
host->ioaddr = (void *)regbase;
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
SDHCI_QUIRK_BROKEN_R1B;
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, 52000000 >> 9);
add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, 0);
upriv->mmc = host->mmc;
return 0;
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
int zynq_sdhci_of_init(const void *blob)
static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
{
int offset = 0;
u32 ret = 0;
phys_addr_t reg;
struct sdhci_host *host = dev_get_priv(dev);
debug("ZYNQ SDHCI: Initialization\n");
host->name = (char *)dev->name;
host->ioaddr = (void *)dev_get_addr(dev);
do {
offset = fdt_node_offset_by_compatible(blob, offset,
"arasan,sdhci-8.9a");
if (offset != -1) {
reg = fdtdec_get_addr(blob, offset, "reg");
if (reg != FDT_ADDR_T_NONE) {
ret |= zynq_sdhci_init(reg);
} else {
debug("ZYNQ SDHCI: Can't get base address\n");
return -1;
}
}
} while (offset != -1);
return ret;
return 0;
}
#endif
static const struct udevice_id arasan_sdhci_ids[] = {
{ .compatible = "arasan,sdhci-8.9a" },
{ }
};
U_BOOT_DRIVER(arasan_sdhci_drv) = {
.name = "arasan_sdhci",
.id = UCLASS_MMC,
.of_match = arasan_sdhci_ids,
.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
.probe = arasan_sdhci_probe,
.priv_auto_alloc_size = sizeof(struct sdhci_host),
};

6
drivers/net/Kconfig
View File

@ -101,4 +101,10 @@ config PCH_GBE
This MAC is present in Intel Platform Controller Hub EG20T. It
supports 10/100/1000 Mbps operation.
config ZYNQ_GEM
depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP)
bool "Xilinx Ethernet GEM"
help
This MAC is presetn in Xilinx Zynq and ZynqMP SoCs.
endif # NETDEVICES

320
drivers/net/zynq_gem.c
View File

@ -10,11 +10,11 @@
*/
#include <common.h>
#include <dm.h>
#include <net.h>
#include <netdev.h>
#include <config.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <console.h>
#include <malloc.h>
#include <asm/io.h>
#include <phy.h>
@ -25,6 +25,8 @@
#include <asm/arch/sys_proto.h>
#include <asm-generic/errno.h>
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CONFIG_PHYLIB)
# error XILINX_GEM_ETHERNET requires PHYLIB
#endif
@ -167,14 +169,14 @@ struct zynq_gem_priv {
int phyaddr;
u32 emio;
int init;
struct zynq_gem_regs *iobase;
phy_interface_t interface;
struct phy_device *phydev;
struct mii_dev *bus;
};
static inline int mdio_wait(struct eth_device *dev)
static inline int mdio_wait(struct zynq_gem_regs *regs)
{
struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
u32 timeout = 20000;
/* Wait till MDIO interface is ready to accept a new transaction. */
@ -192,13 +194,13 @@ static inline int mdio_wait(struct eth_device *dev)
return 0;
}
static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
u32 op, u16 *data)
static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
u32 op, u16 *data)
{
u32 mgtcr;
struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
struct zynq_gem_regs *regs = priv->iobase;
if (mdio_wait(dev))
if (mdio_wait(regs))
return 1;
/* Construct mgtcr mask for the operation */
@ -209,7 +211,7 @@ static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
/* Write mgtcr and wait for completion */
writel(mgtcr, &regs->phymntnc);
if (mdio_wait(dev))
if (mdio_wait(regs))
return 1;
if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
@ -218,12 +220,13 @@ static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
return 0;
}
static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
u32 regnum, u16 *val)
{
u32 ret;
ret = phy_setup_op(dev, phy_addr, regnum,
ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
ret = phy_setup_op(priv, phy_addr, regnum,
ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
if (!ret)
debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
@ -232,29 +235,30 @@ static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
return ret;
}
static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
u32 regnum, u16 data)
{
debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
regnum, data);
return phy_setup_op(dev, phy_addr, regnum,
ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
return phy_setup_op(priv, phy_addr, regnum,
ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
}
static void phy_detection(struct eth_device *dev)
static int phy_detection(struct udevice *dev)
{
int i;
u16 phyreg;
struct zynq_gem_priv *priv = dev->priv;
if (priv->phyaddr != -1) {
phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
if ((phyreg != 0xFFFF) &&
((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
/* Found a valid PHY address */
debug("Default phy address %d is valid\n",
priv->phyaddr);
return;
return 0;
} else {
debug("PHY address is not setup correctly %d\n",
priv->phyaddr);
@ -266,33 +270,36 @@ static void phy_detection(struct eth_device *dev)
if (priv->phyaddr == -1) {
/* detect the PHY address */
for (i = 31; i >= 0; i--) {
phyread(dev, i, PHY_DETECT_REG, &phyreg);
phyread(priv, i, PHY_DETECT_REG, &phyreg);
if ((phyreg != 0xFFFF) &&
((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
/* Found a valid PHY address */
priv->phyaddr = i;
debug("Found valid phy address, %d\n", i);
return;
return 0;
}
}
}
printf("PHY is not detected\n");
return -1;
}
static int zynq_gem_setup_mac(struct eth_device *dev)
static int zynq_gem_setup_mac(struct udevice *dev)
{
u32 i, macaddrlow, macaddrhigh;
struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct zynq_gem_regs *regs = priv->iobase;
/* Set the MAC bits [31:0] in BOT */
macaddrlow = dev->enetaddr[0];
macaddrlow |= dev->enetaddr[1] << 8;
macaddrlow |= dev->enetaddr[2] << 16;
macaddrlow |= dev->enetaddr[3] << 24;
macaddrlow = pdata->enetaddr[0];
macaddrlow |= pdata->enetaddr[1] << 8;
macaddrlow |= pdata->enetaddr[2] << 16;
macaddrlow |= pdata->enetaddr[3] << 24;
/* Set MAC bits [47:32] in TOP */
macaddrhigh = dev->enetaddr[4];
macaddrhigh |= dev->enetaddr[5] << 8;
macaddrhigh = pdata->enetaddr[4];
macaddrhigh |= pdata->enetaddr[5] << 8;
for (i = 0; i < 4; i++) {
writel(0, &regs->laddr[i][LADDR_LOW]);
@ -307,15 +314,11 @@ static int zynq_gem_setup_mac(struct eth_device *dev)
return 0;
}
static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
static int zynq_phy_init(struct udevice *dev)
{
u32 i;
unsigned long clk_rate = 0;
struct phy_device *phydev;
struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
struct zynq_gem_priv *priv = dev->priv;
struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
int ret;
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct zynq_gem_regs *regs = priv->iobase;
const u32 supported = SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
@ -323,6 +326,37 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
SUPPORTED_1000baseT_Half |
SUPPORTED_1000baseT_Full;
/* Enable only MDIO bus */
writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
ret = phy_detection(dev);
if (ret) {
printf("GEM PHY init failed\n");
return ret;
}
priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
priv->interface);
if (!priv->phydev)
return -ENODEV;
priv->phydev->supported = supported | ADVERTISED_Pause |
ADVERTISED_Asym_Pause;
priv->phydev->advertising = priv->phydev->supported;
phy_config(priv->phydev);
return 0;
}
static int zynq_gem_init(struct udevice *dev)
{
u32 i;
unsigned long clk_rate = 0;
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct zynq_gem_regs *regs = priv->iobase;
struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
if (!priv->init) {
/* Disable all interrupts */
writel(0xFFFFFFFF, &regs->idr);
@ -384,25 +418,14 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
priv->init++;
}
phy_detection(dev);
phy_startup(priv->phydev);
/* interface - look at tsec */
phydev = phy_connect(priv->bus, priv->phyaddr, dev,
priv->interface);
phydev->supported = supported | ADVERTISED_Pause |
ADVERTISED_Asym_Pause;
phydev->advertising = phydev->supported;
priv->phydev = phydev;
phy_config(phydev);
phy_startup(phydev);
if (!phydev->link) {
printf("%s: No link.\n", phydev->dev->name);
if (!priv->phydev->link) {
printf("%s: No link.\n", priv->phydev->dev->name);
return -1;
}
switch (phydev->speed) {
switch (priv->phydev->speed) {
case SPEED_1000:
writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
&regs->nwcfg);
@ -420,7 +443,7 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
/* Change the rclk and clk only not using EMIO interface */
if (!priv->emio)
zynq_slcr_gem_clk_setup(dev->iobase !=
zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
ZYNQ_GEM_BASEADDR0, clk_rate);
setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
@ -447,6 +470,11 @@ static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
if (get_timer(start) > timeout)
break;
if (ctrlc()) {
puts("Abort\n");
return -EINTR;
}
udelay(1);
}
@ -456,11 +484,11 @@ static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
return -ETIMEDOUT;
}
static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
{
u32 addr, size;
struct zynq_gem_priv *priv = dev->priv;
struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct zynq_gem_regs *regs = priv->iobase;
struct emac_bd *current_bd = &priv->tx_bd[1];
/* Setup Tx BD */
@ -501,10 +529,10 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
}
/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
static int zynq_gem_recv(struct eth_device *dev)
static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
{
int frame_len;
struct zynq_gem_priv *priv = dev->priv;
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
struct emac_bd *first_bd;
@ -544,51 +572,41 @@ static int zynq_gem_recv(struct eth_device *dev)
return frame_len;
}
static void zynq_gem_halt(struct eth_device *dev)
static void zynq_gem_halt(struct udevice *dev)
{
struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct zynq_gem_regs *regs = priv->iobase;
clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
}
static int zynq_gem_miiphyread(const char *devname, uchar addr,
uchar reg, ushort *val)
static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
int devad, int reg)
{
struct eth_device *dev = eth_get_dev();
struct zynq_gem_priv *priv = bus->priv;
int ret;
u16 val;
ret = phyread(dev, addr, reg, val);
debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
return ret;
ret = phyread(priv, addr, reg, &val);
debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
return val;
}
static int zynq_gem_miiphy_write(const char *devname, uchar addr,
uchar reg, ushort val)
static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
int reg, u16 value)
{
struct eth_device *dev = eth_get_dev();
struct zynq_gem_priv *priv = bus->priv;
debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
return phywrite(dev, addr, reg, val);
debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
return phywrite(priv, addr, reg, value);
}
int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
int phy_addr, u32 emio)
static int zynq_gem_probe(struct udevice *dev)
{
struct eth_device *dev;
struct zynq_gem_priv *priv;
void *bd_space;
dev = calloc(1, sizeof(*dev));
if (dev == NULL)
return -1;
dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
if (dev->priv == NULL) {
free(dev);
return -1;
}
priv = dev->priv;
struct zynq_gem_priv *priv = dev_get_priv(dev);
int ret;
/* Align rxbuffers to ARCH_DMA_MINALIGN */
priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
@ -603,69 +621,87 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
priv->tx_bd = (struct emac_bd *)bd_space;
priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
priv->phyaddr = phy_addr;
priv->emio = emio;
priv->bus = mdio_alloc();
priv->bus->read = zynq_gem_miiphy_read;
priv->bus->write = zynq_gem_miiphy_write;
priv->bus->priv = priv;
strcpy(priv->bus->name, "gem");
#ifndef CONFIG_ZYNQ_GEM_INTERFACE
priv->interface = PHY_INTERFACE_MODE_MII;
#else
priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
#endif
ret = mdio_register(priv->bus);
if (ret)
return ret;
sprintf(dev->name, "Gem.%lx", base_addr);
zynq_phy_init(dev);
dev->iobase = base_addr;
dev->init = zynq_gem_init;
dev->halt = zynq_gem_halt;
dev->send = zynq_gem_send;
dev->recv = zynq_gem_recv;
dev->write_hwaddr = zynq_gem_setup_mac;
eth_register(dev);
miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
priv->bus = miiphy_get_dev_by_name(dev->name);
return 1;
return 0;
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
int zynq_gem_of_init(const void *blob)
static int zynq_gem_remove(struct udevice *dev)
{
int offset = 0;
u32 ret = 0;
u32 reg, phy_reg;
struct zynq_gem_priv *priv = dev_get_priv(dev);
debug("ZYNQ GEM: Initialization\n");
free(priv->phydev);
mdio_unregister(priv->bus);
mdio_free(priv->bus);
do {
offset = fdt_node_offset_by_compatible(blob, offset,
"xlnx,ps7-ethernet-1.00.a");
if (offset != -1) {
reg = fdtdec_get_addr(blob, offset, "reg");
if (reg != FDT_ADDR_T_NONE) {
offset = fdtdec_lookup_phandle(blob, offset,
"phy-handle");
if (offset != -1)
phy_reg = fdtdec_get_addr(blob, offset,
"reg");
else
phy_reg = 0;
debug("ZYNQ GEM: addr %x, phyaddr %x\n",
reg, phy_reg);
ret |= zynq_gem_initialize(NULL, reg,
phy_reg, 0);
} else {
debug("ZYNQ GEM: Can't get base address\n");
return -1;
}
}
} while (offset != -1);
return ret;
return 0;
}
#endif
static const struct eth_ops zynq_gem_ops = {
.start = zynq_gem_init,
.send = zynq_gem_send,
.recv = zynq_gem_recv,
.stop = zynq_gem_halt,
.write_hwaddr = zynq_gem_setup_mac,
};
static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
int offset = 0;
const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
/* Hardcode for now */
priv->emio = 0;
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
"phy-handle");
if (offset > 0)
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0);
phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
priv->interface = pdata->phy_interface;
printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
return 0;
}
static const struct udevice_id zynq_gem_ids[] = {
{ .compatible = "cdns,zynqmp-gem" },
{ .compatible = "cdns,zynq-gem" },
{ .compatible = "cdns,gem" },
{ }
};
U_BOOT_DRIVER(zynq_gem) = {
.name = "zynq_gem",
.id = UCLASS_ETH,
.of_match = zynq_gem_ids,
.ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
.probe = zynq_gem_probe,
.remove = zynq_gem_remove,
.ops = &zynq_gem_ops,
.priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
};

2
drivers/serial/Kconfig
View File

@ -95,7 +95,7 @@ config DEBUG_UART_S5P
config DEBUG_UART_ZYNQ
bool "Xilinx Zynq"
help
Select this to enable a debug UART using the serial_s5p driver. You
Select this to enable a debug UART using the serial_zynq driver. You
will need to provide parameters to make this work. The driver will
be available until the real driver-model serial is running.

5
drivers/serial/serial_zynq.c
View File

@ -180,7 +180,7 @@ static const struct udevice_id zynq_serial_ids[] = {
{ }
};
U_BOOT_DRIVER(serial_s5p) = {
U_BOOT_DRIVER(serial_zynq) = {
.name = "serial_zynq",
.id = UCLASS_SERIAL,
.of_match = zynq_serial_ids,
@ -192,9 +192,6 @@ U_BOOT_DRIVER(serial_s5p) = {
};
#ifdef CONFIG_DEBUG_UART_ZYNQ
#include <debug_uart.h>
void _debug_uart_init(void)
{
struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;

7
include/configs/xilinx_zynqmp.h
View File

@ -184,10 +184,8 @@
#define CONFIG_SYS_MAXARGS 64
/* Ethernet driver */
#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) || \
defined(CONFIG_ZYNQ_GEM2) || defined(CONFIG_ZYNQ_GEM3)
#if defined(CONFIG_ZYNQ_GEM)
# define CONFIG_NET_MULTI
# define CONFIG_ZYNQ_GEM
# define CONFIG_MII
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_PHYLIB
@ -224,9 +222,6 @@
#define CONFIG_CMD_SCSI
#endif
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
#define CONFIG_CMD_BOOTI

3
include/configs/xilinx_zynqmp_ep.h
View File

@ -15,9 +15,6 @@
#ifndef __CONFIG_ZYNQMP_EP_H
#define __CONFIG_ZYNQMP_EP_H
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
#define CONFIG_ZYNQ_I2C0

29
include/configs/zynq-common.h
View File

@ -46,23 +46,15 @@
#define CONFIG_ZYNQ_GPIO
/* Ethernet driver */
#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1)
# define CONFIG_ZYNQ_GEM
#if defined(CONFIG_ZYNQ_GEM)
# define CONFIG_MII
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_PHYLIB
# define CONFIG_PHY_MARVELL
# define CONFIG_BOOTP_SERVERIP
# define CONFIG_BOOTP_BOOTPATH
# define CONFIG_BOOTP_GATEWAY
# define CONFIG_BOOTP_HOSTNAME
# define CONFIG_BOOTP_MAY_FAIL
# if !defined(CONFIG_ZYNQ_GEM_EMIO0)
# define CONFIG_ZYNQ_GEM_EMIO0 0
# endif
# if !defined(CONFIG_ZYNQ_GEM_EMIO1)
# define CONFIG_ZYNQ_GEM_EMIO1 0
# endif
#endif
/* SPI */
@ -298,7 +290,6 @@
/* Boot FreeBSD/vxWorks from an ELF image */
#if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
# define CONFIG_API
# define CONFIG_SYS_MMC_MAX_DEVICE 1
#endif
@ -376,16 +367,16 @@
/* The highest 64k OCM address */
#define OCM_HIGH_ADDR 0xffff0000
/* Just define any reasonable size */
#define CONFIG_SPL_STACK_SIZE 0x1000
/* SPL stack position - and stack goes down */
#define CONFIG_SPL_STACK (OCM_HIGH_ADDR + CONFIG_SPL_STACK_SIZE)
/* On the top of OCM space */
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_STACK + \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x1000
#define CONFIG_SYS_SPL_MALLOC_START OCM_HIGH_ADDR
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000
/*
* SPL stack position - and stack goes down
* 0xfffffe00 is used for putting wfi loop.
* Set it up as limit for now.
*/
#define CONFIG_SPL_STACK 0xfffffe00
/* BSS setup */
#define CONFIG_SPL_BSS_START_ADDR 0x100000

3
include/configs/zynq_microzed.h
View File

@ -12,9 +12,6 @@
#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_SDHCI0

3
include/configs/zynq_picozed.h
View File

@ -12,9 +12,6 @@
#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_SDHCI1

3
include/configs/zynq_zc70x.h
View File

@ -12,9 +12,6 @@
#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_SDHCI0

4
include/configs/zynq_zc770.h
View File

@ -15,8 +15,6 @@
#define CONFIG_SYS_NO_FLASH
#if defined(CONFIG_ZC770_XM010)
# define CONFIG_ZYNQ_GEM0
# define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
# define CONFIG_ZYNQ_SDHCI0
#elif defined(CONFIG_ZC770_XM011)
@ -25,8 +23,6 @@
# undef CONFIG_SYS_NO_FLASH
#elif defined(CONFIG_ZC770_XM013)
# define CONFIG_ZYNQ_GEM1
# define CONFIG_ZYNQ_GEM_PHY_ADDR1 7
#endif

3
include/configs/zynq_zed.h
View File

@ -12,9 +12,6 @@
#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024)
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_USB

3
include/configs/zynq_zybo.h
View File

@ -13,9 +13,6 @@
#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024)
#define CONFIG_ZYNQ_GEM0
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_SDHCI0

3
include/netdev.h
View File

@ -87,9 +87,6 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
int txpp, int rxpp);
int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
unsigned long ctrl_addr);
int zynq_gem_of_init(const void *blob);
int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
int phy_addr, u32 emio);
/*
* As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
* exported by a public hader file, we need a global definition at this point.

14
test/dm/cmd_dm.c
View File

@ -46,11 +46,25 @@ static cmd_tbl_t test_commands[] = {
U_BOOT_CMD_MKENT(devres, 1, 1, do_dm_dump_devres, "", ""),
};
static __maybe_unused void dm_reloc(void)
{
static int relocated;
if (!relocated) {
fixup_cmdtable(test_commands, ARRAY_SIZE(test_commands));
relocated = 1;
}
}
static int do_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
cmd_tbl_t *test_cmd;
int ret;
#ifdef CONFIG_NEEDS_MANUAL_RELOC
dm_reloc();
#endif
if (argc < 2)
return CMD_RET_USAGE;
test_cmd = find_cmd_tbl(argv[1], test_commands,