leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ppc/85xx: Ensure that MAS8 is zero when writing TLB entries.

Browse Source 
Its reset value is random, and we sometimes read uninitialized TLB
arrays.  Make sure that we don't retain MAS8 from reading such an entry
if the VF bit in MAS8 is set, attempts to use the mapping will trap.

Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Scott Wood 2009-08-20 17:45:05 -05:00 committed by Kumar Gala
parent 1b72dbecca
commit dcc87dd58d
3 changed files with 9 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
cpu/mpc85xx/start.S
View File

@ -156,6 +156,10 @@ _start_e500:
mtspr MCSR,r0 /* machine check syndrome register */
mtxer r0 /* clear integer exception register */
#ifdef CONFIG_SYS_BOOK3E_HV
mtspr MAS8,r0 /* make sure MAS8 is clear */
#endif
/* Enable Time Base and Select Time Base Clock */
lis r0,HID0_EMCP@h /* Enable machine check */
#if defined(CONFIG_ENABLE_36BIT_PHYS)

3
cpu/mpc85xx/tlb.c
View File

@ -50,6 +50,9 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
mtspr(MAS3, _mas3);
#ifdef CONFIG_ENABLE_36BIT_PHYS
mtspr(MAS7, _mas7);
#endif
#ifdef CONFIG_SYS_BOOK3E_HV
mtspr(MAS8, 0);
#endif
asm volatile("isync;msync;tlbwe;isync");

2
include/asm-ppc/processor.h
View File

@ -518,6 +518,7 @@
#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
#define SPRN_MAS8 0x155 /* MMU Assist Register 8 */
#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
@ -720,6 +721,7 @@
#define MAS5 SPRN_MAS5
#define MAS6 SPRN_MAS6
#define MAS7 SPRN_MAS7
#define MAS8 SPRN_MAS8
#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
#define DAR_DEAR DEAR