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Tegra30: Add arch-tegra30 include files

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Common Tegra files are in arch-tegra, shared between T20 and T30.
Tegra30-specific headers are in arch-tegra30. Note that some of
these will be filled in as more T30 support is added (drivers,
WB/LP0 support, etc.). A couple of Tegra20 files were changed
to support common headers in arch-tegra, also.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Warren 2012-12-11 13:34:12 +00:00 committed by Tom Warren
parent 6eb320315c
commit dc89ad1438
18 changed files with 1775 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

148
arch/arm/include/asm/arch-tegra/clk_rst.h
View File

@ -21,8 +21,8 @@
* MA 02111-1307 USA
*/
#ifndef _CLK_RST_H_
#define _CLK_RST_H_
#ifndef _TEGRA_CLK_RST_H_
#define _TEGRA_CLK_RST_H_
/* PLL registers - there are several PLLs in the clock controller */
struct clk_pll {
@ -37,6 +37,12 @@ struct clk_pll_simple {
uint pll_misc; /* other misc things */
};
/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
struct clk_set_clr {
uint set;
uint clr;
};
/*
* Most PLLs use the clk_pll structure, but some have a simpler two-member
* structure for which we use clk_pll_simple. The reason for this non-
@ -45,8 +51,10 @@ struct clk_pll_simple {
enum {
TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */
TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */
TEGRA_CLK_REGS = 3, /* Number of clock enable registers */
TEGRA_CLK_SOURCES = 64, /* Number of peripheral clock sources */
TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */
TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */
TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */
TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W*/
};
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@ -82,14 +90,53 @@ struct clk_rst_ctlr {
uint crc_reserved11; /* _reserved_11, 0xFC */
uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */
uint crc_reserved20[80]; /* 0x200-33C */
uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */
uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */
uint crc_reserved20[64]; /* _reserved_20, 0x200-2fc */
/* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
uint crc_reserved30[2]; /* _reserved_30, 0x318, 0x31c */
/* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */
struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS];
uint crc_reserved31[2]; /* _reserved_31, 0x338, 0x33c */
uint crc_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */
uint crc_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */
/* Additional (T30) registers */
uint crc_clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */
uint crc_clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */
uint crc_reserved32[2]; /* _reserved_32, 0x350,0x354 */
uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */
uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */
uint crc_cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */
uint crc_super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */
uint crc_cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */
uint crc_super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */
uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */
uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */
uint crc_reserved33[11]; /* _reserved_33, 0x384-3ac */
uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */
/* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
uint crc_reserved40[12]; /* _reserved_40, 0x450-47C */
uint crc_pll_cfg0; /* _PLL_CFG0_0, 0x480 */
uint crc_pll_cfg1; /* _PLL_CFG1_0, 0x484 */
uint crc_pll_cfg2; /* _PLL_CFG2_0, 0x488 */
};
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
#define CPU3_CLK_STP_SHIFT 11
#define CPU2_CLK_STP_SHIFT 10
#define CPU1_CLK_STP_SHIFT 9
#define CPU0_CLK_STP_SHIFT 8
#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT)
@ -120,6 +167,12 @@ struct clk_rst_ctlr {
#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT)
/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
#define PLL_DCCON_SHIFT 20
#define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT)
#define PLL_LOCK_ENABLE_SHIFT 18
#define PLL_LOCK_ENABLE_MASK (1U << PLL_LOCK_ENABLE_SHIFT)
#define PLL_CPCON_SHIFT 8
#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT)
@ -129,6 +182,22 @@ struct clk_rst_ctlr {
#define PLLU_VCO_FREQ_SHIFT 20
#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT)
#define PLLP_OUT1_OVR (1 << 2)
#define PLLP_OUT2_OVR (1 << 18)
#define PLLP_OUT3_OVR (1 << 2)
#define PLLP_OUT4_OVR (1 << 18)
#define PLLP_OUT1_RATIO 8
#define PLLP_OUT2_RATIO 24
#define PLLP_OUT3_RATIO 8
#define PLLP_OUT4_RATIO 24
enum {
IN_408_OUT_204_DIVISOR = 2,
IN_408_OUT_102_DIVISOR = 6,
IN_408_OUT_48_DIVISOR = 15,
IN_408_OUT_9_6_DIVISOR = 83,
};
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
#define OSC_FREQ_SHIFT 30
#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT)
@ -151,4 +220,65 @@ struct clk_rst_ctlr {
#define OUT_CLK_SOURCE4_SHIFT 28
#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT)
#endif /* CLK_RST_H */
/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
#define SCLK_SYS_STATE_SHIFT 28U
#define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT)
enum {
SCLK_SYS_STATE_STDBY,
SCLK_SYS_STATE_IDLE,
SCLK_SYS_STATE_RUN,
SCLK_SYS_STATE_IRQ = 4U,
SCLK_SYS_STATE_FIQ = 8U,
};
#define SCLK_COP_FIQ_MASK (1 << 27)
#define SCLK_CPU_FIQ_MASK (1 << 26)
#define SCLK_COP_IRQ_MASK (1 << 25)
#define SCLK_CPU_IRQ_MASK (1 << 24)
#define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12
#define SCLK_SWAKEUP_FIQ_SOURCE_MASK \
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
#define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT 8
#define SCLK_SWAKEUP_IRQ_SOURCE_MASK \
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
#define SCLK_SWAKEUP_RUN_SOURCE_SHIFT 4
#define SCLK_SWAKEUP_RUN_SOURCE_MASK \
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
#define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT 0
#define SCLK_SWAKEUP_IDLE_SOURCE_MASK \
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
enum {
SCLK_SOURCE_CLKM,
SCLK_SOURCE_PLLC_OUT1,
SCLK_SOURCE_PLLP_OUT4,
SCLK_SOURCE_PLLP_OUT3,
SCLK_SOURCE_PLLP_OUT2,
SCLK_SOURCE_CLKD,
SCLK_SOURCE_CLKS,
SCLK_SOURCE_PLLM_OUT1,
};
#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12)
#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8)
#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4)
#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0)
/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */
#define SUPER_SCLK_ENB_SHIFT 31U
#define SUPER_SCLK_ENB_MASK (1U << 31)
#define SUPER_SCLK_DIVIDEND_SHIFT 8
#define SUPER_SCLK_DIVIDEND_MASK (0xff << SUPER_SCLK_DIVIDEND_SHIFT)
#define SUPER_SCLK_DIVISOR_SHIFT 0
#define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT)
/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE */
#define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
#define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
#define CLK_SYS_RATE_AHB_RATE_SHIFT 4
#define CLK_SYS_RATE_AHB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
#define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3
#define CLK_SYS_RATE_PCLK_DISABLE_MASK (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT)
#define CLK_SYS_RATE_APB_RATE_SHIFT 0
#define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
#endif /* _TEGRA_CLK_RST_H_ */

8
arch/arm/include/asm/arch-tegra/clock.h
View File

@ -21,8 +21,8 @@
/* Tegra clock control functions */
#ifndef _CLOCK_H
#define _CLOCK_H
#ifndef _TEGRA_CLOCK_H_
#define _TEGRA_CLOCK_H_
/* Set of oscillator frequencies supported in the internal API. */
enum clock_osc_freq {
@ -136,7 +136,7 @@ enum crc_reset_id {
/**
* Put parts of the CPU complex into or out of reset.\
*
* @param cpu cpu number (0 or 1 on Tegra2)
* @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
* @param which which parts of the complex to affect (OR of crc_reset_id)
* @param reset 1 to assert reset, 0 to de-assert
*/
@ -262,4 +262,4 @@ void clock_init(void);
/* Initialize the PLLs */
void clock_early_init(void);
#endif /* _CLOCK_H_ */
#endif /* _TEGRA_CLOCK_H_ */

39
arch/arm/include/asm/arch-tegra/funcmux.h Normal file
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@ -0,0 +1,39 @@
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Tegra high-level function multiplexing */
#ifndef _TEGRA_FUNCMUX_H_
#define _TEGRA_FUNCMUX_H_
/**
* Select a config for a particular peripheral.
*
* Each peripheral can operate through a number of configurations,
* which are sets of pins that it uses to bring out its signals.
* The basic config is 0, and higher numbers indicate different
* pinmux settings to bring the peripheral out on other pins,
*
* This function also disables tristate for the function's pins,
* so that they operate in normal mode.
*
* @param id Peripheral id
* @param config Configuration to use (FUNCMUX_...), 0 for default
* @return 0 if ok, -1 on error (e.g. incorrect id or config)
*/
int funcmux_select(enum periph_id id, int config);
#endif /* _TEGRA_FUNCMUX_H_ */

39
arch/arm/include/asm/arch-tegra/gp_padctrl.h Normal file
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@ -0,0 +1,39 @@
/*
* (C) Copyright 2010-2012
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _TEGRA_GP_PADCTRL_H_
#define _TEGRA_GP_PADCTRL_H_
#define GP_HIDREV 0x804
/* bit fields definitions for APB_MISC_GP_HIDREV register */
#define HIDREV_CHIPID_SHIFT 8
#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
#define HIDREV_MAJORPREV_SHIFT 4
#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
/* CHIPID field returned from APB_MISC_GP_HIDREV register */
#define CHIPID_TEGRA20 0x20
#define CHIPID_TEGRA30 0x30
#endif /* _TEGRA_GP_PADCTRL_H_ */

12
arch/arm/include/asm/arch-tegra/tegra.h
View File

@ -72,14 +72,22 @@ enum {
SKU_ID_T25 = 0x18,
SKU_ID_AP25E = 0x1b,
SKU_ID_T25E = 0x1c,
SKU_ID_T30 = 0x81, /* Cardhu value */
};
/* These are the SOC categories that affect clocking */
/*
* These are used to distinguish SOC types for setting up clocks. Mostly
* we can tell the clocking required by looking at the SOC sku_id, but
* for T30 it is a user option as to whether to run PLLP in fast or slow
* mode, so we have two options there.
*/
enum {
TEGRA_SOC_T20,
TEGRA_SOC_T25,
TEGRA_SOC_T30,
TEGRA_SOC2_SLOW, /* T2x needs to run at slow clock initially */
TEGRA_SOC_COUNT,
TEGRA_SOC_CNT,
TEGRA_SOC_UNKNOWN = -1,
};

26
arch/arm/include/asm/arch-tegra20/funcmux.h
View File

@ -21,8 +21,10 @@
/* Tegra20 high-level function multiplexing */
#ifndef __FUNCMUX_H
#define __FUNCMUX_H
#ifndef _TEGRA20_FUNCMUX_H_
#define _TEGRA20_FUNCMUX_H_
#include <asm/arch-tegra/funcmux.h>
/* Configs supported by the func mux */
enum {
@ -62,22 +64,4 @@ enum {
FUNCMUX_NDFLASH_ATC = 0,
FUNCMUX_NDFLASH_KBC_8_BIT,
};
/**
* Select a config for a particular peripheral.
*
* Each peripheral can operate through a number of configurations,
* which are sets of pins that it uses to bring out its signals.
* The basic config is 0, and higher numbers indicate different
* pinmux settings to bring the peripheral out on other pins,
*
* This function also disables tristate for the function's pins,
* so that they operate in normal mode.
*
* @param id Peripheral id
* @param config Configuration to use (FUNCMUX_...), 0 for default
* @return 0 if ok, -1 on error (e.g. incorrect id or config)
*/
int funcmux_select(enum periph_id id, int config);
#endif
#endif /* _TEGRA20_FUNCMUX_H_ */

17
arch/arm/include/asm/arch-tegra20/gp_padctrl.h
View File

@ -21,8 +21,10 @@
* MA 02111-1307 USA
*/
#ifndef _GP_PADCTRL_H_
#define _GP_PADCTRL_H_
#ifndef _TEGRA20_GP_PADCTRL_H_
#define _TEGRA20_GP_PADCTRL_H_
#include <asm/arch-tegra/gp_padctrl.h>
/* APB_MISC_GP and padctrl registers */
struct apb_misc_gp_ctlr {
@ -61,13 +63,4 @@ struct apb_misc_gp_ctlr {
u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */
};
/* bit fields definitions for APB_MISC_GP_HIDREV register */
#define HIDREV_CHIPID_SHIFT 8
#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
#define HIDREV_MAJORPREV_SHIFT 4
#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
/* CHIPID field returned from APB_MISC_GP_HIDREV register */
#define CHIPID_TEGRA20 0x20
#endif
#endif /* _TEGRA20_GP_PADCTRL_H_ */

378
arch/arm/include/asm/arch-tegra30/clock-tables.h Normal file
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@ -0,0 +1,378 @@
/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Tegra30 clock PLL tables */
#ifndef _TEGRA30_CLOCK_TABLES_H_
#define _TEGRA30_CLOCK_TABLES_H_
/* The PLLs supported by the hardware */
enum clock_id {
CLOCK_ID_FIRST,
CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
CLOCK_ID_MEMORY,
CLOCK_ID_PERIPH,
CLOCK_ID_AUDIO,
CLOCK_ID_USB,
CLOCK_ID_DISPLAY,
/* now the simple ones */
CLOCK_ID_FIRST_SIMPLE,
CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
CLOCK_ID_EPCI,
CLOCK_ID_SFROM32KHZ,
/* These are the base clocks (inputs to the Tegra SOC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
CLOCK_ID_COUNT, /* number of PLLs */
CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */
CLOCK_ID_NONE = -1,
};
/* The clocks supported by the hardware */
enum periph_id {
PERIPH_ID_FIRST,
/* Low word: 31:0 */
PERIPH_ID_CPU = PERIPH_ID_FIRST,
PERIPH_ID_COP,
PERIPH_ID_TRIGSYS,
PERIPH_ID_RESERVED3,
PERIPH_ID_RESERVED4,
PERIPH_ID_TMR,
PERIPH_ID_UART1,
PERIPH_ID_UART2,
/* 8 */
PERIPH_ID_GPIO,
PERIPH_ID_SDMMC2,
PERIPH_ID_SPDIF,
PERIPH_ID_I2S1,
PERIPH_ID_I2C1,
PERIPH_ID_NDFLASH,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC4,
/* 16 */
PERIPH_ID_RESERVED16,
PERIPH_ID_PWM,
PERIPH_ID_I2S2,
PERIPH_ID_EPP,
PERIPH_ID_VI,
PERIPH_ID_2D,
PERIPH_ID_USBD,
PERIPH_ID_ISP,
/* 24 */
PERIPH_ID_3D,
PERIPH_ID_RESERVED24,
PERIPH_ID_DISP2,
PERIPH_ID_DISP1,
PERIPH_ID_HOST1X,
PERIPH_ID_VCP,
PERIPH_ID_I2S0,
PERIPH_ID_CACHE2,
/* Middle word: 63:32 */
PERIPH_ID_MEM,
PERIPH_ID_AHBDMA,
PERIPH_ID_APBDMA,
PERIPH_ID_RESERVED35,
PERIPH_ID_KBC,
PERIPH_ID_STAT_MON,
PERIPH_ID_PMC,
PERIPH_ID_FUSE,
/* 40 */
PERIPH_ID_KFUSE,
PERIPH_ID_SBC1,
PERIPH_ID_SNOR,
PERIPH_ID_RESERVED43,
PERIPH_ID_SBC2,
PERIPH_ID_RESERVED45,
PERIPH_ID_SBC3,
PERIPH_ID_DVC_I2C,
/* 48 */
PERIPH_ID_DSI,
PERIPH_ID_TVO,
PERIPH_ID_MIPI,
PERIPH_ID_HDMI,
PERIPH_ID_CSI,
PERIPH_ID_TVDAC,
PERIPH_ID_I2C2,
PERIPH_ID_UART3,
/* 56 */
PERIPH_ID_RESERVED56,
PERIPH_ID_EMC,
PERIPH_ID_USB2,
PERIPH_ID_USB3,
PERIPH_ID_MPE,
PERIPH_ID_VDE,
PERIPH_ID_BSEA,
PERIPH_ID_BSEV,
/* Upper word 95:64 */
PERIPH_ID_SPEEDO,
PERIPH_ID_UART4,
PERIPH_ID_UART5,
PERIPH_ID_I2C3,
PERIPH_ID_SBC4,
PERIPH_ID_SDMMC3,
PERIPH_ID_PCIE,
PERIPH_ID_OWR,
/* 72 */
PERIPH_ID_AFI,
PERIPH_ID_CORESIGHT,
PERIPH_ID_PCIEXCLK,
PERIPH_ID_AVPUCQ,
PERIPH_ID_RESERVED76,
PERIPH_ID_RESERVED77,
PERIPH_ID_RESERVED78,
PERIPH_ID_DTV,
/* 80 */
PERIPH_ID_NANDSPEED,
PERIPH_ID_I2CSLOW,
PERIPH_ID_DSIB,
PERIPH_ID_RESERVED83,
PERIPH_ID_IRAMA,
PERIPH_ID_IRAMB,
PERIPH_ID_IRAMC,
PERIPH_ID_IRAMD,
/* 88 */
PERIPH_ID_CRAM2,
PERIPH_ID_RESERVED89,
PERIPH_ID_MDOUBLER,
PERIPH_ID_RESERVED91,
PERIPH_ID_SUSOUT,
PERIPH_ID_RESERVED93,
PERIPH_ID_RESERVED94,
PERIPH_ID_RESERVED95,
PERIPH_ID_VW_FIRST,
/* V word: 31:0 */
PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
PERIPH_ID_CPULP,
PERIPH_ID_3D2,
PERIPH_ID_MSELECT,
PERIPH_ID_TSENSOR,
PERIPH_ID_I2S3,
PERIPH_ID_I2S4,
PERIPH_ID_I2C4,
/* 08 */
PERIPH_ID_SBC5,
PERIPH_ID_SBC6,
PERIPH_ID_AUDIO,
PERIPH_ID_APBIF,
PERIPH_ID_DAM0,
PERIPH_ID_DAM1,
PERIPH_ID_DAM2,
PERIPH_ID_HDA2CODEC2X,
/* 16 */
PERIPH_ID_ATOMICS,
PERIPH_ID_EX_RESERVED17,
PERIPH_ID_EX_RESERVED18,
PERIPH_ID_EX_RESERVED19,
PERIPH_ID_EX_RESERVED20,
PERIPH_ID_EX_RESERVED21,
PERIPH_ID_EX_RESERVED22,
PERIPH_ID_ACTMON,
/* 24 */
PERIPH_ID_EX_RESERVED24,
PERIPH_ID_EX_RESERVED25,
PERIPH_ID_EX_RESERVED26,
PERIPH_ID_EX_RESERVED27,
PERIPH_ID_SATA,
PERIPH_ID_HDA,
PERIPH_ID_EX_RESERVED30,
PERIPH_ID_EX_RESERVED31,
/* W word: 31:0 */
PERIPH_ID_HDA2HDMICODEC,
PERIPH_ID_SATACOLD,
PERIPH_ID_RESERVED0_PCIERX0,
PERIPH_ID_RESERVED1_PCIERX1,
PERIPH_ID_RESERVED2_PCIERX2,
PERIPH_ID_RESERVED3_PCIERX3,
PERIPH_ID_RESERVED4_PCIERX4,
PERIPH_ID_RESERVED5_PCIERX5,
/* 40 */
PERIPH_ID_CEC,
PERIPH_ID_RESERVED6_PCIE2,
PERIPH_ID_RESERVED7_EMC,
PERIPH_ID_RESERVED8_HDMI,
PERIPH_ID_RESERVED9_SATA,
PERIPH_ID_RESERVED10_MIPI,
PERIPH_ID_EX_RESERVED46,
PERIPH_ID_EX_RESERVED47,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
};
enum pll_out_id {
PLL_OUT1,
PLL_OUT2,
PLL_OUT3,
PLL_OUT4
};
/*
* Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
* callers to use the PERIPH_ID for all access to peripheral clocks to avoid
* confusion bewteen PERIPH_ID_... and PERIPHC_...
*
* We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
* confusing.
*/
enum periphc_internal_id {
/* 0x00 */
PERIPHC_I2S1,
PERIPHC_I2S2,
PERIPHC_SPDIF_OUT,
PERIPHC_SPDIF_IN,
PERIPHC_PWM,
PERIPHC_05h,
PERIPHC_SBC2,
PERIPHC_SBC3,
/* 0x08 */
PERIPHC_08h,
PERIPHC_I2C1,
PERIPHC_DVC_I2C,
PERIPHC_0bh,
PERIPHC_0ch,
PERIPHC_SBC1,
PERIPHC_DISP1,
PERIPHC_DISP2,
/* 0x10 */
PERIPHC_CVE,
PERIPHC_11h,
PERIPHC_VI,
PERIPHC_13h,
PERIPHC_SDMMC1,
PERIPHC_SDMMC2,
PERIPHC_G3D,
PERIPHC_G2D,
/* 0x18 */
PERIPHC_NDFLASH,
PERIPHC_SDMMC4,
PERIPHC_VFIR,
PERIPHC_EPP,
PERIPHC_MPE,
PERIPHC_MIPI,
PERIPHC_UART1,
PERIPHC_UART2,
/* 0x20 */
PERIPHC_HOST1X,
PERIPHC_21h,
PERIPHC_TVO,
PERIPHC_HDMI,
PERIPHC_24h,
PERIPHC_TVDAC,
PERIPHC_I2C2,
PERIPHC_EMC,
/* 0x28 */
PERIPHC_UART3,
PERIPHC_29h,
PERIPHC_VI_SENSOR,
PERIPHC_2bh,
PERIPHC_2ch,
PERIPHC_SBC4,
PERIPHC_I2C3,
PERIPHC_SDMMC3,
/* 0x30 */
PERIPHC_UART4,
PERIPHC_UART5,
PERIPHC_VDE,
PERIPHC_OWR,
PERIPHC_NOR,
PERIPHC_CSITE,
PERIPHC_I2S0,
PERIPHC_37h,
PERIPHC_VW_FIRST,
/* 0x38 */
PERIPHC_G3D2 = PERIPHC_VW_FIRST,
PERIPHC_MSELECT,
PERIPHC_TSENSOR,
PERIPHC_I2S3,
PERIPHC_I2S4,
PERIPHC_I2C4,
PERIPHC_SBC5,
PERIPHC_SBC6,
/* 0x40 */
PERIPHC_AUDIO,
PERIPHC_41h,
PERIPHC_DAM0,
PERIPHC_DAM1,
PERIPHC_DAM2,
PERIPHC_HDA2CODEC2X,
PERIPHC_ACTMON,
PERIPHC_EXTPERIPH1,
/* 0x48 */
PERIPHC_EXTPERIPH2,
PERIPHC_EXTPERIPH3,
PERIPHC_NANDSPEED,
PERIPHC_I2CSLOW,
PERIPHC_SYS,
PERIPHC_SPEEDO,
PERIPHC_4eh,
PERIPHC_4fh,
/* 0x50 */
PERIPHC_SATAOOB,
PERIPHC_SATA,
PERIPHC_HDA,
PERIPHC_COUNT,
PERIPHC_NONE = -1,
};
/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
#define PERIPH_REG(id) \
(id < PERIPH_ID_VW_FIRST) ? \
((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
/* Mask value for a clock (within PERIPH_REG(id)) */
#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
/* return 1 if a PLL ID is in range */
#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
/* return 1 if a peripheral ID is in range */
#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
(id) < PERIPH_ID_COUNT)
#endif /* _TEGRA30_CLOCK_TABLES_H_ */

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/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Tegra30 clock control functions */
#ifndef _TEGRA30_CLOCK_H_
#define _TEGRA30_CLOCK_H_
#include <asm/arch-tegra/clock.h>
#endif /* _TEGRA30_CLOCK_H_ */

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/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _TEGRA30_FLOW_H_
#define _TEGRA30_FLOW_H_
struct flow_ctlr {
u32 halt_cpu_events;
u32 halt_cop_events;
u32 cpu_csr;
u32 cop_csr;
u32 xrq_events;
u32 halt_cpu1_events;
u32 cpu1_csr;
u32 halt_cpu2_events;
u32 cpu2_csr;
u32 halt_cpu3_events;
u32 cpu3_csr;
u32 cluster_control;
};
#endif /* _TEGRA30_FLOW_H_ */

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/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Tegra30 high-level function multiplexing */
#ifndef _TEGRA30_FUNCMUX_H_
#define _TEGRA30_FUNCMUX_H_
#include <asm/arch-tegra/funcmux.h>
/* Configs supported by the func mux */
enum {
FUNCMUX_DEFAULT = 0, /* default config */
/* UART configs */
FUNCMUX_UART1_ULPI = 0,
};
#endif /* _TEGRA30_FUNCMUX_H_ */

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/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _TEGRA30_GP_PADCTRL_H_
#define _TEGRA30_GP_PADCTRL_H_
#include <asm/arch-tegra/gp_padctrl.h>
/* APB_MISC_GP and padctrl registers */
struct apb_misc_gp_ctlr {
u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
u32 reserved0[22]; /* 0x08 - 0x5C: */
u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
u32 reserved1[7]; /* 0xD0-0xE8: */
u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
};
#endif /* _TEGRA30_GP_PADCTRL_H_ */

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/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _TEGRA30_GPIO_H_
#define _TEGRA30_GPIO_H_
/*
* The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports,
* each with 8 GPIOs.
*/
#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
#define TEGRA_GPIO_BANKS 8 /* number of banks */
#include <asm/arch-tegra/gpio.h>
/* GPIO Controller registers for a single bank */
struct gpio_ctlr_bank {
uint gpio_config[TEGRA_GPIO_PORTS];
uint gpio_dir_out[TEGRA_GPIO_PORTS];
uint gpio_out[TEGRA_GPIO_PORTS];
uint gpio_in[TEGRA_GPIO_PORTS];
uint gpio_int_status[TEGRA_GPIO_PORTS];
uint gpio_int_enable[TEGRA_GPIO_PORTS];
uint gpio_int_level[TEGRA_GPIO_PORTS];
uint gpio_int_clear[TEGRA_GPIO_PORTS];
uint gpio_masked_config[TEGRA_GPIO_PORTS];
uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
uint gpio_masked_out[TEGRA_GPIO_PORTS];
uint gpio_masked_in[TEGRA_GPIO_PORTS];
uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
};
struct gpio_ctlr {
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
};
enum gpio_pin {
GPIO_PA0 = 0, /* pin 0 */
GPIO_PA1,
GPIO_PA2,
GPIO_PA3,
GPIO_PA4,
GPIO_PA5,
GPIO_PA6,
GPIO_PA7,
GPIO_PB0, /* pin 8 */
GPIO_PB1,
GPIO_PB2,
GPIO_PB3,
GPIO_PB4,
GPIO_PB5,
GPIO_PB6,
GPIO_PB7,
GPIO_PC0, /* pin 16 */
GPIO_PC1,
GPIO_PC2,
GPIO_PC3,
GPIO_PC4,
GPIO_PC5,
GPIO_PC6,
GPIO_PC7,
GPIO_PD0, /* pin 24 */
GPIO_PD1,
GPIO_PD2,
GPIO_PD3,
GPIO_PD4,
GPIO_PD5,
GPIO_PD6,
GPIO_PD7,
GPIO_PE0, /* pin 32 */
GPIO_PE1,
GPIO_PE2,
GPIO_PE3,
GPIO_PE4,
GPIO_PE5,
GPIO_PE6,
GPIO_PE7,
GPIO_PF0, /* pin 40 */
GPIO_PF1,
GPIO_PF2,
GPIO_PF3,
GPIO_PF4,
GPIO_PF5,
GPIO_PF6,
GPIO_PF7,
GPIO_PG0, /* pin 48 */
GPIO_PG1,
GPIO_PG2,
GPIO_PG3,
GPIO_PG4,
GPIO_PG5,
GPIO_PG6,
GPIO_PG7,
GPIO_PH0, /* pin 56 */
GPIO_PH1,
GPIO_PH2,
GPIO_PH3,
GPIO_PH4,
GPIO_PH5,
GPIO_PH6,
GPIO_PH7,
GPIO_PI0, /* pin 64 */
GPIO_PI1,
GPIO_PI2,
GPIO_PI3,
GPIO_PI4,
GPIO_PI5,
GPIO_PI6,
GPIO_PI7,
GPIO_PJ0, /* pin 72 */
GPIO_PJ1,
GPIO_PJ2,
GPIO_PJ3,
GPIO_PJ4,
GPIO_PJ5,
GPIO_PJ6,
GPIO_PJ7,
GPIO_PK0, /* pin 80 */
GPIO_PK1,
GPIO_PK2,
GPIO_PK3,
GPIO_PK4,
GPIO_PK5,
GPIO_PK6,
GPIO_PK7,
GPIO_PL0, /* pin 88 */
GPIO_PL1,
GPIO_PL2,
GPIO_PL3,
GPIO_PL4,
GPIO_PL5,
GPIO_PL6,
GPIO_PL7,
GPIO_PM0, /* pin 96 */
GPIO_PM1,
GPIO_PM2,
GPIO_PM3,
GPIO_PM4,
GPIO_PM5,
GPIO_PM6,
GPIO_PM7,
GPIO_PN0, /* pin 104 */
GPIO_PN1,
GPIO_PN2,
GPIO_PN3,
GPIO_PN4,
GPIO_PN5,
GPIO_PN6,
GPIO_PN7,
GPIO_PO0, /* pin 112 */
GPIO_PO1,
GPIO_PO2,
GPIO_PO3,
GPIO_PO4,
GPIO_PO5,
GPIO_PO6,
GPIO_PO7,
GPIO_PP0, /* pin 120 */
GPIO_PP1,
GPIO_PP2,
GPIO_PP3,
GPIO_PP4,
GPIO_PP5,
GPIO_PP6,
GPIO_PP7,
GPIO_PQ0, /* pin 128 */
GPIO_PQ1,
GPIO_PQ2,
GPIO_PQ3,
GPIO_PQ4,
GPIO_PQ5,
GPIO_PQ6,
GPIO_PQ7,
GPIO_PR0, /* pin 136 */
GPIO_PR1,
GPIO_PR2,
GPIO_PR3,
GPIO_PR4,
GPIO_PR5,
GPIO_PR6,
GPIO_PR7,
GPIO_PS0, /* pin 144 */
GPIO_PS1,
GPIO_PS2,
GPIO_PS3,
GPIO_PS4,
GPIO_PS5,
GPIO_PS6,
GPIO_PS7,
GPIO_PT0, /* pin 152 */
GPIO_PT1,
GPIO_PT2,
GPIO_PT3,
GPIO_PT4,
GPIO_PT5,
GPIO_PT6,
GPIO_PT7,
GPIO_PU0, /* pin 160 */
GPIO_PU1,
GPIO_PU2,
GPIO_PU3,
GPIO_PU4,
GPIO_PU5,
GPIO_PU6,
GPIO_PU7,
GPIO_PV0, /* pin 168 */
GPIO_PV1,
GPIO_PV2,
GPIO_PV3,
GPIO_PV4,
GPIO_PV5,
GPIO_PV6,
GPIO_PV7,
GPIO_PW0, /* pin 176 */
GPIO_PW1,
GPIO_PW2,
GPIO_PW3,
GPIO_PW4,
GPIO_PW5,
GPIO_PW6,
GPIO_PW7,
GPIO_PX0, /* pin 184 */
GPIO_PX1,
GPIO_PX2,
GPIO_PX3,
GPIO_PX4,
GPIO_PX5,
GPIO_PX6,
GPIO_PX7,
GPIO_PY0, /* pin 192 */
GPIO_PY1,
GPIO_PY2,
GPIO_PY3,
GPIO_PY4,
GPIO_PY5,
GPIO_PY6,
GPIO_PY7,
GPIO_PZ0, /* pin 200 */
GPIO_PZ1,
GPIO_PZ2,
GPIO_PZ3,
GPIO_PZ4,
GPIO_PZ5,
GPIO_PZ6,
GPIO_PZ7,
GPIO_PAA0, /* pin 208 */
GPIO_PAA1,
GPIO_PAA2,
GPIO_PAA3,
GPIO_PAA4,
GPIO_PAA5,
GPIO_PAA6,
GPIO_PAA7,
GPIO_PBB0, /* pin 216 */
GPIO_PBB1,
GPIO_PBB2,
GPIO_PBB3,
GPIO_PBB4,
GPIO_PBB5,
GPIO_PBB6,
GPIO_PBB7,
GPIO_PCC0, /* pin 224 */
GPIO_PCC1,
GPIO_PCC2,
GPIO_PCC3,
GPIO_PCC4,
GPIO_PCC5,
GPIO_PCC6,
GPIO_PCC7,
GPIO_PDD0, /* pin 232 */
GPIO_PDD1,
GPIO_PDD2,
GPIO_PDD3,
GPIO_PDD4,
GPIO_PDD5,
GPIO_PDD6,
GPIO_PDD7,
GPIO_PEE0, /* pin 240 */
GPIO_PEE1,
GPIO_PEE2,
GPIO_PEE3,
GPIO_PEE4,
GPIO_PEE5,
GPIO_PEE6,
GPIO_PEE7, /* pin 247 */
};
#endif /* _TEGRA30_GPIO_H_ */

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/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _TEGRA30_HARDWARE_H_
#define _TEGRA30_HARDWARE_H_
/* include tegra specific hardware definitions */
#endif /* _TEGRA30-HARDWARE_H_ */

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/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _TEGRA30_PINMUX_H_
#define _TEGRA30_PINMUX_H_
/*
* Pin groups which we adjust. There are three basic attributes of each pin
* group which use this enum:
*
* - function
* - pullup / pulldown
* - tristate or normal
*/
enum pmux_pingrp {
PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
PINGRP_ULPI_DATA1,
PINGRP_ULPI_DATA2,
PINGRP_ULPI_DATA3,
PINGRP_ULPI_DATA4,
PINGRP_ULPI_DATA5,
PINGRP_ULPI_DATA6,
PINGRP_ULPI_DATA7,
PINGRP_ULPI_CLK,
PINGRP_ULPI_DIR,
PINGRP_ULPI_NXT,
PINGRP_ULPI_STP,
PINGRP_DAP3_FS,
PINGRP_DAP3_DIN,
PINGRP_DAP3_DOUT,
PINGRP_DAP3_SCLK,
PINGRP_GPIO_PV0,
PINGRP_GPIO_PV1,
PINGRP_SDMMC1_CLK,
PINGRP_SDMMC1_CMD,
PINGRP_SDMMC1_DAT3,
PINGRP_SDMMC1_DAT2,
PINGRP_SDMMC1_DAT1,
PINGRP_SDMMC1_DAT0,
PINGRP_GPIO_PV2,
PINGRP_GPIO_PV3,
PINGRP_CLK2_OUT,
PINGRP_CLK2_REQ,
PINGRP_LCD_PWR1,
PINGRP_LCD_PWR2,
PINGRP_LCD_SDIN,
PINGRP_LCD_SDOUT,
PINGRP_LCD_WR_N,
PINGRP_LCD_CS0_N,
PINGRP_LCD_DC0,
PINGRP_LCD_SCK,
PINGRP_LCD_PWR0,
PINGRP_LCD_PCLK,
PINGRP_LCD_DE,
PINGRP_LCD_HSYNC,
PINGRP_LCD_VSYNC,
PINGRP_LCD_D0,
PINGRP_LCD_D1,
PINGRP_LCD_D2,
PINGRP_LCD_D3,
PINGRP_LCD_D4,
PINGRP_LCD_D5,
PINGRP_LCD_D6,
PINGRP_LCD_D7,
PINGRP_LCD_D8,
PINGRP_LCD_D9,
PINGRP_LCD_D10,
PINGRP_LCD_D11,
PINGRP_LCD_D12,
PINGRP_LCD_D13,
PINGRP_LCD_D14,
PINGRP_LCD_D15,
PINGRP_LCD_D16,
PINGRP_LCD_D17,
PINGRP_LCD_D18,
PINGRP_LCD_D19,
PINGRP_LCD_D20,
PINGRP_LCD_D21,
PINGRP_LCD_D22,
PINGRP_LCD_D23,
PINGRP_LCD_CS1_N,
PINGRP_LCD_M1,
PINGRP_LCD_DC1,
PINGRP_HDMI_INT,
PINGRP_DDC_SCL,
PINGRP_DDC_SDA,
PINGRP_CRT_HSYNC,
PINGRP_CRT_VSYNC,
PINGRP_VI_D0,
PINGRP_VI_D1,
PINGRP_VI_D2,
PINGRP_VI_D3,
PINGRP_VI_D4,
PINGRP_VI_D5,
PINGRP_VI_D6,
PINGRP_VI_D7,
PINGRP_VI_D8,
PINGRP_VI_D9,
PINGRP_VI_D10,
PINGRP_VI_D11,
PINGRP_VI_PCLK,
PINGRP_VI_MCLK,
PINGRP_VI_VSYNC,
PINGRP_VI_HSYNC,
PINGRP_UART2_RXD,
PINGRP_UART2_TXD,
PINGRP_UART2_RTS_N,
PINGRP_UART2_CTS_N,
PINGRP_UART3_TXD,
PINGRP_UART3_RXD,
PINGRP_UART3_CTS_N,
PINGRP_UART3_RTS_N,
PINGRP_GPIO_PU0,
PINGRP_GPIO_PU1,
PINGRP_GPIO_PU2,
PINGRP_GPIO_PU3,
PINGRP_GPIO_PU4,
PINGRP_GPIO_PU5,
PINGRP_GPIO_PU6,
PINGRP_GEN1_I2C_SDA,
PINGRP_GEN1_I2C_SCL,
PINGRP_DAP4_FS,
PINGRP_DAP4_DIN,
PINGRP_DAP4_DOUT,
PINGRP_DAP4_SCLK,
PINGRP_CLK3_OUT,
PINGRP_CLK3_REQ,
PINGRP_GMI_WP_N,
PINGRP_GMI_IORDY,
PINGRP_GMI_WAIT,
PINGRP_GMI_ADV_N,
PINGRP_GMI_CLK,
PINGRP_GMI_CS0_N,
PINGRP_GMI_CS1_N,
PINGRP_GMI_CS2_N,
PINGRP_GMI_CS3_N,
PINGRP_GMI_CS4_N,
PINGRP_GMI_CS6_N,
PINGRP_GMI_CS7_N,
PINGRP_GMI_AD0,
PINGRP_GMI_AD1,
PINGRP_GMI_AD2,
PINGRP_GMI_AD3,
PINGRP_GMI_AD4,
PINGRP_GMI_AD5,
PINGRP_GMI_AD6,
PINGRP_GMI_AD7,
PINGRP_GMI_AD8,
PINGRP_GMI_AD9,
PINGRP_GMI_AD10,
PINGRP_GMI_AD11,
PINGRP_GMI_AD12,
PINGRP_GMI_AD13,
PINGRP_GMI_AD14,
PINGRP_GMI_AD15,
PINGRP_GMI_A16,
PINGRP_GMI_A17,
PINGRP_GMI_A18,
PINGRP_GMI_A19,
PINGRP_GMI_WR_N,
PINGRP_GMI_OE_N,
PINGRP_GMI_DQS,
PINGRP_GMI_RST_N,
PINGRP_GEN2_I2C_SCL,
PINGRP_GEN2_I2C_SDA,
PINGRP_SDMMC4_CLK,
PINGRP_SDMMC4_CMD,
PINGRP_SDMMC4_DAT0,
PINGRP_SDMMC4_DAT1,
PINGRP_SDMMC4_DAT2,
PINGRP_SDMMC4_DAT3,
PINGRP_SDMMC4_DAT4,
PINGRP_SDMMC4_DAT5,
PINGRP_SDMMC4_DAT6,
PINGRP_SDMMC4_DAT7,
PINGRP_SDMMC4_RST_N,
PINGRP_CAM_MCLK,
PINGRP_GPIO_PCC1,
PINGRP_GPIO_PBB0,
PINGRP_CAM_I2C_SCL,
PINGRP_CAM_I2C_SDA,
PINGRP_GPIO_PBB3,
PINGRP_GPIO_PBB4,
PINGRP_GPIO_PBB5,
PINGRP_GPIO_PBB6,
PINGRP_GPIO_PBB7,
PINGRP_GPIO_PCC2,
PINGRP_JTAG_RTCK,
PINGRP_PWR_I2C_SCL,
PINGRP_PWR_I2C_SDA,
PINGRP_KB_ROW0,
PINGRP_KB_ROW1,
PINGRP_KB_ROW2,
PINGRP_KB_ROW3,
PINGRP_KB_ROW4,
PINGRP_KB_ROW5,
PINGRP_KB_ROW6,
PINGRP_KB_ROW7,
PINGRP_KB_ROW8,
PINGRP_KB_ROW9,
PINGRP_KB_ROW10,
PINGRP_KB_ROW11,
PINGRP_KB_ROW12,
PINGRP_KB_ROW13,
PINGRP_KB_ROW14,
PINGRP_KB_ROW15,
PINGRP_KB_COL0,
PINGRP_KB_COL1,
PINGRP_KB_COL2,
PINGRP_KB_COL3,
PINGRP_KB_COL4,
PINGRP_KB_COL5,
PINGRP_KB_COL6,
PINGRP_KB_COL7,
PINGRP_CLK_32K_OUT,
PINGRP_SYS_CLK_REQ,
PINGRP_CORE_PWR_REQ,
PINGRP_CPU_PWR_REQ,
PINGRP_PWR_INT_N,
PINGRP_CLK_32K_IN,
PINGRP_OWR,
PINGRP_DAP1_FS,
PINGRP_DAP1_DIN,
PINGRP_DAP1_DOUT,
PINGRP_DAP1_SCLK,
PINGRP_CLK1_REQ,
PINGRP_CLK1_OUT,
PINGRP_SPDIF_IN,
PINGRP_SPDIF_OUT,
PINGRP_DAP2_FS,
PINGRP_DAP2_DIN,
PINGRP_DAP2_DOUT,
PINGRP_DAP2_SCLK,
PINGRP_SPI2_MOSI,
PINGRP_SPI2_MISO,
PINGRP_SPI2_CS0_N,
PINGRP_SPI2_SCK,
PINGRP_SPI1_MOSI,
PINGRP_SPI1_SCK,
PINGRP_SPI1_CS0_N,
PINGRP_SPI1_MISO,
PINGRP_SPI2_CS1_N,
PINGRP_SPI2_CS2_N,
PINGRP_SDMMC3_CLK,
PINGRP_SDMMC3_CMD,
PINGRP_SDMMC3_DAT0,
PINGRP_SDMMC3_DAT1,
PINGRP_SDMMC3_DAT2,
PINGRP_SDMMC3_DAT3,
PINGRP_SDMMC3_DAT4,
PINGRP_SDMMC3_DAT5,
PINGRP_SDMMC3_DAT6,
PINGRP_SDMMC3_DAT7,
PINGRP_PEX_L0_PRSNT_N,
PINGRP_PEX_L0_RST_N,
PINGRP_PEX_L0_CLKREQ_N,
PINGRP_PEX_WAKE_N,
PINGRP_PEX_L1_PRSNT_N,
PINGRP_PEX_L1_RST_N,
PINGRP_PEX_L1_CLKREQ_N,
PINGRP_PEX_L2_PRSNT_N,
PINGRP_PEX_L2_RST_N,
PINGRP_PEX_L2_CLKREQ_N,
PINGRP_HDMI_CEC, /* offset 0x33e0 */
PINGRP_COUNT,
};
enum pdrive_pingrp {
PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
PDRIVE_PINGROUP_AO2,
PDRIVE_PINGROUP_AT1,
PDRIVE_PINGROUP_AT2,
PDRIVE_PINGROUP_AT3,
PDRIVE_PINGROUP_AT4,
PDRIVE_PINGROUP_AT5,
PDRIVE_PINGROUP_CDEV1,
PDRIVE_PINGROUP_CDEV2,
PDRIVE_PINGROUP_CSUS,
PDRIVE_PINGROUP_DAP1,
PDRIVE_PINGROUP_DAP2,
PDRIVE_PINGROUP_DAP3,
PDRIVE_PINGROUP_DAP4,
PDRIVE_PINGROUP_DBG,
PDRIVE_PINGROUP_LCD1,
PDRIVE_PINGROUP_LCD2,
PDRIVE_PINGROUP_SDIO2,
PDRIVE_PINGROUP_SDIO3,
PDRIVE_PINGROUP_SPI,
PDRIVE_PINGROUP_UAA,
PDRIVE_PINGROUP_UAB,
PDRIVE_PINGROUP_UART2,
PDRIVE_PINGROUP_UART3,
PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */
PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */
PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */
PDRIVE_PINGROUP_DDC,
PDRIVE_PINGROUP_GMA,
PDRIVE_PINGROUP_GMB,
PDRIVE_PINGROUP_GMC,
PDRIVE_PINGROUP_GMD,
PDRIVE_PINGROUP_GME,
PDRIVE_PINGROUP_GMF,
PDRIVE_PINGROUP_GMG,
PDRIVE_PINGROUP_GMH,
PDRIVE_PINGROUP_OWR,
PDRIVE_PINGROUP_UAD,
PDRIVE_PINGROUP_GPV,
PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
PDRIVE_PINGROUP_COUNT,
};
/*
* Functions which can be assigned to each of the pin groups. The values here
* bear no relation to the values programmed into pinmux registers and are
* purely a convenience. The translation is done through a table search.
*/
enum pmux_func {
PMUX_FUNC_AHB_CLK,
PMUX_FUNC_APB_CLK,
PMUX_FUNC_AUDIO_SYNC,
PMUX_FUNC_CRT,
PMUX_FUNC_DAP1,
PMUX_FUNC_DAP2,
PMUX_FUNC_DAP3,
PMUX_FUNC_DAP4,
PMUX_FUNC_DAP5,
PMUX_FUNC_DISPA,
PMUX_FUNC_DISPB,
PMUX_FUNC_EMC_TEST0_DLL,
PMUX_FUNC_EMC_TEST1_DLL,
PMUX_FUNC_GMI,
PMUX_FUNC_GMI_INT,
PMUX_FUNC_HDMI,
PMUX_FUNC_I2C1,
PMUX_FUNC_I2C2,
PMUX_FUNC_I2C3,
PMUX_FUNC_IDE,
PMUX_FUNC_IRDA,
PMUX_FUNC_KBC,
PMUX_FUNC_MIO,
PMUX_FUNC_MIPI_HS,
PMUX_FUNC_NAND,
PMUX_FUNC_OSC,
PMUX_FUNC_OWR,
PMUX_FUNC_PCIE,
PMUX_FUNC_PLLA_OUT,
PMUX_FUNC_PLLC_OUT1,
PMUX_FUNC_PLLM_OUT1,
PMUX_FUNC_PLLP_OUT2,
PMUX_FUNC_PLLP_OUT3,
PMUX_FUNC_PLLP_OUT4,
PMUX_FUNC_PWM,
PMUX_FUNC_PWR_INTR,
PMUX_FUNC_PWR_ON,
PMUX_FUNC_RTCK,
PMUX_FUNC_SDMMC1,
PMUX_FUNC_SDMMC2,
PMUX_FUNC_SDMMC3,
PMUX_FUNC_SDMMC4,
PMUX_FUNC_SFLASH,
PMUX_FUNC_SPDIF,
PMUX_FUNC_SPI1,
PMUX_FUNC_SPI2,
PMUX_FUNC_SPI2_ALT,
PMUX_FUNC_SPI3,
PMUX_FUNC_SPI4,
PMUX_FUNC_TRACE,
PMUX_FUNC_TWC,
PMUX_FUNC_UARTA,
PMUX_FUNC_UARTB,
PMUX_FUNC_UARTC,
PMUX_FUNC_UARTD,
PMUX_FUNC_UARTE,
PMUX_FUNC_ULPI,
PMUX_FUNC_VI,
PMUX_FUNC_VI_SENSOR_CLK,
PMUX_FUNC_XIO,
PMUX_FUNC_BLINK,
PMUX_FUNC_CEC,
PMUX_FUNC_CLK12,
PMUX_FUNC_DAP,
PMUX_FUNC_DAPSDMMC2,
PMUX_FUNC_DDR,
PMUX_FUNC_DEV3,
PMUX_FUNC_DTV,
PMUX_FUNC_VI_ALT1,
PMUX_FUNC_VI_ALT2,
PMUX_FUNC_VI_ALT3,
PMUX_FUNC_EMC_DLL,
PMUX_FUNC_EXTPERIPH1,
PMUX_FUNC_EXTPERIPH2,
PMUX_FUNC_EXTPERIPH3,
PMUX_FUNC_GMI_ALT,
PMUX_FUNC_HDA,
PMUX_FUNC_HSI,
PMUX_FUNC_I2C4,
PMUX_FUNC_I2C5,
PMUX_FUNC_I2CPWR,
PMUX_FUNC_I2S0,
PMUX_FUNC_I2S1,
PMUX_FUNC_I2S2,
PMUX_FUNC_I2S3,
PMUX_FUNC_I2S4,
PMUX_FUNC_NAND_ALT,
PMUX_FUNC_POPSDIO4,
PMUX_FUNC_POPSDMMC4,
PMUX_FUNC_PWM0,
PMUX_FUNC_PWM1,
PMUX_FUNC_PWM2,
PMUX_FUNC_PWM3,
PMUX_FUNC_SATA,
PMUX_FUNC_SPI5,
PMUX_FUNC_SPI6,
PMUX_FUNC_SYSCLK,
PMUX_FUNC_VGP1,
PMUX_FUNC_VGP2,
PMUX_FUNC_VGP3,
PMUX_FUNC_VGP4,
PMUX_FUNC_VGP5,
PMUX_FUNC_VGP6,
PMUX_FUNC_CLK_12M_OUT,
PMUX_FUNC_HDCP,
PMUX_FUNC_TEST,
PMUX_FUNC_CORE_PWR_REQ,
PMUX_FUNC_CPU_PWR_REQ,
PMUX_FUNC_PWR_INT_N,
PMUX_FUNC_CLK_32K_IN,
PMUX_FUNC_SAFE,
PMUX_FUNC_MAX,
PMUX_FUNC_RSVD1 = 0x8000,
PMUX_FUNC_RSVD2 = 0x8001,
PMUX_FUNC_RSVD3 = 0x8002,
PMUX_FUNC_RSVD4 = 0x8003,
};
/* return 1 if a pmux_func is in range */
#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
|| (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
/* return 1 if a pingrp is in range */
#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
/* The pullup/pulldown state of a pin group */
enum pmux_pull {
PMUX_PULL_NORMAL = 0,
PMUX_PULL_DOWN,
PMUX_PULL_UP,
};
/* return 1 if a pin_pupd_is in range */
#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
((pupd) <= PMUX_PULL_UP))
/* Defines whether a pin group is tristated or in normal operation */
enum pmux_tristate {
PMUX_TRI_NORMAL = 0,
PMUX_TRI_TRISTATE = 1,
};
/* return 1 if a pin_tristate_is in range */
#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
&& ((tristate) <= PMUX_TRI_TRISTATE))
enum pmux_pin_io {
PMUX_PIN_OUTPUT = 0,
PMUX_PIN_INPUT = 1,
};
/* return 1 if a pin_io_is in range */
#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
((io) <= PMUX_PIN_INPUT))
enum pmux_pin_lock {
PMUX_PIN_LOCK_DEFAULT = 0,
PMUX_PIN_LOCK_DISABLE,
PMUX_PIN_LOCK_ENABLE,
};
/* return 1 if a pin_lock is in range */
#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
((lock) <= PMUX_PIN_LOCK_ENABLE))
enum pmux_pin_od {
PMUX_PIN_OD_DEFAULT = 0,
PMUX_PIN_OD_DISABLE,
PMUX_PIN_OD_ENABLE,
};
/* return 1 if a pin_od is in range */
#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
((od) <= PMUX_PIN_OD_ENABLE))
enum pmux_pin_ioreset {
PMUX_PIN_IO_RESET_DEFAULT = 0,
PMUX_PIN_IO_RESET_DISABLE,
PMUX_PIN_IO_RESET_ENABLE,
};
/* return 1 if a pin_ioreset_is in range */
#define pmux_pin_ioreset_isvalid(ioreset) \
(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
/* Available power domains used by pin groups */
enum pmux_vddio {
PMUX_VDDIO_BB = 0,
PMUX_VDDIO_LCD,
PMUX_VDDIO_VI,
PMUX_VDDIO_UART,
PMUX_VDDIO_DDR,
PMUX_VDDIO_NAND,
PMUX_VDDIO_SYS,
PMUX_VDDIO_AUDIO,
PMUX_VDDIO_SD,
PMUX_VDDIO_CAM,
PMUX_VDDIO_GMI,
PMUX_VDDIO_PEXCTL,
PMUX_VDDIO_SDMMC1,
PMUX_VDDIO_SDMMC3,
PMUX_VDDIO_SDMMC4,
PMUX_VDDIO_NONE
};
/* t30 pin drive group and pin mux registers */
#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
PDRIVE_PINGROUP_COUNT)
struct pmux_tri_ctlr {
uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
uint pmt_reserved5[PMUX_OFFSET];
uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
};
/*
* This defines the configuration for a pin, including the function assigned,
* pull up/down settings and tristate settings. Having set up one of these
* you can call pinmux_config_pingroup() to configure a pin in one step. Also
* available is pinmux_config_table() to configure a list of pins.
*/
struct pingroup_config {
enum pmux_pingrp pingroup; /* pin group PINGRP_... */
enum pmux_func func; /* function to assign FUNC_... */
enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
enum pmux_pin_io io; /* input or output PMUX_PIN_... */
enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
enum pmux_pin_od od; /* open-drain or push-pull driver */
enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
};
/* Set a pin group to tristate */
void pinmux_tristate_enable(enum pmux_pingrp pin);
/* Set a pin group to normal (non tristate) */
void pinmux_tristate_disable(enum pmux_pingrp pin);
/* Set the pull up/down feature for a pin group */
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
/* Set the mux function for a pin group */
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
/* Set the complete configuration for a pin group */
void pinmux_config_pingroup(struct pingroup_config *config);
/* Set a pin group to tristate or normal */
void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
/* Set a pin group as input or output */
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
/**
* Configure a list of pin groups
*
* @param config List of config items
* @param len Number of config items in list
*/
void pinmux_config_table(struct pingroup_config *config, int len);
/* Set a group of pins from a table */
void pinmux_init(void);
#endif /* _TEGRA30_PINMUX_H_ */

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/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _TEGRA30_PMU_H_
#define _TEGRA30_PMU_H_
/* Set core and CPU voltages to nominal levels */
int pmu_set_nominal(void);
#endif /* _TEGRA30_PMU_H_ */

28
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/*
* (C) Copyright 2012
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_ARCH_SPL_H_
#define BOOT_DEVICE_RAM 1
#endif

26
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/*
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _TEGRA30_H_
#define _TEGRA30_H_
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
#include <asm/arch-tegra/tegra.h>
#define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */
#endif /* TEGRA30_H */