x86: Bring in msr-index.h from linux 3.8
Update this file to include x86_64 fields. Signed-off-by: Simon Glass <sjg@chromium.org>
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Simon Glass
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7bddac947d
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dc68584b42
@ -44,12 +44,16 @@
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#define MSR_IA32_PERFCTR0 0x000000c1
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#define MSR_IA32_PERFCTR1 0x000000c2
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#define MSR_FSB_FREQ 0x000000cd
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#define MSR_NHM_PLATFORM_INFO 0x000000ce
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#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
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#define NHM_C3_AUTO_DEMOTE (1UL << 25)
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#define NHM_C1_AUTO_DEMOTE (1UL << 26)
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#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
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#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
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#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
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#define MSR_PLATFORM_INFO 0x000000ce
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#define MSR_MTRRcap 0x000000fe
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#define MSR_IA32_BBL_CR_CTL 0x00000119
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#define MSR_IA32_BBL_CR_CTL3 0x0000011e
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@ -64,10 +68,20 @@
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#define MSR_OFFCORE_RSP_0 0x000001a6
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#define MSR_OFFCORE_RSP_1 0x000001a7
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#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad
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#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae
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#define MSR_LBR_SELECT 0x000001c8
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#define MSR_LBR_TOS 0x000001c9
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#define MSR_LBR_NHM_FROM 0x00000680
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#define MSR_LBR_NHM_TO 0x000006c0
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#define MSR_LBR_CORE_FROM 0x00000040
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#define MSR_LBR_CORE_TO 0x00000060
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#define MSR_IA32_PEBS_ENABLE 0x000003f1
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#define MSR_IA32_DS_AREA 0x00000600
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#define MSR_IA32_PERF_CAPABILITIES 0x00000345
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#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
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#define MSR_MTRRfix64K_00000 0x00000250
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#define MSR_MTRRfix16K_80000 0x00000258
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@ -91,7 +105,8 @@
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#define MSR_IA32_LASTINTTOIP 0x000001de
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/* DEBUGCTLMSR bits (others vary by model): */
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#define DEBUGCTLMSR_LBR (1UL << 0)
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#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
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/* single-step on branches */
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#define DEBUGCTLMSR_BTF (1UL << 1)
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#define DEBUGCTLMSR_TR (1UL << 6)
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#define DEBUGCTLMSR_BTS (1UL << 7)
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@ -100,11 +115,50 @@
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#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
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#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
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#define MSR_IA32_POWER_CTL 0x000001fc
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#define MSR_IA32_MC0_CTL 0x00000400
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#define MSR_IA32_MC0_STATUS 0x00000401
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#define MSR_IA32_MC0_ADDR 0x00000402
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#define MSR_IA32_MC0_MISC 0x00000403
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/* C-state Residency Counters */
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#define MSR_PKG_C3_RESIDENCY 0x000003f8
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#define MSR_PKG_C6_RESIDENCY 0x000003f9
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#define MSR_PKG_C7_RESIDENCY 0x000003fa
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#define MSR_CORE_C3_RESIDENCY 0x000003fc
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#define MSR_CORE_C6_RESIDENCY 0x000003fd
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#define MSR_CORE_C7_RESIDENCY 0x000003fe
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#define MSR_PKG_C2_RESIDENCY 0x0000060d
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#define MSR_PKG_C8_RESIDENCY 0x00000630
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#define MSR_PKG_C9_RESIDENCY 0x00000631
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#define MSR_PKG_C10_RESIDENCY 0x00000632
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/* Run Time Average Power Limiting (RAPL) Interface */
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#define MSR_RAPL_POWER_UNIT 0x00000606
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#define MSR_PKG_POWER_LIMIT 0x00000610
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#define MSR_PKG_ENERGY_STATUS 0x00000611
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#define MSR_PKG_PERF_STATUS 0x00000613
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#define MSR_PKG_POWER_INFO 0x00000614
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#define MSR_DRAM_POWER_LIMIT 0x00000618
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#define MSR_DRAM_ENERGY_STATUS 0x00000619
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#define MSR_DRAM_PERF_STATUS 0x0000061b
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#define MSR_DRAM_POWER_INFO 0x0000061c
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#define MSR_PP0_POWER_LIMIT 0x00000638
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#define MSR_PP0_ENERGY_STATUS 0x00000639
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#define MSR_PP0_POLICY 0x0000063a
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#define MSR_PP0_PERF_STATUS 0x0000063b
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#define MSR_PP1_POWER_LIMIT 0x00000640
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#define MSR_PP1_ENERGY_STATUS 0x00000641
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#define MSR_PP1_POLICY 0x00000642
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#define MSR_CORE_C1_RES 0x00000660
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#define MSR_AMD64_MC0_MASK 0xc0010044
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#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
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@ -123,18 +177,31 @@
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#define MSR_P6_EVNTSEL0 0x00000186
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#define MSR_P6_EVNTSEL1 0x00000187
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#define MSR_KNC_PERFCTR0 0x00000020
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#define MSR_KNC_PERFCTR1 0x00000021
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#define MSR_KNC_EVNTSEL0 0x00000028
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#define MSR_KNC_EVNTSEL1 0x00000029
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/* Alternative perfctr range with full access. */
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#define MSR_IA32_PMC0 0x000004c1
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/* AMD64 MSRs. Not complete. See the architecture manual for a more
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complete list. */
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#define MSR_AMD64_PATCH_LEVEL 0x0000008b
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#define MSR_AMD64_TSC_RATIO 0xc0000104
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#define MSR_AMD64_NB_CFG 0xc001001f
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#define MSR_AMD64_PATCH_LOADER 0xc0010020
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#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
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#define MSR_AMD64_OSVW_STATUS 0xc0010141
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#define MSR_AMD64_LS_CFG 0xc0011020
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#define MSR_AMD64_DC_CFG 0xc0011022
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#define MSR_AMD64_BU_CFG2 0xc001102a
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#define MSR_AMD64_IBSFETCHCTL 0xc0011030
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#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
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#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
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#define MSR_AMD64_IBSFETCH_REG_COUNT 3
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#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
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#define MSR_AMD64_IBSOPCTL 0xc0011033
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#define MSR_AMD64_IBSOPRIP 0xc0011034
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#define MSR_AMD64_IBSOPDATA 0xc0011035
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@ -142,12 +209,21 @@
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#define MSR_AMD64_IBSOPDATA3 0xc0011037
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#define MSR_AMD64_IBSDCLINAD 0xc0011038
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#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
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#define MSR_AMD64_IBSOP_REG_COUNT 7
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#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
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#define MSR_AMD64_IBSCTL 0xc001103a
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#define MSR_AMD64_IBSBRTARGET 0xc001103b
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#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
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/* Fam 16h MSRs */
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#define MSR_F16H_L2I_PERF_CTL 0xc0010230
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#define MSR_F16H_L2I_PERF_CTR 0xc0010231
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/* Fam 15h MSRs */
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#define MSR_F15H_PERF_CTL 0xc0010200
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#define MSR_F15H_PERF_CTR 0xc0010201
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#define MSR_F15H_NB_PERF_CTL 0xc0010240
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#define MSR_F15H_NB_PERF_CTR 0xc0010241
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/* Fam 10h MSRs */
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#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
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@ -226,7 +302,9 @@
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#define MSR_IA32_PLATFORM_ID 0x00000017
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#define MSR_IA32_EBL_CR_POWERON 0x0000002a
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#define MSR_EBC_FREQUENCY_ID 0x0000002c
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#define MSR_SMI_COUNT 0x00000034
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#define MSR_IA32_FEATURE_CONTROL 0x0000003a
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#define MSR_IA32_TSC_ADJUST 0x0000003b
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#define FEATURE_CONTROL_LOCKED (1<<0)
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#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
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@ -237,11 +315,16 @@
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#define MSR_IA32_APICBASE_ENABLE (1<<11)
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#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
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#define MSR_IA32_TSCDEADLINE 0x000006e0
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#define MSR_IA32_UCODE_WRITE 0x00000079
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#define MSR_IA32_UCODE_REV 0x0000008b
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#define MSR_IA32_PERF_STATUS 0x00000198
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#define MSR_IA32_PERF_CTL 0x00000199
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#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
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#define MSR_AMD_PERF_STATUS 0xc0010063
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#define MSR_AMD_PERF_CTL 0xc0010062
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#define MSR_IA32_MPERF 0x000000e7
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#define MSR_IA32_APERF 0x000000e8
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@ -267,6 +350,9 @@
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#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
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#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
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#define ENERGY_PERF_BIAS_PERFORMANCE 0
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#define ENERGY_PERF_BIAS_NORMAL 6
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#define ENERGY_PERF_BIAS_POWERSAVE 15
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#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
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@ -320,6 +406,8 @@
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#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
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#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
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#define MSR_IA32_TSC_DEADLINE 0x000006E0
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/* P4/Xeon+ specific */
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#define MSR_IA32_MCG_EAX 0x00000180
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#define MSR_IA32_MCG_EBX 0x00000181
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@ -446,7 +534,23 @@
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#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
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#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
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#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
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#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
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#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
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#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
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#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
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#define MSR_IA32_VMX_VMFUNC 0x00000491
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/* VMX_BASIC bits and bitmasks */
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#define VMX_BASIC_VMCS_SIZE_SHIFT 32
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#define VMX_BASIC_64 0x0001000000000000LLU
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#define VMX_BASIC_MEM_TYPE_SHIFT 50
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#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
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#define VMX_BASIC_MEM_TYPE_WB 6LLU
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#define VMX_BASIC_INOUT 0x0040000000000000LLU
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/* MSR_IA32_VMX_MISC bits */
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#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
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#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
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/* AMD-V MSRs */
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#define MSR_VM_CR 0xc0010114
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