spi: rk: Limit transfers to (64K - 1) bytes
The Rockchip SPI controller's length register only supports 16-bits, yielding a maximum length of 64KiB (the CTRLR1 register holds "length - 1"). Trying to transfer more than that (e.g., with a large SPI flash read) will cause the driver to hang. Now, it seems that while theoretically we should be able to program CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to cause the core to choke, so stick with a maximum of 64K - 1 bytes -- i.e., 0xffff. Note, that the size is further divided into 'minus 1' while writing into CTRLR1. This change fixed two different read issues, 1. sf read failure when with > 0x10000 2. Boot from SPI flash failed during spi_flash_read call in common/spl/spl_spi.c Observed and Tested in - Rockpro64 with Gigadevice flash - ROC-RK3399-PC with Winbond flash Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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@ -27,6 +27,12 @@
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/* Change to 1 to output registers at the start of each transaction */
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#define DEBUG_RK_SPI 0
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/*
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* ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However,
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* the controller seems to hang when given 0x10000, so stick with this for now.
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*/
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#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
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struct rockchip_spi_params {
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/* RXFIFO overruns and TXFIFO underruns stop the master clock */
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bool master_manages_fifo;
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@ -367,7 +373,7 @@ static inline int rockchip_spi_16bit_reader(struct udevice *dev,
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* represented in CTRLR1.
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*/
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if (data && data->master_manages_fifo)
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max_chunk_size = 0x10000;
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max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN;
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// rockchip_spi_configure(dev, mode, size)
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rkspi_enable_chip(regs, false);
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@ -451,7 +457,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
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/* This is the original 8bit reader/writer code */
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while (len > 0) {
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int todo = min(len, 0x10000);
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int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN);
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rkspi_enable_chip(regs, false);
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writel(todo - 1, ®s->ctrlr1);
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