reset: stm32: Add support of MCU HOLD BOOT
Handle the register RCC_MP_GCR without SET/CLR registers but with a direct access to bit BOOT_MCU: - deassert => set the bit: The MCU will not be in HOLD_BOOT - assert => clear the bit: The MCU will be set in HOLD_BOOT With this patch the RCC driver handles the MCU_HOLD_BOOT_R value added in binding stm32mp1-resets.h Cc: Fabien DESSENNE <fabien.dessenne@st.com> Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
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@ -14,6 +14,9 @@
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#include <asm/io.h>
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#include <linux/bitops.h>
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/* offset of register without set/clear management */
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#define RCC_MP_GCR_OFFSET 0x10C
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/* reset clear offset for STM32MP RCC */
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#define RCC_CL 0x4
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@ -40,8 +43,11 @@ static int stm32_reset_assert(struct reset_ctl *reset_ctl)
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reset_ctl->id, bank, offset);
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if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
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/* reset assert is done in rcc set register */
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writel(BIT(offset), priv->base + bank);
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if (bank != RCC_MP_GCR_OFFSET)
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/* reset assert is done in rcc set register */
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writel(BIT(offset), priv->base + bank);
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else
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clrbits_le32(priv->base + bank, BIT(offset));
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else
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setbits_le32(priv->base + bank, BIT(offset));
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@ -57,8 +63,11 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
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reset_ctl->id, bank, offset);
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if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
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/* reset deassert is done in rcc clr register */
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writel(BIT(offset), priv->base + bank + RCC_CL);
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if (bank != RCC_MP_GCR_OFFSET)
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/* reset deassert is done in rcc clr register */
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writel(BIT(offset), priv->base + bank + RCC_CL);
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else
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setbits_le32(priv->base + bank, BIT(offset));
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else
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clrbits_le32(priv->base + bank, BIT(offset));
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@ -7,6 +7,7 @@
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#ifndef _DT_BINDINGS_STM32MP1_RESET_H_
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#define _DT_BINDINGS_STM32MP1_RESET_H_
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#define MCU_HOLD_BOOT_R 2144
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#define LTDC_R 3072
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#define DSI_R 3076
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#define DDRPERFM_R 3080
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