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rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 64bit)

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Create a non-cacheable mapping for the 0x600000000 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
This commit is contained in:
Marek Szyprowski 2020-05-25 13:39:55 +02:00 committed by Matthias Brugger
parent c44b3f523c
commit d69ddf2494
1 changed files with 15 additions and 3 deletions
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18
arch/arm/mach-bcm283x/init.c
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@ -12,10 +12,15 @@
#include <dm/device.h>
#include <fdt_support.h>
#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL
#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL
#ifdef CONFIG_ARM64
#include <asm/armv8/mmu.h>
static struct mm_region bcm283x_mem_map[] = {
#define MEM_MAP_MAX_ENTRIES (4)
static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = {
{
.virt = 0x00000000UL,
.phys = 0x00000000UL,
@ -35,7 +40,7 @@ static struct mm_region bcm283x_mem_map[] = {
}
};
static struct mm_region bcm2711_mem_map[] = {
static struct mm_region bcm2711_mem_map[MEM_MAP_MAX_ENTRIES] = {
{
.virt = 0x00000000UL,
.phys = 0x00000000UL,
@ -49,6 +54,13 @@ static struct mm_region bcm2711_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
.phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
.size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
@ -72,7 +84,7 @@ static void _rpi_update_mem_map(struct mm_region *pd)
{
int i;
for (i = 0; i < 2; i++) {
for (i = 0; i < MEM_MAP_MAX_ENTRIES; i++) {
mem_map[i].virt = pd[i].virt;
mem_map[i].phys = pd[i].phys;
mem_map[i].size = pd[i].size;