ram: rockchip: add common code for sdram driver
There are some function like os_reg setting, capacity detect functions, can be used as common code for different Rockchip SoCs, add a sdram_common.c for all these functions. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang
parent
c7becc3a2b
commit
d6647b08b2
@ -6,6 +6,15 @@
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#ifndef _ASM_ARCH_SDRAM_COMMON_H
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#define _ASM_ARCH_SDRAM_COMMON_H
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#ifndef MHZ
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#define MHZ (1000 * 1000)
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#endif
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#define PATTERN (0x5aa5f00f)
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#define MIN(a, b) (((a) > (b)) ? (b) : (a))
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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struct sdram_cap_info {
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unsigned int rank;
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/* dram column number, 0 means this channel is invalid */
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@ -125,4 +134,26 @@ void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
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void sdram_print_stride(unsigned int stride);
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#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
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void sdram_org_config(struct sdram_cap_info *cap_info,
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struct sdram_base_params *base,
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u32 *p_os_reg2, u32 *p_os_reg3, u32 channel);
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int sdram_detect_bw(struct sdram_cap_info *cap_info);
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int sdram_detect_cs(struct sdram_cap_info *cap_info);
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int sdram_detect_col(struct sdram_cap_info *cap_info,
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u32 coltmp);
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int sdram_detect_bank(struct sdram_cap_info *cap_info,
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u32 coltmp, u32 bktmp);
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int sdram_detect_bg(struct sdram_cap_info *cap_info,
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u32 coltmp);
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int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type);
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int sdram_detect_row(struct sdram_cap_info *cap_info,
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u32 coltmp, u32 bktmp, u32 rowtmp);
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int sdram_detect_row_3_4(struct sdram_cap_info *cap_info,
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u32 coltmp, u32 bktmp);
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int sdram_detect_high_row(struct sdram_cap_info *cap_info);
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int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type);
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u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type);
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void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n);
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#endif
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@ -5,6 +5,12 @@ config RAM_ROCKCHIP
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help
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This enables support for ram drivers Rockchip SoCs.
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config ROCKCHIP_SDRAM_COMMON
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bool "Enable rockchip sdram common driver"
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depends on TPL_RAM || SPL_RAM
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help
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This enable sdram common driver
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if RAM_ROCKCHIP
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config RAM_ROCKCHIP_DEBUG
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@ -11,3 +11,4 @@ obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
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obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
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obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o
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obj-$(CONFIG_RAM_RK3399) += sdram_rk3399.o
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obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o
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285
drivers/ram/rockchip/sdram_common.c
Normal file
285
drivers/ram/rockchip/sdram_common.c
Normal file
@ -0,0 +1,285 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2018 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <ram.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/sdram.h>
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#include <asm/arch-rockchip/sdram_common.h>
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/* n: Unit bytes */
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void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n)
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{
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int i;
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for (i = 0; i < n / sizeof(u32); i++) {
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writel(*src, dest);
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src++;
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dest++;
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}
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}
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void sdram_org_config(struct sdram_cap_info *cap_info,
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struct sdram_base_params *base,
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u32 *p_os_reg2, u32 *p_os_reg3, u32 channel)
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{
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*p_os_reg2 |= SYS_REG_ENC_DDRTYPE(base->dramtype);
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*p_os_reg2 |= SYS_REG_ENC_NUM_CH(base->num_channels);
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*p_os_reg2 |= SYS_REG_ENC_ROW_3_4(cap_info->row_3_4, channel);
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*p_os_reg2 |= SYS_REG_ENC_CHINFO(channel);
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*p_os_reg2 |= SYS_REG_ENC_RANK(cap_info->rank, channel);
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*p_os_reg2 |= SYS_REG_ENC_COL(cap_info->col, channel);
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*p_os_reg2 |= SYS_REG_ENC_BK(cap_info->bk, channel);
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*p_os_reg2 |= SYS_REG_ENC_BW(cap_info->bw, channel);
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*p_os_reg2 |= SYS_REG_ENC_DBW(cap_info->dbw, channel);
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SYS_REG_ENC_CS0_ROW(cap_info->cs0_row, *p_os_reg2, *p_os_reg3, channel);
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if (cap_info->cs1_row)
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SYS_REG_ENC_CS1_ROW(cap_info->cs1_row, *p_os_reg2,
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*p_os_reg3, channel);
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*p_os_reg3 |= SYS_REG_ENC_CS1_COL(cap_info->col, channel);
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*p_os_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
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}
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int sdram_detect_bw(struct sdram_cap_info *cap_info)
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{
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return 0;
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}
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int sdram_detect_cs(struct sdram_cap_info *cap_info)
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{
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return 0;
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}
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int sdram_detect_col(struct sdram_cap_info *cap_info,
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u32 coltmp)
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{
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void __iomem *test_addr;
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u32 col;
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u32 bw = cap_info->bw;
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for (col = coltmp; col >= 9; col -= 1) {
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writel(0, CONFIG_SYS_SDRAM_BASE);
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test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
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(1ul << (col + bw - 1ul)));
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writel(PATTERN, test_addr);
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if ((readl(test_addr) == PATTERN) &&
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(readl(CONFIG_SYS_SDRAM_BASE) == 0))
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break;
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}
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if (col == 8) {
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printascii("col error\n");
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return -1;
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}
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cap_info->col = col;
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return 0;
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}
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int sdram_detect_bank(struct sdram_cap_info *cap_info,
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u32 coltmp, u32 bktmp)
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{
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void __iomem *test_addr;
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u32 bk;
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u32 bw = cap_info->bw;
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test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
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(1ul << (coltmp + bktmp + bw - 1ul)));
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writel(0, CONFIG_SYS_SDRAM_BASE);
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writel(PATTERN, test_addr);
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if ((readl(test_addr) == PATTERN) &&
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(readl(CONFIG_SYS_SDRAM_BASE) == 0))
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bk = 3;
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else
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bk = 2;
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cap_info->bk = bk;
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return 0;
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}
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/* detect bg for ddr4 */
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int sdram_detect_bg(struct sdram_cap_info *cap_info,
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u32 coltmp)
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{
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void __iomem *test_addr;
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u32 dbw;
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u32 bw = cap_info->bw;
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test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
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(1ul << (coltmp + bw + 1ul)));
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writel(0, CONFIG_SYS_SDRAM_BASE);
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writel(PATTERN, test_addr);
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if ((readl(test_addr) == PATTERN) &&
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(readl(CONFIG_SYS_SDRAM_BASE) == 0))
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dbw = 0;
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else
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dbw = 1;
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cap_info->dbw = dbw;
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return 0;
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}
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/* detect dbw for ddr3,lpddr2,lpddr3,lpddr4 */
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int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type)
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{
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u32 row, col, bk, bw, cs_cap, cs;
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u32 die_bw_0 = 0, die_bw_1 = 0;
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if (dram_type == DDR3 || dram_type == LPDDR4) {
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cap_info->dbw = 1;
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} else if (dram_type == LPDDR3 || dram_type == LPDDR2) {
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row = cap_info->cs0_row;
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col = cap_info->col;
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bk = cap_info->bk;
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cs = cap_info->rank;
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bw = cap_info->bw;
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cs_cap = (1 << (row + col + bk + bw - 20));
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if (bw == 2) {
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if (cs_cap <= 0x2000000) /* 256Mb */
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die_bw_0 = (col < 9) ? 2 : 1;
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else if (cs_cap <= 0x10000000) /* 2Gb */
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die_bw_0 = (col < 10) ? 2 : 1;
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else if (cs_cap <= 0x40000000) /* 8Gb */
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die_bw_0 = (col < 11) ? 2 : 1;
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else
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die_bw_0 = (col < 12) ? 2 : 1;
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if (cs > 1) {
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row = cap_info->cs1_row;
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cs_cap = (1 << (row + col + bk + bw - 20));
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if (cs_cap <= 0x2000000) /* 256Mb */
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die_bw_0 = (col < 9) ? 2 : 1;
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else if (cs_cap <= 0x10000000) /* 2Gb */
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die_bw_0 = (col < 10) ? 2 : 1;
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else if (cs_cap <= 0x40000000) /* 8Gb */
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die_bw_0 = (col < 11) ? 2 : 1;
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else
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die_bw_0 = (col < 12) ? 2 : 1;
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}
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} else {
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die_bw_1 = 1;
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die_bw_0 = 1;
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}
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cap_info->dbw = (die_bw_0 > die_bw_1) ? die_bw_0 : die_bw_1;
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}
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return 0;
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}
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int sdram_detect_row(struct sdram_cap_info *cap_info,
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u32 coltmp, u32 bktmp, u32 rowtmp)
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{
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u32 row;
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u32 bw = cap_info->bw;
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void __iomem *test_addr;
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for (row = rowtmp; row > 12; row--) {
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writel(0, CONFIG_SYS_SDRAM_BASE);
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test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
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(1ul << (row + bktmp + coltmp + bw - 1ul)));
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writel(PATTERN, test_addr);
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if ((readl(test_addr) == PATTERN) &&
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(readl(CONFIG_SYS_SDRAM_BASE) == 0))
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break;
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}
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if (row == 12) {
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printascii("row error");
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return -1;
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}
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cap_info->cs0_row = row;
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return 0;
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}
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int sdram_detect_row_3_4(struct sdram_cap_info *cap_info,
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u32 coltmp, u32 bktmp)
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{
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u32 row_3_4;
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u32 bw = cap_info->bw;
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u32 row = cap_info->cs0_row;
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void __iomem *test_addr, *test_addr1;
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test_addr = CONFIG_SYS_SDRAM_BASE;
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test_addr1 = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
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(0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul)));
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writel(0, test_addr);
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writel(PATTERN, test_addr1);
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if ((readl(test_addr) == 0) && (readl(test_addr1) == PATTERN))
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row_3_4 = 0;
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else
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row_3_4 = 1;
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cap_info->row_3_4 = row_3_4;
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return 0;
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}
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int sdram_detect_high_row(struct sdram_cap_info *cap_info)
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{
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cap_info->cs0_high16bit_row = cap_info->cs0_row;
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cap_info->cs1_high16bit_row = cap_info->cs1_row;
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return 0;
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}
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int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type)
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{
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void __iomem *test_addr;
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u32 row = 0, bktmp, coltmp, bw;
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ulong cs0_cap;
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u32 byte_mask;
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if (cap_info->rank == 2) {
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cs0_cap = sdram_get_cs_cap(cap_info, 0, dram_type);
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if (dram_type == DDR4) {
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if (cap_info->dbw == 0)
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bktmp = cap_info->bk + 2;
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else
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bktmp = cap_info->bk + 1;
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} else {
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bktmp = cap_info->bk;
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}
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bw = cap_info->bw;
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coltmp = cap_info->col;
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/*
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* because px30 support axi split,min bandwidth
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* is 8bit. if cs0 is 32bit, cs1 may 32bit or 16bit
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* so we check low 16bit data when detect cs1 row.
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* if cs0 is 16bit/8bit, we check low 8bit data.
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*/
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if (bw == 2)
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byte_mask = 0xFFFF;
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else
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byte_mask = 0xFF;
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/* detect cs1 row */
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for (row = cap_info->cs0_row; row > 12; row--) {
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test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
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cs0_cap +
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(1ul << (row + bktmp + coltmp + bw - 1ul)));
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writel(0, CONFIG_SYS_SDRAM_BASE + cs0_cap);
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writel(PATTERN, test_addr);
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if (((readl(test_addr) & byte_mask) ==
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(PATTERN & byte_mask)) &&
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((readl(CONFIG_SYS_SDRAM_BASE + cs0_cap) &
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byte_mask) == 0)) {
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break;
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}
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}
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}
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cap_info->cs1_row = row;
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return 0;
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}
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