From 605714f66998e02cbe3666139a48d83e85fcdc0f Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Mon, 19 May 2014 15:08:14 +0800 Subject: [PATCH 01/20] powerpc/85xx: add fdt_fixup_dma3 On some SoC(e.g. T2080/T4240) the 3rd DMA is not functional if SRIO2 is chosen. we add fdt_fixup_dma3() to disable the 3rd DMA if SRIO2 is chosen. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/fdt.c | 47 ++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 85dfa5bc01..3665ec6b6c 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -612,6 +612,51 @@ static void fdt_fixup_usb(void *fdt) #define fdt_fixup_usb(x) #endif +#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T4240) || \ + defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) +void fdt_fixup_dma3(void *blob) +{ + /* the 3rd DMA is not functional if SRIO2 is chosen */ + int nodeoff; + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + +#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300) +#if defined(CONFIG_PPC_T2080) + u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + + switch (srds_prtcl_s2) { + case 0x29: + case 0x2d: + case 0x2e: +#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) + u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS4_PRTCL; + srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; + + switch (srds_prtcl_s4) { + case 6: + case 8: + case 14: + case 16: +#endif + nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma", + CONFIG_SYS_ELO3_DMA3); + if (nodeoff > 0) + fdt_status_disabled(blob, nodeoff); + else + printf("WARNING: unable to disable dma3\n"); + break; + default: + break; + } +} +#else +#define fdt_fixup_dma3(x) +#endif + #if defined(CONFIG_PPC_T1040) static void fdt_fixup_l2_switch(void *blob) { @@ -778,6 +823,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_usb(blob); fdt_fixup_l2_switch(blob); + + fdt_fixup_dma3(blob); } /* From 1155d8d853ff8639062651a903ae3062f483dc70 Mon Sep 17 00:00:00 2001 From: Rotariu Marian-Cristian Date: Mon, 19 May 2014 10:59:52 +0300 Subject: [PATCH 02/20] net/fm: call fm_port_to_index() with proper checks Some of the fm_port_to_index() callers did not check for -1 return value and used -1 as an array index. Signed-off-by: Marian Rotariu Reviewed-by: York Sun --- drivers/net/fm/fm.h | 3 ++- drivers/net/fm/init.c | 6 ++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h index 43de114b52..316e06e17e 100644 --- a/drivers/net/fm/fm.h +++ b/drivers/net/fm/fm.h @@ -143,6 +143,7 @@ struct fm_eth { #define MAX_RXBUF_LOG2 11 #define MAX_RXBUF_LEN (1 << MAX_RXBUF_LOG2) -#define PORT_IS_ENABLED(port) fm_info[fm_port_to_index(port)].enabled +#define PORT_IS_ENABLED(port) (fm_port_to_index(port) == -1 ? \ + 0 : fm_info[fm_port_to_index(port)].enabled) #endif /* __FM_H__ */ diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index cd787f4eed..ff04695c32 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -147,6 +147,9 @@ void fm_disable_port(enum fm_port port) { int i = fm_port_to_index(port); + if (i == -1) + return; + fm_info[i].enabled = 0; fman_disable_port(port); } @@ -155,6 +158,9 @@ void fm_enable_port(enum fm_port port) { int i = fm_port_to_index(port); + if (i == -1) + return; + fm_info[i].enabled = 1; fman_enable_port(port); } From 09c2046ff651a0d47bb2834d775991ba2c607130 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 21 May 2014 13:26:17 +0800 Subject: [PATCH 03/20] board/t2080qds: enable sst and eon spi flash for nor boot Remove unnecessary condition CONFIG_RAMBOOT_PBL to have SST and EON SPI flash work in case of NOR boot. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- include/configs/T208xQDS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 59d142e97e..9b81ff70eb 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -537,7 +537,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_SPI_FLASH #define CONFIG_FSL_ESPI #define CONFIG_SPI_FLASH_STMICRO -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_RAMBOOT_PBL) +#ifndef CONFIG_SPL_BUILD #define CONFIG_SPI_FLASH_SST #define CONFIG_SPI_FLASH_EON #endif From 38d67a4e552ac991f21c2d3e442a38fb0098fda6 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Tue, 3 Jun 2014 16:27:07 +0800 Subject: [PATCH 04/20] qe: move immap_qe.h from arch directory into common directory ls1021 is arm-core and supports qe too. Move immap_qe.h into common directory for both arm and powerpc. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- arch/powerpc/cpu/mpc83xx/cpu.c | 2 +- arch/powerpc/cpu/mpc83xx/fdt.c | 2 +- drivers/bootcount/bootcount.c | 2 +- drivers/qe/qe.c | 2 +- drivers/qe/uccf.c | 2 +- drivers/qe/uccf.h | 2 +- drivers/qe/uec.c | 2 +- drivers/qe/uec_phy.c | 2 +- {arch/powerpc/include/asm => include/linux}/immap_qe.h | 0 include/post.h | 2 +- 10 files changed, 9 insertions(+), 9 deletions(-) rename {arch/powerpc/include/asm => include/linux}/immap_qe.h (100%) diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index e41988d5fa..38093097e4 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -20,7 +20,7 @@ #include #include #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x) -#include +#include #include #endif diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index 450a9704e5..f249a585ed 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_BOOTCOUNT_LIMIT) && \ (defined(CONFIG_QE) && !defined(CONFIG_MPC831x)) -#include +#include void fdt_fixup_muram (void *blob) { diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c index 3ad441393e..e0343f71d7 100644 --- a/drivers/bootcount/bootcount.c +++ b/drivers/bootcount/bootcount.c @@ -36,7 +36,7 @@ #endif /* defined(CONFIG_MPC8260) */ #if defined(CONFIG_QE) -#include +#include #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \ QE_MURAM_SIZE - 2 * sizeof(u32)) diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 9c5fbd1d69..be09a17297 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -11,7 +11,7 @@ #include #include "asm/errno.h" #include "asm/io.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" #include "qe.h" #define MPC85xx_DEVDISR_QE_DISABLE 0x1 diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c index 593d96d1a2..85386bfc70 100644 --- a/drivers/qe/uccf.c +++ b/drivers/qe/uccf.c @@ -11,7 +11,7 @@ #include "malloc.h" #include "asm/errno.h" #include "asm/io.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" #include "qe.h" #include "uccf.h" diff --git a/drivers/qe/uccf.h b/drivers/qe/uccf.h index 0b57e2f422..55941e4601 100644 --- a/drivers/qe/uccf.h +++ b/drivers/qe/uccf.h @@ -12,7 +12,7 @@ #include "common.h" #include "qe.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" /* Fast or Giga ethernet */ diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 68045733b8..c91f084a7c 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -11,7 +11,7 @@ #include "malloc.h" #include "asm/errno.h" #include "asm/io.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" #include "qe.h" #include "uccf.h" #include "uec.h" diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 5dc4641bf6..e701787c41 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -14,7 +14,7 @@ #include "net.h" #include "malloc.h" #include "asm/errno.h" -#include "asm/immap_qe.h" +#include "linux/immap_qe.h" #include "asm/io.h" #include "qe.h" #include "uccf.h" diff --git a/arch/powerpc/include/asm/immap_qe.h b/include/linux/immap_qe.h similarity index 100% rename from arch/powerpc/include/asm/immap_qe.h rename to include/linux/immap_qe.h diff --git a/include/post.h b/include/post.h index 24ca728b40..5ebd535823 100644 --- a/include/post.h +++ b/include/post.h @@ -38,7 +38,7 @@ #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) #elif defined(CONFIG_MPC8360) -#include +#include #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) #elif defined (CONFIG_MPC85xx) From d43a386a91379816a6c26458daf3de92cc901b52 Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Thu, 5 Jun 2014 19:12:03 +0530 Subject: [PATCH 05/20] powerpc/mpc85xx: Removed support for G4060 G4060 has no PA cores, hence removing its support. Signed-off-by: Sandeep Singh Reviewed-by: York Sun --- arch/powerpc/cpu/mpc8xxx/cpu.c | 1 - arch/powerpc/include/asm/processor.h | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 15561a1533..84fec5ed28 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -65,7 +65,6 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(T4080, T4080, 4), CPU_TYPE_ENTRY(B4860, B4860, 0), CPU_TYPE_ENTRY(G4860, G4860, 0), - CPU_TYPE_ENTRY(G4060, G4060, 0), CPU_TYPE_ENTRY(B4440, B4440, 0), CPU_TYPE_ENTRY(B4460, B4460, 0), CPU_TYPE_ENTRY(G4440, G4440, 0), diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index a5e7a612bf..2445acd69d 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1118,7 +1118,6 @@ #define SVR_B4860 0X868000 #define SVR_G4860 0x868001 #define SVR_B4460 0x868003 -#define SVR_G4060 0x868003 #define SVR_B4440 0x868100 #define SVR_G4440 0x868101 #define SVR_B4420 0x868102 From d0bc51407cb1a10bdc0025fb58524c6d13658b83 Mon Sep 17 00:00:00 2001 From: Lijun Pan Date: Fri, 6 Jun 2014 15:13:58 -0500 Subject: [PATCH 06/20] powerpc/mpc85xx: Remove P1023 RDS support Since P1023RDS is no longer supported/manufactured by Freescale, we clean up P1023RDS related code. Since P1023RDB is still supported by Freescale, we keep P1023RDB releated code. Signed-off-by: Lijun Pan Reviewed-by: York Sun --- board/freescale/p1023rds/Makefile | 9 - board/freescale/p1023rds/README | 101 ------ board/freescale/p1023rds/bcsr.h | 49 --- board/freescale/p1023rds/law.c | 19 -- board/freescale/p1023rds/p1023rds.c | 191 ----------- board/freescale/p1023rds/tlb.c | 100 ------ boards.cfg | 1 - include/configs/P1023RDS.h | 479 ---------------------------- 8 files changed, 949 deletions(-) delete mode 100644 board/freescale/p1023rds/Makefile delete mode 100644 board/freescale/p1023rds/README delete mode 100644 board/freescale/p1023rds/bcsr.h delete mode 100644 board/freescale/p1023rds/law.c delete mode 100644 board/freescale/p1023rds/p1023rds.c delete mode 100644 board/freescale/p1023rds/tlb.c delete mode 100644 include/configs/P1023RDS.h diff --git a/board/freescale/p1023rds/Makefile b/board/freescale/p1023rds/Makefile deleted file mode 100644 index fdbf365ea5..0000000000 --- a/board/freescale/p1023rds/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright 2010-2011 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += p1023rds.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/p1023rds/README b/board/freescale/p1023rds/README deleted file mode 100644 index d382551c4d..0000000000 --- a/board/freescale/p1023rds/README +++ /dev/null @@ -1,101 +0,0 @@ -Overview --------- -The P1023 process includes a performance optimized implementation of the -QorIQ data Path Acceleration Architecture (DPAA). This architecture -provides the infrastructure to support simplified sharing of networking -interfaces and accelerators by multiple CPU cores. P1023 is an e500 based -dual core SOC. - -P1023RDS board is a Low End Dual core platform supporting the P1023 -processor of QorIQ series. - -Building U-boot ---------------- -To build the u-boot for P1023RDS: -Configure to NOR boot: - make P1023RDS_config -Configure to NAND boot: - make P1023RDS_NAND_config -Build: - make - -Board Switches --------------- -Most switches on the board should not be changed. The most frequent -user-settable switches on the board are used to configure -the flash banks. - -J4: all open - -Default NOR flash boot switch setting: - Sw3[1:8]: off on on off on on off off - Sw4[1:8]: off off off on off off off off - Sw6[1:8]: off on off on off on on off - Sw7[1:8]: off on off off on off off off - Sw8[1:8]: on off off off off off off off - -For NAND flash boot,set -Sw4[1:4]: off on on on - -The default native ethernet setting is for RGMII mode. -To use SGMII mode, set -SW8[1:2]: OFF OFF -SW7[6:7]: ON ON - -Memory Map ----------- -0x0000_0000 0x7fff_ffff DDR 2G Cacheable -0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable -0xc000_0000 0xdfff_ffff PCI 512M non-cacheable -0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable - -0xe000_0000 0xe003_ffff BCSR 256K BCSR -0xee00_0000 0xefff_ffff NOR flash 32M NOR flash -0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M -0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable -0xffa0_0000 0xffaf_ffff NAND FLASH 1M non-cacheable -0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - -Flashing u-boot Images ---------------- -To program the image in the boot flash bank: -NOR flash boot: - => tftp 1000000 u-boot.bin - => protect off all - => erase eff40000 efffffff - => cp.b 1000000 eff40000 c0000 - -NAND flash boot: - => tftp 1000000 u-boot-nand.bin - => nand erase 0 80000 - => nand write 1000000 0 80000 - -Firmware ucode location ---------------------------------- -Microcode(ucode) to FMAN's IRAM is needed to make FMAN Ethernet work. -u-boot loads ucode FLASH. The location for ucode: -NOR Flash: 0xfe000000 -NAND Flash: 0x1f00000 - -Using the Device Tree Source File ---------------------------------- -To create the DTB (Device Tree Binary) image file, -use a command similar to this: - - dtc -b 0 -f -I dts -O dtb p1023rds.dts > p1023rds.dtb - -Likely, that .dts file will come from here; - - linux-2.6/arch/powerpc/boot/dts/p1023rds.dts -or - make p1023rds.dtb ARCH=powerpc -in linux-2.6 directory. - -Booting Linux -------------- -Place a linux uImage in the TFTP disk area. - - tftp 1000000 uImage - tftp 2000000 rootfs.ext2.gz.uboot - tftp c00000 p1023rds.dtb - bootm 1000000 2000000 c00000 diff --git a/board/freescale/p1023rds/bcsr.h b/board/freescale/p1023rds/bcsr.h deleted file mode 100644 index a9deb72f78..0000000000 --- a/board/freescale/p1023rds/bcsr.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * - * Authors: Chunhe Lan - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __BCSR_H_ -#define __BCSR_H_ - -#include - -/* - * BCSR Bit definitions - * BCSR 15 * - 0 device insertion oriention - 1 stack processor present - 2 power supply shut down/normal operation - 3 I2C bus0 drive enable - 4 reserved - 5:7 I2C bus0 select - 5 - I2C_BUS_0_SS0 - 6 - I2C_BUS_0_SS1 - 7 - I2C_BUS_0_SS2 -*/ - -/* BCSR register base address is 0xFX000020 */ -#define BCSR_BASE_REG_OFFSET 0x20 -#define BCSR_ACCESS_REG_ADDR (CONFIG_SYS_BCSR_BASE + BCSR_BASE_REG_OFFSET) - -#define BCSR15_DEV_INS_ORI 0x80 -#define BCSR15_STACK_PRO_PRE 0x40 -#define BCSR15_POWER_SUPPLY 0x20 -#define BCSR15_I2C_BUS0_EN 0x10 -#define BCSR15_I2C_BUS0_SEG0 0x00 -#define BCSR15_I2C_BUS0_SEG1 0x04 -#define BCSR15_I2C_BUS0_SEG2 0x02 -#define BCSR15_I2C_BUS0_SEG3 0x06 -#define BCSR15_I2C_BUS0_SEG4 0x01 -#define BCSR15_I2C_BUS0_SEG5 0x05 -#define BCSR15_I2C_BUS0_SEG6 0x03 -#define BCSR15_I2C_BUS0_SEG7 0x07 -#define BCSR15_I2C_BUS0_SEG_CLR 0x07 -#define BCSR19_SGMII_SEL_L 0x01 - -/*BCSR Utils functions*/ -void fixup_i2c_bus0_sel_seg0(void); -#endif /* __BCSR_H_ */ diff --git a/board/freescale/p1023rds/law.c b/board/freescale/p1023rds/law.c deleted file mode 100644 index 92f5a3fcb5..0000000000 --- a/board/freescale/p1023rds/law.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M, - LAW_TRGT_IF_DPAA_SWP_SRAM), - /* The LAW 0xe0000000 ~ 0xefffffff for BCSR and NOR flash */ - SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c deleted file mode 100644 index 2b883c719e..0000000000 --- a/board/freescale/p1023rds/p1023rds.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * - * Authors: Roy Zang - * Chunhe Lan - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "bcsr.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - fsl_lbc_t *lbc = LBC_BASE_ADDR; - - /* Set ABSWP to implement conversion of addresses in the LBC */ - setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); - - return 0; -} - -int checkboard(void) -{ - u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR; - - printf("Board: P1023 RDS\n"); - - clrbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG_CLR); - setbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG0); - - return 0; -} - -/* Fixed sdram init -- doesn't use serial presence detect. */ -phys_size_t fixed_sdram(void) -{ -#ifndef CONFIG_SYS_RAMBOOT - struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; - - set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); - - out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); - out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); - out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); - out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); - out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); - out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); - out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); - out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); - out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2); - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); -#endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024ul; -} - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_BCSR_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + BCSR region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash + bcsr */ - disable_tlb(flash_esel); - - set_tlb(1, flashbase, CONFIG_SYS_BCSR_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - setup_portals(); - - return 0; -} - -unsigned long get_board_sys_clk(ulong dummy) -{ - return gd->bus_clk; -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - return gd->mem_clk; -} - -int board_eth_init(bd_t *bis) -{ - u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR; - ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - struct fsl_pq_mdio_info dtsec_mdio_info; - - /* - * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting - * is not correct. - */ - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - - fm_info_set_mdio(FM1_DTSEC1, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - fm_info_set_mdio(FM1_DTSEC2, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - - /* Make SERDES connected to SGMII by cleaing bcsr19[7] */ - if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII) - clrbits_8(&bcsr[19], BCSR19_SGMII_SEL_L); - -#ifdef CONFIG_FMAN_ENET - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = getenv_bootm_low(); - size = getenv_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_HAS_FSL_DR_USB - fdt_fixup_dr_usb(blob, bd); -#endif - - fdt_fixup_fman_ethernet(blob); -} -#endif diff --git a/board/freescale/p1023rds/tlb.c b/board/freescale/p1023rds/tlb.c deleted file mode 100644 index 3c92c14ae3..0000000000 --- a/board/freescale/p1023rds/tlb.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_4M, 1), - - /* *W*G* - BCSR and NOR flash on local bus*/ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 9, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_1M, 1), - - /* *I*G - NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 11, BOOKE_PAGESZ_1M, 1), - -#ifdef CONFIG_SYS_RAMBOOT - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, - CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 12, BOOKE_PAGESZ_1G, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 13, BOOKE_PAGESZ_1G, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 4b2bc19a95..110dd9d9aa 100644 --- a/boards.cfg +++ b/boards.cfg @@ -830,7 +830,6 @@ Active powerpc mpc85xx - freescale p1022ds Active powerpc mpc85xx - freescale p1022ds P1022DS_SDCARD P1022DS:SDCARD Timur Tabi Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi Active powerpc mpc85xx - freescale p1023rdb P1023RDB - - -Active powerpc mpc85xx - freescale p1023rds P1023RDS - Roy Zang Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB - Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT - Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SDCARD P1_P2_RDB:P1011RDB,36BIT,SDCARD - diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h deleted file mode 100644 index ac75b9c5fb..0000000000 --- a/include/configs/P1023RDS.h +++ /dev/null @@ -1,479 +0,0 @@ -/* - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * - * Authors: Roy Zang - * Chunhe Lan - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * p1023rds board configuration file - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff40000 -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -/* High Level Configuration Options */ -#define CONFIG_BOOKE /* BOOKE */ -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_P1023 -#define CONFIG_P1023RDS -#define CONFIG_MP /* support multiple processors */ - -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ -#define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ -#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_FSL_LAW /* Use common FSL init code */ - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif - -#define CONFIG_SYS_CLK_FREQ 66666666 -#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_HWCONFIG - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff /* fix me, only 1G */ -#define CONFIG_PANIC_HANG /* do not reset board on panic */ - -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* Implement conversion of - addresses in the LBC */ - -/* DDR Setup */ -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 2048u /* DDR is 2GB */ - -/* Default settings for "stable" mode */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x40110104 -#define CONFIG_SYS_DDR_TIMING_1 0x5C59E544 -#define CONFIG_SYS_DDR_TIMING_2 0x0fA888CA -#define CONFIG_SYS_DDR_MODE_1 0x00441210 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x0A280100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x01800000 -#define CONFIG_SYS_DDR_TIMING_4 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5 0x01401400 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F605 -#define CONFIG_SYS_DDR_CONTROL 0xC70C0008 /* Type = DDR3: No Interleaving */ -#define CONFIG_SYS_DDR_CONTROL2 0x24401010 -#define CONFIG_SYS_DDR_CDR1 0x00000000 -#define CONFIG_SYS_DDR_CDR2 0x00000000 - -#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00000000 - -/* Settings that differ for "performance" mode */ -#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ -#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ -#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014302 -#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5C58E544 -#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0FA888CA -/* Type = DDR3: cs0-cs1 interleaving */ -#define CONFIG_SYS_DDR_CONTROL_PERF 0xC70C4008 -#define CONFIG_SYS_DDR_CDR_1 0x00000000 -#define CONFIG_SYS_DDR_CDR_2 0x00000000 - - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable - * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable - * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable - * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable - * - * Localbus non-cacheable - * 0xe000_0000 0xe003_ffff BCSR 256K BCSR - * 0xee00_0000 0xefff_ffff NOR flash 32M NOR flash - * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M - * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable - * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_BCSR_BASE 0xe0000000 /* start of on board FPGA */ -#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE - -#define CONFIG_SYS_FLASH_BASE 0xee000000 /* start of FLASH 32M */ - -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ - | BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#if defined(CONFIG_SYS_SPL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */ -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ - -#ifndef CONFIG_NAND_SPL -#define CONFIG_SYS_NAND_BASE 0xffa00000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#else -#define CONFIG_SYS_NAND_BASE 0xfff00000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif - -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_CMD_NAND -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) - -/* NAND boot: 4K NAND loader config */ -#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + CONFIG_SYS_NAND_SPL_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2< - -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NET -#endif - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI -#define CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#define CONFIG_USB_STORAGE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ - -#define CONFIG_BAUDRATE 115200 - -/* Qman/Bman */ -#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */ -#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 - -/* For FM */ -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_FMAN_ENET -#define CONFIG_PHY_MARVELL -#endif - -/* Default address of microcode for the Linux Fman driver */ -/* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 -#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x7 - -#define CONFIG_SYS_TBIPA_VALUE 8 -#define CONFIG_MII /* MII PHY management */ -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" - -#endif /* __CONFIG_H */ From 3bab3d8324874604501ff9154e68732fb986057a Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 12 Jun 2014 09:13:08 +0530 Subject: [PATCH 07/20] driver/nand:Define MAX_BANKS same as SoC defined for IFC The number of chip select used by IFC controller vary from one SoC to other. For eg. P1010 has 4, T4240 has 8. Update MAX_BANKS same as SoC defined Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- drivers/mtd/nand/fsl_ifc_nand.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index be5a16a1ba..27f5177d71 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -19,8 +19,12 @@ #include #include +#ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#endif + #define FSL_IFC_V1_1_0 0x01010000 -#define MAX_BANKS 4 +#define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ #define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC From 04818bbdc34cb02b2590af8e5f77118ed8a8d755 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 12 Jun 2014 12:14:00 +0530 Subject: [PATCH 08/20] driver/nand: Update SRAM initialize logic for IFC. IFC controller v1.1.0 requires internal SRAM initialize by reading NAND flash. Higher controller versions have provided "SRAM init" bit in NCFGR register space. update SRAM initialize logic to reflect the same. Also print error message in case of Page read error. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- drivers/mtd/nand/fsl_ifc_nand.c | 35 +++++++++++++++++++++++++++++---- include/fsl_ifc.h | 2 ++ 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 27f5177d71..280e14e24a 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -806,12 +806,30 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) { } -static void fsl_ifc_sram_init(void) +static int fsl_ifc_sram_init(uint32_t ver) { struct fsl_ifc *ifc = ifc_ctrl->regs; uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0; + uint32_t ncfgr = 0; long long end_tick; + if (ver > FSL_IFC_V1_1_0) { + ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr); + ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN); + + /* wait for SRAM_INIT bit to be clear or timeout */ + end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); + while (end_tick > get_ticks()) { + ifc_ctrl->status = + ifc_in32(&ifc->ifc_nand.nand_evter_stat); + + if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN)) + return 0; + } + printf("fsl-ifc: Failed to Initialise SRAM\n"); + return 1; + } + cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT; /* Save CSOR and CSOR_ext */ @@ -854,11 +872,18 @@ static void fsl_ifc_sram_init(void) break; } + if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) { + printf("fsl-ifc: Failed to Initialise SRAM\n"); + return 1; + } + ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); /* Restore CSOR and CSOR_ext */ ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); + + return 0; } static int fsl_ifc_chip_init(int devnum, u8 *addr) @@ -868,7 +893,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) struct fsl_ifc_mtd *priv; struct nand_ecclayout *layout; uint32_t cspr = 0, csor = 0, ver = 0; - int ret; + int ret = 0; if (!ifc_ctrl) { fsl_ifc_ctrl_init(); @@ -1010,8 +1035,10 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) } ver = ifc_in32(&ifc_ctrl->regs->ifc_rev); - if (ver == FSL_IFC_V1_1_0) - fsl_ifc_sram_init(); + if (ver >= FSL_IFC_V1_1_0) + ret = fsl_ifc_sram_init(ver); + if (ret) + return ret; ret = nand_scan_ident(mtd, 1, NULL); if (ret) diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 630e4b4999..b353b04c46 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -367,6 +367,8 @@ */ /* Auto Boot Mode */ #define IFC_NAND_NCFGR_BOOT 0x80000000 +/* SRAM INIT EN */ +#define IFC_NAND_SRAM_INIT_EN 0x20000000 /* Addressing Mode-ROW0+n/COL0 */ #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 /* Addressing Mode-ROW0+n/COL0+n */ From 32514d259bf37cc92872aeb0624b75f600e7fb3a Mon Sep 17 00:00:00 2001 From: Zang Roy-R61911 Date: Thu, 12 Jun 2014 14:49:23 -0500 Subject: [PATCH 09/20] fsl/pcie: Change 'no link' to 'undetermined' for pcie endpoint Even u-boot boots up, the pcie link may not setup correctly when Freescale SOC acts as endpoint. So change the link status from 'no link' to 'undetermined' to reduce the confusion. The link status can check from host side eventually. Signed-off-by: Roy Zang Reviewed-by: York Sun --- drivers/pci/fsl_pci_init.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 3a41b0ec17..231b07573f 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -504,8 +504,14 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) } #endif if (!enabled) { - /* Let the user know there's no PCIe link */ - printf("no link, regs @ 0x%lx\n", pci_info->regs); + /* Let the user know there's no PCIe link for root + * complex. for endpoint, the link may not setup, so + * print undetermined. + */ + if (fsl_is_pci_agent(hose)) + printf("undetermined, regs @ 0x%lx\n", pci_info->regs); + else + printf("no link, regs @ 0x%lx\n", pci_info->regs); hose->last_busno = hose->first_busno; return; } From 591dd192307d81cf8f8705b06854e973c53d4c4d Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Sat, 14 Jun 2014 08:48:19 +0530 Subject: [PATCH 10/20] driver/nand: Add support of 16K SRAM for IFC 2.0 Internal SRAM has been incresed from 8KB to 16KB for IFC cotroller ver 2.0. Update the page offset calculation logic to support the same. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- drivers/mtd/nand/fsl_ifc_nand.c | 4 +++- drivers/mtd/nand/fsl_ifc_spl.c | 6 +++++- include/fsl_ifc.h | 2 ++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 280e14e24a..8b453cb383 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -23,7 +23,6 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #endif -#define FSL_IFC_V1_1_0 0x01010000 #define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ @@ -1040,6 +1039,9 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) if (ret) return ret; + if (ver >= FSL_IFC_V2_0_0) + priv->bufnum_mask = (priv->bufnum_mask * 2) + 1; + ret = nand_scan_ident(mtd, 1, NULL); if (ret) return ret; diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index 510077282c..e336cb1c94 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -97,7 +97,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) int pages_per_blk; int blk_size; int bad_marker = 0; - int bufnum_mask, bufnum; + int bufnum_mask, bufnum, ver = 0; int csor, cspr; int pos = 0; @@ -130,6 +130,10 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) bad_marker = 5; } + ver = ifc_in32(&ifc->ifc_rev); + if (ver >= FSL_IFC_V2_0_0) + bufnum_mask = (bufnum_mask * 2) + 1; + pages_per_blk = 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT); diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index b353b04c46..11474b757c 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -12,6 +12,8 @@ #include #include +#define FSL_IFC_V1_1_0 0x01010000 +#define FSL_IFC_V2_0_0 0x02000000 #ifdef CONFIG_SYS_FSL_IFC_LE #define ifc_in32(a) in_le32(a) From 6666017f44e39ec0385e3c7736b8c9af46cf4f08 Mon Sep 17 00:00:00 2001 From: vijay rai Date: Fri, 20 Jun 2014 10:45:29 +0530 Subject: [PATCH 11/20] powerpc/t1040qds: Initialize EPHY2 clock to RGMII only Setting FPGA register brdcfg9 EPHY2 bits to '0' to initialize EPHY2 clock to RGMII mode. Signed-off-by: Vijay Rai Signed-off-by: Priyanka Jain Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- board/freescale/t1040qds/eth.c | 4 +++- board/freescale/t1040qds/t1040qds_qixis.h | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c index 3077b4ae2c..1929bba20b 100644 --- a/board/freescale/t1040qds/eth.c +++ b/board/freescale/t1040qds/eth.c @@ -355,7 +355,9 @@ static void set_brdcfg9_for_gtx_clk(void) { u8 brdcfg9; brdcfg9 = QIXIS_READ(brdcfg[9]); - brdcfg9 |= (1 << 5); +/* Initializing EPHY2 clock to RGMII mode */ + brdcfg9 &= ~(BRDCFG9_EPHY2_MASK); + brdcfg9 |= (BRDCFG9_EPHY2_VAL); QIXIS_WRITE(brdcfg[9], brdcfg9); } diff --git a/board/freescale/t1040qds/t1040qds_qixis.h b/board/freescale/t1040qds/t1040qds_qixis.h index 98d2d39e6d..cef8ad0bfa 100644 --- a/board/freescale/t1040qds/t1040qds_qixis.h +++ b/board/freescale/t1040qds/t1040qds_qixis.h @@ -17,6 +17,10 @@ #define BRDCFG5_IMX_MASK 0xC0 #define BRDCFG5_IMX_DIU 0x80 +/* BRDCFG9[2] controls EPHY2 Clock */ +#define BRDCFG9_EPHY2_MASK 0x20 +#define BRDCFG9_EPHY2_VAL 0x00 + /* BRDCFG15[3] controls LCD Panel Powerdown*/ #define BRDCFG15_LCDPD_MASK 0x10 #define BRDCFG15_LCDPD_ENABLED 0x00 From 8340e7ac86ad3c59956e8f0bd627b741e5209439 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 23 Jun 2014 15:36:44 -0700 Subject: [PATCH 12/20] driver/ddr: Fix DDR4 driver for ARM Previously the driver was only tested on Power SoCs. Different barrier instructions are needed for ARM SoCs. Signed-off-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 4 ++++ arch/arm/include/asm/io.h | 1 + arch/powerpc/include/asm/io.h | 3 +++ drivers/ddr/fsl/fsl_ddr_gen4.c | 7 +++++-- 4 files changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index c1c718ecd4..b17410a58a 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -43,7 +43,11 @@ /* DDR */ #define CONFIG_SYS_FSL_DDR_LE #define CONFIG_VERY_BIG_RAM +#ifdef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDRC_GEN4 +#else #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ +#endif #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 214f3ea51f..6d18eb330a 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -136,6 +136,7 @@ extern inline void __raw_readsl(unsigned long addr, void *data, int longlen) * TODO: The kernel offers some more advanced versions of barriers, it might * have some advantages to use them instead of the simple one here. */ +#define mb() asm volatile("dsb sy" : : : "memory") #define dmb() __asm__ __volatile__ ("" : : : "memory") #define __iormb() dmb() #define __iowmb() dmb() diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index d8b7b974d4..a5257e9b62 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -123,6 +123,9 @@ static inline void isync(void) #define iobarrier_r() eieio() #define iobarrier_w() eieio() +#define mb() sync() +#define isb() isync() + /* * Non ordered and non-swapping "raw" accessors */ diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 7cd878aeec..bfc76b3485 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) @@ -183,12 +184,14 @@ step2: * we choose the max, that is 500 us for all of case. */ udelay(500); - asm volatile("sync;isync"); + mb(); + isb(); /* Let the controller go */ temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); - asm volatile("sync;isync"); + mb(); + isb(); total_gb_size_per_controller = 0; for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { From 9d0456822c4fec302608d4161ae9d9cfe81100b1 Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 24 Jun 2014 21:16:20 -0700 Subject: [PATCH 13/20] powerpc/mpc85xx: Check return value of find_tlb_idx find_tlb_idx() is called in board_early_init_r() on multiple boards. The return value is not checked before being used to disable a TLB. In normal case the return value wouldn't be -1. In case of a mis- configuration during porting to a new board, checking the return value may be helpful to reveal some user errors. Signed-off-by: York Sun --- board/exmeritus/hww1u1a/hww1u1a.c | 12 +++++++++--- board/freescale/b4860qds/b4860qds.c | 12 +++++++++--- board/freescale/bsc9132qds/bsc9132qds.c | 12 +++++++++--- board/freescale/c29xpcie/c29xpcie.c | 12 +++++++++--- board/freescale/corenet_ds/corenet_ds.c | 12 +++++++++--- board/freescale/mpc8536ds/mpc8536ds.c | 12 +++++++++--- board/freescale/mpc8572ds/mpc8572ds.c | 12 +++++++++--- board/freescale/p1010rdb/p1010rdb.c | 12 +++++++++--- board/freescale/p1022ds/p1022ds.c | 12 +++++++++--- board/freescale/p1023rdb/p1023rdb.c | 12 +++++++++--- board/freescale/p1_p2_rdb/p1_p2_rdb.c | 12 +++++++++--- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 12 +++++++++--- board/freescale/p1_twr/p1_twr.c | 12 +++++++++--- board/freescale/p2020ds/p2020ds.c | 12 +++++++++--- board/freescale/p2041rdb/p2041rdb.c | 12 +++++++++--- board/freescale/t1040qds/t1040qds.c | 12 +++++++++--- board/freescale/t104xrdb/t104xrdb.c | 12 +++++++++--- board/freescale/t208xqds/t208xqds.c | 12 +++++++++--- board/freescale/t208xrdb/t208xrdb.c | 13 +++++++++---- board/freescale/t4qds/t4240emu.c | 12 +++++++++--- board/freescale/t4qds/t4240qds.c | 12 +++++++++--- board/freescale/t4rdb/t4240rdb.c | 12 +++++++++--- 22 files changed, 198 insertions(+), 67 deletions(-) diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c index 97b84b3224..643ece1ae6 100644 --- a/board/exmeritus/hww1u1a/hww1u1a.c +++ b/board/exmeritus/hww1u1a/hww1u1a.c @@ -203,7 +203,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap bootflash region to caching-inhibited @@ -214,8 +214,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for FLASH */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for FLASH */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index 9d6b9a7b66..34d66d5fd2 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -913,7 +913,7 @@ out: int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); int ret; /* @@ -925,8 +925,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c index 9377280063..10580bcecc 100644 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -150,7 +150,7 @@ int board_early_init_r(void) { #ifndef CONFIG_SYS_NO_FLASH const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash region to caching-inhibited @@ -161,8 +161,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c index f964d6185a..534c6d11b0 100644 --- a/board/freescale/c29xpcie/c29xpcie.c +++ b/board/freescale/c29xpcie/c29xpcie.c @@ -49,7 +49,7 @@ int board_early_init_f(void) int board_early_init_r(void) { const unsigned long flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash region to caching-inhibited @@ -60,8 +60,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 1; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 9212372fee..65b386741e 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -101,7 +101,7 @@ int board_early_init_f(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -112,8 +112,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 467f4f2013..93eed59b1a 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -196,7 +196,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -207,8 +207,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 1; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 56863222c8..1bbf832148 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -144,7 +144,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -155,8 +155,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 62caf676c6..491b576258 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -93,7 +93,7 @@ int board_early_init_f(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash region to caching-inhibited @@ -104,8 +104,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index ba789a4daf..f5e18515a0 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -249,7 +249,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -260,8 +260,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c index d2d4f8390a..d4d277ba6d 100644 --- a/board/freescale/p1023rdb/p1023rdb.c +++ b/board/freescale/p1023rdb/p1023rdb.c @@ -57,7 +57,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -68,8 +68,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 3df557d6a3..aba4f534b8 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -128,7 +128,7 @@ int misc_init_r(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); unsigned int orig_bus = i2c_get_bus_num(); u8 i2c_data; @@ -163,8 +163,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 5f3d6fd28b..a6756c68f4 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -288,7 +288,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash region to caching-inhibited @@ -299,8 +299,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */ diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c index 0e0d0587d7..a0a416ba17 100644 --- a/board/freescale/p1_twr/p1_twr.c +++ b/board/freescale/p1_twr/p1_twr.c @@ -155,7 +155,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash region to caching-inhibited @@ -166,8 +166,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index a0cf927038..b72fcffdd0 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -159,7 +159,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -170,8 +170,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 8554512df6..a14b43b5a5 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -116,7 +116,7 @@ void board_config_lanes_mux(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -127,8 +127,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 0e83d172da..19af46e48f 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -119,7 +119,7 @@ int board_early_init_r(void) { #ifdef CONFIG_SYS_FLASH_BASE const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -130,8 +130,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index a5e5fffac4..ddb669fb06 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -48,7 +48,7 @@ int board_early_init_r(void) { #ifdef CONFIG_SYS_FLASH_BASE const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash region to caching-inhibited @@ -59,8 +59,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 135343949e..fc6d256111 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -326,7 +326,7 @@ int brd_mux_lane_to_slot(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -337,8 +337,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 265c1f97dd..be99fb806d 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -58,7 +58,7 @@ int checkboard(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited * so that flash can be erased properly. @@ -67,9 +67,14 @@ int board_early_init_r(void) /* Flush d-cache and invalidate i-cache of any FLASH data */ flush_dcache(); invalidate_icache(); - - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c index 7a610367da..479e124a39 100644 --- a/board/freescale/t4qds/t4240emu.c +++ b/board/freescale/t4qds/t4240emu.c @@ -32,7 +32,7 @@ int checkboard(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -43,8 +43,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index fe1bc7f08d..c5161c80b6 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -528,7 +528,7 @@ int config_backside_crossbar_mux(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -539,8 +539,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index 5448c86c48..afef7e93d0 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -39,7 +39,7 @@ int checkboard(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -50,8 +50,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, From de5191631088e71ba8ed28bb491dafa776058008 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Thu, 26 Jun 2014 14:41:33 +0800 Subject: [PATCH 14/20] powerpc/ifc: fix invalid CSn FTIM2.TCH setting On some platforms, CSn FTIM2.TCH is set to zero which is invalid, an invalid hold time makes DUT timing variances, whether it works or not on luck. Signed-off-by: Shaohui Xie Reviewed-by: York Sun --- include/configs/B4860QDS.h | 2 +- include/configs/BSC9132QDS.h | 2 +- include/configs/C29XPCIE.h | 2 +- include/configs/P1010RDB.h | 2 +- include/configs/T104xRDB.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240QDS.h | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 1af9ba686d..43c9df01bd 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -340,7 +340,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 7bb5d33d0c..49c16afa25 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -354,7 +354,7 @@ combinations. this should be removed later #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS2_FTIM3 0x0 #endif diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 9e12fac5b1..0dd15603ed 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -319,7 +319,7 @@ #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS2_FTIM3 0x0 diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index d612a8b9c4..50529bff04 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -537,7 +537,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 8d6c51bb37..40bfc60cf5 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -286,7 +286,7 @@ #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS2_FTIM3 0x0 diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 3a1c49c811..5d10ad25e5 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -283,7 +283,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS2_FTIM3 0x0 diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index a770dd0d3a..efdb68b7ae 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -237,7 +237,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 From 3d75ec95f57224995210db5c5dea8d458cf862fb Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 26 Jun 2014 11:14:44 -0700 Subject: [PATCH 15/20] driver/ddr: Fix DDR register timing_cfg_8 The field wrtord_bg should add 2 clocks if on the fly chop is enabled, according to DDR controller manual for DDR4. Signed-off-by: York Sun --- drivers/ddr/fsl/ctrl_regs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index dcf6287f66..04e4178b15 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -1857,6 +1857,9 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr, acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps); wrtord_bg = max(4, picos_to_mclk(7500)); + if (popts->otf_burst_chop_en) + wrtord_bg += 2; + pre_all_rec = 0; ddr->timing_cfg_8 = (0 From e55782ecccadc196a4f9d8e5e8b456e200ea9727 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Fri, 27 Jun 2014 14:39:31 +0800 Subject: [PATCH 16/20] powerpc/t4240qds: fix offset of serdes when checking reference clock T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie Reviewed-by: York Sun --- arch/powerpc/include/asm/immap_85xx.h | 6 ++++++ board/freescale/t4qds/t4240qds.c | 10 ++++++---- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 8258ab3805..dfb370e051 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2905,6 +2905,8 @@ struct ccsr_sfp_regs { #endif #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 +#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000 +#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 #define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 @@ -3090,6 +3092,10 @@ struct ccsr_sfp_regs { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET) +#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET) +#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET) #define CONFIG_SYS_MPC85xx_USB1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET) #define CONFIG_SYS_MPC85xx_USB2_ADDR \ diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index c5161c80b6..6205fea35e 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -644,9 +644,10 @@ unsigned long get_board_ddr_clk(void) int misc_init_r(void) { u8 sw; - serdes_corenet_t *srds_regs = - (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + serdes_corenet_t *srds_regs; u32 actual[MAX_SERDES]; + u32 pllcr0, expected; unsigned int i; sw = QIXIS_READ(brdcfg[2]); @@ -669,8 +670,9 @@ int misc_init_r(void) } for (i = 0; i < MAX_SERDES; i++) { - u32 pllcr0 = srds_regs->bank[i].pllcr0; - u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + srds_regs = srds_base + i * 0x1000; + pllcr0 = srds_regs->bank[0].pllcr0; + expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) { printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n", i + 1, serdes_clock_to_string(expected), From a1399a918720337ad14053cf6185786aa33b58b2 Mon Sep 17 00:00:00 2001 From: Shaveta Leekha Date: Wed, 2 Jul 2014 11:44:54 +0530 Subject: [PATCH 17/20] powerpc/chassis2: Configure and enable L2 cache for PPC clusters only Signed-off-by: Poonam Aggrwal Signed-off-by: Shaveta Leekha Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 78316a6815..c2a89c2fa6 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -520,7 +520,8 @@ int enable_cluster_l2(void) u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; u32 type = in_be32(&gur->tp_ityp[idx]); - if (type & TP_ITYP_AV) + if ((type & TP_ITYP_AV) && + TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) cluster_valid = 1; } From 7cb7272365983e3a1eedf18a9f688c825e1cf95e Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Fri, 4 Jul 2014 17:39:26 +0800 Subject: [PATCH 18/20] mpc85xx/t104x: Enable L2 and CPC cache when resume When resume from deep sleep, uboot needs to enable L2 and CPC cache, or they would be keeping unusable in kernel because kernel didn't enble or initialized them. This patch didn't change the existing L2 cache enabling code, just put them in a function. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 163 +++++++++++++++------------- arch/powerpc/include/asm/cache.h | 6 + arch/powerpc/lib/board.c | 5 + 3 files changed, 98 insertions(+), 76 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index c2a89c2fa6..b237505d3e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -200,7 +200,7 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) #ifdef CONFIG_SYS_FSL_CPC #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) -static void disable_cpc_sram(void) +void disable_cpc_sram(void) { int i; @@ -251,7 +251,7 @@ static void enable_tdm_law(void) } #endif -static void enable_cpc(void) +void enable_cpc(void) { int i; u32 size = 0; @@ -306,6 +306,7 @@ static void invalidate_cpc(void) #else #define enable_cpc() #define invalidate_cpc() +#define disable_cpc_sram() #endif /* CONFIG_SYS_FSL_CPC */ /* @@ -546,88 +547,15 @@ int enable_cluster_l2(void) /* * Initialize L2 as cache. - * - * The newer 8548, etc, parts have twice as much cache, but - * use the same bit-encoding as the older 8555, etc, parts. - * */ -int cpu_init_r(void) +int l2cache_init(void) { __maybe_unused u32 svr = get_svr(); -#ifdef CONFIG_SYS_LBC_LCRR - fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; -#endif #ifdef CONFIG_L2_CACHE ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; #endif -#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) - extern int spin_table_compat; - const char *spin; -#endif -#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 - ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; -#endif -#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ - defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) - /* - * CPU22 and NMG_CPU_A011 share the same workaround. - * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 - * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 - * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both - * fixed in 2.0. NMG_CPU_A011 is activated by default and can - * be disabled by hwconfig with syntax: - * - * fsl_cpu_a011:disable - */ - extern int enable_cpu_a011_workaround; -#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 - enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); -#else - char buffer[HWCONFIG_BUFFER_SIZE]; - char *buf = NULL; - int n, res; - - n = getenv_f("hwconfig", buffer, sizeof(buffer)); - if (n > 0) - buf = buffer; - - res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); - if (res > 0) - enable_cpu_a011_workaround = 0; - else { - if (n >= HWCONFIG_BUFFER_SIZE) { - printf("fsl_cpu_a011 was not found. hwconfig variable " - "may be too long\n"); - } - enable_cpu_a011_workaround = - (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || - (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); - } -#endif - if (enable_cpu_a011_workaround) { - flush_dcache(); - mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); - sync(); - } -#endif -#ifdef CONFIG_SYS_FSL_ERRATUM_A005812 - /* - * A-005812 workaround sets bit 32 of SPR 976 for SoCs running - * in write shadow mode. Checking DCWS before setting SPR 976. - */ - if (mfspr(L1CSR2) & L1CSR2_DCWS) - mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); -#endif - -#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) - spin = getenv("spin_table_compat"); - if (spin && (*spin == 'n')) - spin_table_compat = 0; - else - spin_table_compat = 1; -#endif puts ("L2: "); @@ -752,6 +680,89 @@ skip_l2: puts("disabled\n"); #endif + return 0; +} + +/* + * + * The newer 8548, etc, parts have twice as much cache, but + * use the same bit-encoding as the older 8555, etc, parts. + * + */ +int cpu_init_r(void) +{ + __maybe_unused u32 svr = get_svr(); +#ifdef CONFIG_SYS_LBC_LCRR + fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; +#endif +#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) + extern int spin_table_compat; + const char *spin; +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 + ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; +#endif +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ + defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) + /* + * CPU22 and NMG_CPU_A011 share the same workaround. + * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both + * fixed in 2.0. NMG_CPU_A011 is activated by default and can + * be disabled by hwconfig with syntax: + * + * fsl_cpu_a011:disable + */ + extern int enable_cpu_a011_workaround; +#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 + enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); +#else + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + int n, res; + + n = getenv_f("hwconfig", buffer, sizeof(buffer)); + if (n > 0) + buf = buffer; + + res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); + if (res > 0) { + enable_cpu_a011_workaround = 0; + } else { + if (n >= HWCONFIG_BUFFER_SIZE) { + printf("fsl_cpu_a011 was not found. hwconfig variable " + "may be too long\n"); + } + enable_cpu_a011_workaround = + (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || + (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); + } +#endif + if (enable_cpu_a011_workaround) { + flush_dcache(); + mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); + sync(); + } +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005812 + /* + * A-005812 workaround sets bit 32 of SPR 976 for SoCs running + * in write shadow mode. Checking DCWS before setting SPR 976. + */ + if (mfspr(L1CSR2) & L1CSR2_DCWS) + mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); +#endif + +#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) + spin = getenv("spin_table_compat"); + if (spin && (*spin == 'n')) + spin_table_compat = 0; + else + spin_table_compat = 1; +#endif + + l2cache_init(); #if defined(CONFIG_RAMBOOT_PBL) disable_cpc_sram(); #endif diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index cdc1f10872..d3a83910b6 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -57,6 +57,12 @@ extern void unlock_ram_in_cache(void); #endif /* CONFIG_SYS_INIT_RAM_LOCK */ #endif /* __ASSEMBLY__ */ +#if defined(__KERNEL__) && !defined(__ASSEMBLY__) +int l2cache_init(void); +void enable_cpc(void); +void disable_cpc_sram(void); +#endif + /* prep registers for L2 */ #define CACHECRBA 0x80000823 /* Cache configuration register address */ #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 300ab12a3b..50eb820336 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -370,6 +370,11 @@ void board_init_f(ulong bootflag) #ifdef CONFIG_DEEP_SLEEP /* Jump to kernel in deep sleep case */ if (in_be32(&gur->scrtsr[0]) & (1 << 3)) { + l2cache_init(); +#if defined(CONFIG_RAMBOOT_PBL) + disable_cpc_sram(); +#endif + enable_cpc(); start_addr = in_be32(&scfg->sparecr[1]); kernel_resume = (func_t)start_addr; kernel_resume(); From b0d97cd2ed8533f98a6c8a12103eddf07ff7bbff Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Mon, 7 Jul 2014 12:17:47 +0800 Subject: [PATCH 19/20] powerpc/t1040: update i2c for t1040qds and t104xrdb - Fix base address of I2C2 as 0x118100 instead of 0x119000. - Add definitions for I2C3 & I2C4. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- include/configs/T1040QDS.h | 10 ++++++++-- include/configs/T104xRDB.h | 10 ++++++++-- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index f2a75aed43..ebee89a9a1 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -445,11 +445,17 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SPEED 50000 +#define CONFIG_SYS_FSL_I2C3_SPEED 50000 +#define CONFIG_SYS_FSL_I2C4_SPEED 50000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 #define I2C_MUX_PCA_ADDR 0x77 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 40bfc60cf5..c96f03ce2b 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -443,11 +443,17 @@ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C3_SPEED 400000 +#define CONFIG_SYS_FSL_I2C4_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 From fb5368789a45ca5ee4396cbbf563a8f16ab24f9c Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 23 Jul 2014 15:54:16 +0800 Subject: [PATCH 20/20] board/freescale: use generic board architecture for t2080qds and t2080rdb Tested with NOR boot and NAND boot on T2080QDS and T2080RDB. Signed-off-by: Shengzhou Liu --- include/configs/T208xQDS.h | 2 ++ include/configs/T208xRDB.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 9b81ff70eb..784310a112 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -11,6 +11,8 @@ #ifndef __T208xQDS_H #define __T208xQDS_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #define CONFIG_MMC #define CONFIG_SPI_FLASH diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 5d10ad25e5..deeabae329 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -11,6 +11,8 @@ #ifndef __T2080RDB_H #define __T2080RDB_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_T2080RDB #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #define CONFIG_MMC