leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Browse Source
This commit is contained in:
Tom Rini 2014-07-28 14:54:29 -04:00
commit d5f8a6ddd4
69 changed files with 481 additions and 1133 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/include/asm/arch-fsl-lsch3/config.h
View File

@ -43,7 +43,11 @@
/* DDR */
#define CONFIG_SYS_FSL_DDR_LE
#define CONFIG_VERY_BIG_RAM
#ifdef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDRC_GEN4
#else
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
#endif
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE

1
arch/arm/include/asm/io.h
View File

@ -136,6 +136,7 @@ extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
* TODO: The kernel offers some more advanced versions of barriers, it might
* have some advantages to use them instead of the simple one here.
*/
#define mb() asm volatile("dsb sy" : : : "memory")
#define dmb() __asm__ __volatile__ ("" : : : "memory")
#define __iormb() dmb()
#define __iowmb() dmb()

2
arch/powerpc/cpu/mpc83xx/cpu.c
View File

@ -20,7 +20,7 @@
#include <netdev.h>
#include <fsl_esdhc.h>
#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
#include <asm/immap_qe.h>
#include <linux/immap_qe.h>
#include <asm/io.h>
#endif

2
arch/powerpc/cpu/mpc83xx/fdt.c
View File

@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
(defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
#include <asm/immap_qe.h>
#include <linux/immap_qe.h>
void fdt_fixup_muram (void *blob)
{

166
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -200,7 +200,7 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
#ifdef CONFIG_SYS_FSL_CPC
#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
static void disable_cpc_sram(void)
void disable_cpc_sram(void)
{
int i;
@ -251,7 +251,7 @@ static void enable_tdm_law(void)
}
#endif
static void enable_cpc(void)
void enable_cpc(void)
{
int i;
u32 size = 0;
@ -306,6 +306,7 @@ static void invalidate_cpc(void)
#else
#define enable_cpc()
#define invalidate_cpc()
#define disable_cpc_sram()
#endif /* CONFIG_SYS_FSL_CPC */
/*
@ -520,7 +521,8 @@ int enable_cluster_l2(void)
u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
u32 type = in_be32(&gur->tp_ityp[idx]);
if (type & TP_ITYP_AV)
if ((type & TP_ITYP_AV) &&
TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
cluster_valid = 1;
}
@ -545,88 +547,15 @@ int enable_cluster_l2(void)
/*
* Initialize L2 as cache.
*
* The newer 8548, etc, parts have twice as much cache, but
* use the same bit-encoding as the older 8555, etc, parts.
*
*/
int cpu_init_r(void)
int l2cache_init(void)
{
__maybe_unused u32 svr = get_svr();
#ifdef CONFIG_SYS_LBC_LCRR
fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
#endif
#ifdef CONFIG_L2_CACHE
ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
extern int spin_table_compat;
const char *spin;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
/*
* CPU22 and NMG_CPU_A011 share the same workaround.
* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
* fixed in 2.0. NMG_CPU_A011 is activated by default and can
* be disabled by hwconfig with syntax:
*
* fsl_cpu_a011:disable
*/
extern int enable_cpu_a011_workaround;
#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
#else
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
int n, res;
n = getenv_f("hwconfig", buffer, sizeof(buffer));
if (n > 0)
buf = buffer;
res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
if (res > 0)
enable_cpu_a011_workaround = 0;
else {
if (n >= HWCONFIG_BUFFER_SIZE) {
printf("fsl_cpu_a011 was not found. hwconfig variable "
"may be too long\n");
}
enable_cpu_a011_workaround =
(SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
(SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
}
#endif
if (enable_cpu_a011_workaround) {
flush_dcache();
mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
sync();
}
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
/*
* A-005812 workaround sets bit 32 of SPR 976 for SoCs running
* in write shadow mode. Checking DCWS before setting SPR 976.
*/
if (mfspr(L1CSR2) & L1CSR2_DCWS)
mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
spin = getenv("spin_table_compat");
if (spin && (*spin == 'n'))
spin_table_compat = 0;
else
spin_table_compat = 1;
#endif
puts ("L2: ");
@ -751,6 +680,89 @@ skip_l2:
puts("disabled\n");
#endif
return 0;
}
/*
*
* The newer 8548, etc, parts have twice as much cache, but
* use the same bit-encoding as the older 8555, etc, parts.
*
*/
int cpu_init_r(void)
{
__maybe_unused u32 svr = get_svr();
#ifdef CONFIG_SYS_LBC_LCRR
fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
extern int spin_table_compat;
const char *spin;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
/*
* CPU22 and NMG_CPU_A011 share the same workaround.
* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
* fixed in 2.0. NMG_CPU_A011 is activated by default and can
* be disabled by hwconfig with syntax:
*
* fsl_cpu_a011:disable
*/
extern int enable_cpu_a011_workaround;
#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
#else
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
int n, res;
n = getenv_f("hwconfig", buffer, sizeof(buffer));
if (n > 0)
buf = buffer;
res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
if (res > 0) {
enable_cpu_a011_workaround = 0;
} else {
if (n >= HWCONFIG_BUFFER_SIZE) {
printf("fsl_cpu_a011 was not found. hwconfig variable "
"may be too long\n");
}
enable_cpu_a011_workaround =
(SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
(SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
}
#endif
if (enable_cpu_a011_workaround) {
flush_dcache();
mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
sync();
}
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
/*
* A-005812 workaround sets bit 32 of SPR 976 for SoCs running
* in write shadow mode. Checking DCWS before setting SPR 976.
*/
if (mfspr(L1CSR2) & L1CSR2_DCWS)
mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
spin = getenv("spin_table_compat");
if (spin && (*spin == 'n'))
spin_table_compat = 0;
else
spin_table_compat = 1;
#endif
l2cache_init();
#if defined(CONFIG_RAMBOOT_PBL)
disable_cpc_sram();
#endif

47
arch/powerpc/cpu/mpc85xx/fdt.c
View File

@ -612,6 +612,51 @@ static void fdt_fixup_usb(void *fdt)
#define fdt_fixup_usb(x)
#endif
#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T4240) || \
defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
void fdt_fixup_dma3(void *blob)
{
/* the 3rd DMA is not functional if SRIO2 is chosen */
int nodeoff;
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
#if defined(CONFIG_PPC_T2080)
u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
switch (srds_prtcl_s2) {
case 0x29:
case 0x2d:
case 0x2e:
#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
defined(CONFIG_PPC_T4080)
u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
switch (srds_prtcl_s4) {
case 6:
case 8:
case 14:
case 16:
#endif
nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
CONFIG_SYS_ELO3_DMA3);
if (nodeoff > 0)
fdt_status_disabled(blob, nodeoff);
else
printf("WARNING: unable to disable dma3\n");
break;
default:
break;
}
}
#else
#define fdt_fixup_dma3(x)
#endif
#if defined(CONFIG_PPC_T1040)
static void fdt_fixup_l2_switch(void *blob)
{
@ -778,6 +823,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_usb(blob);
fdt_fixup_l2_switch(blob);
fdt_fixup_dma3(blob);
}
/*

1
arch/powerpc/cpu/mpc8xxx/cpu.c
View File

@ -65,7 +65,6 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(T4080, T4080, 4),
CPU_TYPE_ENTRY(B4860, B4860, 0),
CPU_TYPE_ENTRY(G4860, G4860, 0),
CPU_TYPE_ENTRY(G4060, G4060, 0),
CPU_TYPE_ENTRY(B4440, B4440, 0),
CPU_TYPE_ENTRY(B4460, B4460, 0),
CPU_TYPE_ENTRY(G4440, G4440, 0),

6
arch/powerpc/include/asm/cache.h
View File

@ -57,6 +57,12 @@ extern void unlock_ram_in_cache(void);
#endif /* CONFIG_SYS_INIT_RAM_LOCK */
#endif /* __ASSEMBLY__ */
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
int l2cache_init(void);
void enable_cpc(void);
void disable_cpc_sram(void);
#endif
/* prep registers for L2 */
#define CACHECRBA 0x80000823 /* Cache configuration register address */
#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */

6
arch/powerpc/include/asm/immap_85xx.h
View File

@ -2905,6 +2905,8 @@ struct ccsr_sfp_regs {
#endif
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
@ -3090,6 +3092,10 @@ struct ccsr_sfp_regs {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
#define CONFIG_SYS_MPC85xx_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
#define CONFIG_SYS_MPC85xx_USB2_ADDR \

3
arch/powerpc/include/asm/io.h
View File

@ -123,6 +123,9 @@ static inline void isync(void)
#define iobarrier_r() eieio()
#define iobarrier_w() eieio()
#define mb() sync()
#define isb() isync()
/*
* Non ordered and non-swapping "raw" accessors
*/

1
arch/powerpc/include/asm/processor.h
View File

@ -1118,7 +1118,6 @@
#define SVR_B4860 0X868000
#define SVR_G4860 0x868001
#define SVR_B4460 0x868003
#define SVR_G4060 0x868003
#define SVR_B4440 0x868100
#define SVR_G4440 0x868101
#define SVR_B4420 0x868102

5
arch/powerpc/lib/board.c
View File

@ -370,6 +370,11 @@ void board_init_f(ulong bootflag)
#ifdef CONFIG_DEEP_SLEEP
/* Jump to kernel in deep sleep case */
if (in_be32(&gur->scrtsr[0]) & (1 << 3)) {
l2cache_init();
#if defined(CONFIG_RAMBOOT_PBL)
disable_cpc_sram();
#endif
enable_cpc();
start_addr = in_be32(&scfg->sparecr[1]);
kernel_resume = (func_t)start_addr;
kernel_resume();

12
board/exmeritus/hww1u1a/hww1u1a.c
View File

@ -203,7 +203,7 @@ void pci_init_board(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap bootflash region to caching-inhibited
@ -214,8 +214,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for FLASH */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for FLASH */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

12
board/freescale/b4860qds/b4860qds.c
View File

@ -913,7 +913,7 @@ out:
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
int ret;
/*
@ -925,8 +925,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

12
board/freescale/bsc9132qds/bsc9132qds.c
View File

@ -150,7 +150,7 @@ int board_early_init_r(void)
{
#ifndef CONFIG_SYS_NO_FLASH
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
@ -161,8 +161,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

12
board/freescale/c29xpcie/c29xpcie.c
View File

@ -49,7 +49,7 @@ int board_early_init_f(void)
int board_early_init_r(void)
{
const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
@ -60,8 +60,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 1; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

12
board/freescale/corenet_ds/corenet_ds.c
View File

@ -101,7 +101,7 @@ int board_early_init_f(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
@ -112,8 +112,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */

12
board/freescale/mpc8536ds/mpc8536ds.c
View File

@ -196,7 +196,7 @@ void pci_init_board(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
@ -207,8 +207,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 1; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */

12
board/freescale/mpc8572ds/mpc8572ds.c
View File

@ -144,7 +144,7 @@ void pci_init_board(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
@ -155,8 +155,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */

12
board/freescale/p1010rdb/p1010rdb.c
View File

@ -93,7 +93,7 @@ int board_early_init_f(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
@ -104,8 +104,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

12
board/freescale/p1022ds/p1022ds.c
View File

@ -249,7 +249,7 @@ void pci_init_board(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
@ -260,8 +260,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

12
board/freescale/p1023rdb/p1023rdb.c
View File

@ -57,7 +57,7 @@ void pci_init_board(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
@ -68,8 +68,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

9
board/freescale/p1023rds/Makefile
View File

@ -1,9 +0,0 @@
#
# Copyright 2010-2011 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += p1023rds.o
obj-y += law.o
obj-y += tlb.o

101
board/freescale/p1023rds/README
View File

@ -1,101 +0,0 @@
Overview
--------
The P1023 process includes a performance optimized implementation of the
QorIQ data Path Acceleration Architecture (DPAA). This architecture
provides the infrastructure to support simplified sharing of networking
interfaces and accelerators by multiple CPU cores. P1023 is an e500 based
dual core SOC.
P1023RDS board is a Low End Dual core platform supporting the P1023
processor of QorIQ series.
Building U-boot
---------------
To build the u-boot for P1023RDS:
Configure to NOR boot:
make P1023RDS_config
Configure to NAND boot:
make P1023RDS_NAND_config
Build:
make
Board Switches
--------------
Most switches on the board should not be changed. The most frequent
user-settable switches on the board are used to configure
the flash banks.
J4: all open
Default NOR flash boot switch setting:
Sw3[1:8]: off on on off on on off off
Sw4[1:8]: off off off on off off off off
Sw6[1:8]: off on off on off on on off
Sw7[1:8]: off on off off on off off off
Sw8[1:8]: on off off off off off off off
For NAND flash boot,set
Sw4[1:4]: off on on on
The default native ethernet setting is for RGMII mode.
To use SGMII mode, set
SW8[1:2]: OFF OFF
SW7[6:7]: ON ON
Memory Map
----------
0x0000_0000 0x7fff_ffff DDR 2G Cacheable
0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
0xe000_0000 0xe003_ffff BCSR 256K BCSR
0xee00_0000 0xefff_ffff NOR flash 32M NOR flash
0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M
0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
0xffa0_0000 0xffaf_ffff NAND FLASH 1M non-cacheable
0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
Flashing u-boot Images
---------------
To program the image in the boot flash bank:
NOR flash boot:
=> tftp 1000000 u-boot.bin
=> protect off all
=> erase eff40000 efffffff
=> cp.b 1000000 eff40000 c0000
NAND flash boot:
=> tftp 1000000 u-boot-nand.bin
=> nand erase 0 80000
=> nand write 1000000 0 80000
Firmware ucode location
---------------------------------
Microcode(ucode) to FMAN's IRAM is needed to make FMAN Ethernet work.
u-boot loads ucode FLASH. The location for ucode:
NOR Flash: 0xfe000000
NAND Flash: 0x1f00000
Using the Device Tree Source File
---------------------------------
To create the DTB (Device Tree Binary) image file,
use a command similar to this:
dtc -b 0 -f -I dts -O dtb p1023rds.dts > p1023rds.dtb
Likely, that .dts file will come from here;
linux-2.6/arch/powerpc/boot/dts/p1023rds.dts
or
make p1023rds.dtb ARCH=powerpc
in linux-2.6 directory.
Booting Linux
-------------
Place a linux uImage in the TFTP disk area.
tftp 1000000 uImage
tftp 2000000 rootfs.ext2.gz.uboot
tftp c00000 p1023rds.dtb
bootm 1000000 2000000 c00000

49
board/freescale/p1023rds/bcsr.h
View File

@ -1,49 +0,0 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
*
* Authors: Chunhe Lan <b25806@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __BCSR_H_
#define __BCSR_H_
#include <common.h>
/*
* BCSR Bit definitions
* BCSR 15 *
0 device insertion oriention
1 stack processor present
2 power supply shut down/normal operation
3 I2C bus0 drive enable
4 reserved
5:7 I2C bus0 select
5 - I2C_BUS_0_SS0
6 - I2C_BUS_0_SS1
7 - I2C_BUS_0_SS2
*/
/* BCSR register base address is 0xFX000020 */
#define BCSR_BASE_REG_OFFSET 0x20
#define BCSR_ACCESS_REG_ADDR (CONFIG_SYS_BCSR_BASE + BCSR_BASE_REG_OFFSET)
#define BCSR15_DEV_INS_ORI 0x80
#define BCSR15_STACK_PRO_PRE 0x40
#define BCSR15_POWER_SUPPLY 0x20
#define BCSR15_I2C_BUS0_EN 0x10
#define BCSR15_I2C_BUS0_SEG0 0x00
#define BCSR15_I2C_BUS0_SEG1 0x04
#define BCSR15_I2C_BUS0_SEG2 0x02
#define BCSR15_I2C_BUS0_SEG3 0x06
#define BCSR15_I2C_BUS0_SEG4 0x01
#define BCSR15_I2C_BUS0_SEG5 0x05
#define BCSR15_I2C_BUS0_SEG6 0x03
#define BCSR15_I2C_BUS0_SEG7 0x07
#define BCSR15_I2C_BUS0_SEG_CLR 0x07
#define BCSR19_SGMII_SEL_L 0x01
/*BCSR Utils functions*/
void fixup_i2c_bus0_sel_seg0(void);
#endif /* __BCSR_H_ */

19
board/freescale/p1023rds/law.c
View File

@ -1,19 +0,0 @@
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M,
LAW_TRGT_IF_DPAA_SWP_SRAM),
/* The LAW 0xe0000000 ~ 0xefffffff for BCSR and NOR flash */
SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

191
board/freescale/p1023rds/p1023rds.c
View File

@ -1,191 +0,0 @@
/*
* Copyright 2010-2012 Freescale Semiconductor, Inc.
*
* Authors: Roy Zang <tie-fei.zang@freescale.com>
* Chunhe Lan <b25806@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/io.h>
#include <asm/cache.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_portals.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <netdev.h>
#include <malloc.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include "bcsr.h"
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
fsl_lbc_t *lbc = LBC_BASE_ADDR;
/* Set ABSWP to implement conversion of addresses in the LBC */
setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
return 0;
}
int checkboard(void)
{
u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR;
printf("Board: P1023 RDS\n");
clrbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG_CLR);
setbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG0);
return 0;
}
/* Fixed sdram init -- doesn't use serial presence detect. */
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
#endif
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024ul;
}
#ifdef CONFIG_PCI
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
#endif
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_BCSR_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + BCSR region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + bcsr */
disable_tlb(flash_esel);
set_tlb(1, flashbase, CONFIG_SYS_BCSR_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
setup_portals();
return 0;
}
unsigned long get_board_sys_clk(ulong dummy)
{
return gd->bus_clk;
}
unsigned long get_board_ddr_clk(ulong dummy)
{
return gd->mem_clk;
}
int board_eth_init(bd_t *bis)
{
u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR;
ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
struct fsl_pq_mdio_info dtsec_mdio_info;
/*
* Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
* is not correct.
*/
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
dtsec_mdio_info.regs =
(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fsl_pq_mdio_init(bis, &dtsec_mdio_info);
fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_mdio(FM1_DTSEC1,
miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
fm_info_set_mdio(FM1_DTSEC2,
miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
/* Make SERDES connected to SGMII by cleaing bcsr19[7] */
if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII)
clrbits_8(&bcsr[19], BCSR19_SGMII_SEL_L);
#ifdef CONFIG_FMAN_ENET
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = getenv_bootm_low();
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_HAS_FSL_DR_USB
fdt_fixup_dr_usb(blob, bd);
#endif
fdt_fixup_fman_ethernet(blob);
}
#endif

100
board/freescale/p1023rds/tlb.c
View File

@ -1,100 +0,0 @@
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_4M, 1),
/* *W*G* - BCSR and NOR flash on local bus*/
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_1M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_1M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 9, BOOKE_PAGESZ_1M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_1M, 1),
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 11, BOOKE_PAGESZ_1M, 1),
#ifdef CONFIG_SYS_RAMBOOT
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 12, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 13, BOOKE_PAGESZ_1G, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

12
board/freescale/p1_p2_rdb/p1_p2_rdb.c
View File

@ -128,7 +128,7 @@ int misc_init_r(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
unsigned int orig_bus = i2c_get_bus_num();
u8 i2c_data;
@ -163,8 +163,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

12
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
View File

@ -288,7 +288,7 @@ void pci_init_board(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
@ -299,8 +299,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */

12
board/freescale/p1_twr/p1_twr.c
View File

@ -155,7 +155,7 @@ void pci_init_board(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
@ -166,8 +166,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */

12
board/freescale/p2020ds/p2020ds.c
View File

@ -159,7 +159,7 @@ void pci_init_board(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
@ -170,8 +170,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

12
board/freescale/p2041rdb/p2041rdb.c
View File

@ -116,7 +116,7 @@ void board_config_lanes_mux(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
@ -127,8 +127,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

4
board/freescale/t1040qds/eth.c
View File

@ -355,7 +355,9 @@ static void set_brdcfg9_for_gtx_clk(void)
{
u8 brdcfg9;
brdcfg9 = QIXIS_READ(brdcfg[9]);
brdcfg9 |= (1 << 5);
/* Initializing EPHY2 clock to RGMII mode */
brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
brdcfg9 |= (BRDCFG9_EPHY2_VAL);
QIXIS_WRITE(brdcfg[9], brdcfg9);
}

12
board/freescale/t1040qds/t1040qds.c
View File

@ -119,7 +119,7 @@ int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
@ -130,8 +130,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

4
board/freescale/t1040qds/t1040qds_qixis.h
View File

@ -17,6 +17,10 @@
#define BRDCFG5_IMX_MASK 0xC0
#define BRDCFG5_IMX_DIU 0x80
/* BRDCFG9[2] controls EPHY2 Clock */
#define BRDCFG9_EPHY2_MASK 0x20
#define BRDCFG9_EPHY2_VAL 0x00
/* BRDCFG15[3] controls LCD Panel Powerdown*/
#define BRDCFG15_LCDPD_MASK 0x10
#define BRDCFG15_LCDPD_ENABLED 0x00

12
board/freescale/t104xrdb/t104xrdb.c
View File

@ -48,7 +48,7 @@ int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
@ -59,8 +59,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

12
board/freescale/t208xqds/t208xqds.c
View File

@ -326,7 +326,7 @@ int brd_mux_lane_to_slot(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
@ -337,8 +337,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

13
board/freescale/t208xrdb/t208xrdb.c
View File

@ -58,7 +58,7 @@ int checkboard(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
@ -67,9 +67,14 @@ int board_early_init_r(void)
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

12
board/freescale/t4qds/t4240emu.c
View File

@ -32,7 +32,7 @@ int checkboard(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
@ -43,8 +43,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

22
board/freescale/t4qds/t4240qds.c
View File

@ -528,7 +528,7 @@ int config_backside_crossbar_mux(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
@ -539,8 +539,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@ -638,9 +644,10 @@ unsigned long get_board_ddr_clk(void)
int misc_init_r(void)
{
u8 sw;
serdes_corenet_t *srds_regs =
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
serdes_corenet_t *srds_regs;
u32 actual[MAX_SERDES];
u32 pllcr0, expected;
unsigned int i;
sw = QIXIS_READ(brdcfg[2]);
@ -663,8 +670,9 @@ int misc_init_r(void)
}
for (i = 0; i < MAX_SERDES; i++) {
u32 pllcr0 = srds_regs->bank[i].pllcr0;
u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
srds_regs = srds_base + i * 0x1000;
pllcr0 = srds_regs->bank[0].pllcr0;
expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
if (expected != actual[i]) {
printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
i + 1, serdes_clock_to_string(expected),

12
board/freescale/t4rdb/t4240rdb.c
View File

@ -39,7 +39,7 @@ int checkboard(void)
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
@ -50,8 +50,14 @@ int board_early_init_r(void)
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

1
boards.cfg
View File

@ -830,7 +830,6 @@ Active powerpc mpc85xx - freescale p1022ds
Active powerpc mpc85xx - freescale p1022ds P1022DS_SDCARD P1022DS:SDCARD Timur Tabi <timur@freescale.com>
Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi <timur@freescale.com>
Active powerpc mpc85xx - freescale p1023rdb P1023RDB - -
Active powerpc mpc85xx - freescale p1023rds P1023RDS - Roy Zang <tie-fei.zang@freescale.com>
Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB -
Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT -
Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SDCARD P1_P2_RDB:P1011RDB,36BIT,SDCARD -

2
drivers/bootcount/bootcount.c
View File

@ -36,7 +36,7 @@
#endif /* defined(CONFIG_MPC8260) */
#if defined(CONFIG_QE)
#include <asm/immap_qe.h>
#include <linux/immap_qe.h>
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \
QE_MURAM_SIZE - 2 * sizeof(u32))

3
drivers/ddr/fsl/ctrl_regs.c
View File

@ -1857,6 +1857,9 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
wrtord_bg = max(4, picos_to_mclk(7500));
if (popts->otf_burst_chop_en)
wrtord_bg += 2;
pre_all_rec = 0;
ddr->timing_cfg_8 = (0

7
drivers/ddr/fsl/fsl_ddr_gen4.c
View File

@ -8,6 +8,7 @@
#include <asm/io.h>
#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
#include <fsl_immap.h>
#include <fsl_ddr.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
@ -183,12 +184,14 @@ step2:
* we choose the max, that is 500 us for all of case.
*/
udelay(500);
asm volatile("sync;isync");
mb();
isb();
/* Let the controller go */
temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
asm volatile("sync;isync");
mb();
isb();
total_gb_size_per_controller = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {

45
drivers/mtd/nand/fsl_ifc_nand.c
View File

@ -19,8 +19,11 @@
#include <asm/errno.h>
#include <fsl_ifc.h>
#define FSL_IFC_V1_1_0 0x01010000
#define MAX_BANKS 4
#ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#endif
#define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT
#define ERR_BYTE 0xFF /* Value returned for read bytes
when read failed */
#define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
@ -802,12 +805,30 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
{
}
static void fsl_ifc_sram_init(void)
static int fsl_ifc_sram_init(uint32_t ver)
{
struct fsl_ifc *ifc = ifc_ctrl->regs;
uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
uint32_t ncfgr = 0;
long long end_tick;
if (ver > FSL_IFC_V1_1_0) {
ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
/* wait for SRAM_INIT bit to be clear or timeout */
end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
while (end_tick > get_ticks()) {
ifc_ctrl->status =
ifc_in32(&ifc->ifc_nand.nand_evter_stat);
if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
return 0;
}
printf("fsl-ifc: Failed to Initialise SRAM\n");
return 1;
}
cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
/* Save CSOR and CSOR_ext */
@ -850,11 +871,18 @@ static void fsl_ifc_sram_init(void)
break;
}
if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
printf("fsl-ifc: Failed to Initialise SRAM\n");
return 1;
}
ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
/* Restore CSOR and CSOR_ext */
ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
return 0;
}
static int fsl_ifc_chip_init(int devnum, u8 *addr)
@ -864,7 +892,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
struct fsl_ifc_mtd *priv;
struct nand_ecclayout *layout;
uint32_t cspr = 0, csor = 0, ver = 0;
int ret;
int ret = 0;
if (!ifc_ctrl) {
fsl_ifc_ctrl_init();
@ -1006,8 +1034,13 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
}
ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
if (ver == FSL_IFC_V1_1_0)
fsl_ifc_sram_init();
if (ver >= FSL_IFC_V1_1_0)
ret = fsl_ifc_sram_init(ver);
if (ret)
return ret;
if (ver >= FSL_IFC_V2_0_0)
priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
ret = nand_scan_ident(mtd, 1, NULL);
if (ret)

6
drivers/mtd/nand/fsl_ifc_spl.c
View File

@ -97,7 +97,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
int pages_per_blk;
int blk_size;
int bad_marker = 0;
int bufnum_mask, bufnum;
int bufnum_mask, bufnum, ver = 0;
int csor, cspr;
int pos = 0;
@ -130,6 +130,10 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
bad_marker = 5;
}
ver = ifc_in32(&ifc->ifc_rev);
if (ver >= FSL_IFC_V2_0_0)
bufnum_mask = (bufnum_mask * 2) + 1;
pages_per_blk =
32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);

3
drivers/net/fm/fm.h
View File

@ -143,6 +143,7 @@ struct fm_eth {
#define MAX_RXBUF_LOG2 11
#define MAX_RXBUF_LEN (1 << MAX_RXBUF_LOG2)
#define PORT_IS_ENABLED(port) fm_info[fm_port_to_index(port)].enabled
#define PORT_IS_ENABLED(port) (fm_port_to_index(port) == -1 ? \
0 : fm_info[fm_port_to_index(port)].enabled)
#endif /* __FM_H__ */

6
drivers/net/fm/init.c
View File

@ -147,6 +147,9 @@ void fm_disable_port(enum fm_port port)
{
int i = fm_port_to_index(port);
if (i == -1)
return;
fm_info[i].enabled = 0;
fman_disable_port(port);
}
@ -155,6 +158,9 @@ void fm_enable_port(enum fm_port port)
{
int i = fm_port_to_index(port);
if (i == -1)
return;
fm_info[i].enabled = 1;
fman_enable_port(port);
}

10
drivers/pci/fsl_pci_init.c
View File

@ -504,8 +504,14 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
}
#endif
if (!enabled) {
/* Let the user know there's no PCIe link */
printf("no link, regs @ 0x%lx\n", pci_info->regs);
/* Let the user know there's no PCIe link for root
* complex. for endpoint, the link may not setup, so
* print undetermined.
*/
if (fsl_is_pci_agent(hose))
printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
else
printf("no link, regs @ 0x%lx\n", pci_info->regs);
hose->last_busno = hose->first_busno;
return;
}

2
drivers/qe/qe.c
View File

@ -11,7 +11,7 @@
#include <command.h>
#include "asm/errno.h"
#include "asm/io.h"
#include "asm/immap_qe.h"
#include "linux/immap_qe.h"
#include "qe.h"
#define MPC85xx_DEVDISR_QE_DISABLE 0x1

2
drivers/qe/uccf.c
View File

@ -11,7 +11,7 @@
#include "malloc.h"
#include "asm/errno.h"
#include "asm/io.h"
#include "asm/immap_qe.h"
#include "linux/immap_qe.h"
#include "qe.h"
#include "uccf.h"

2
drivers/qe/uccf.h
View File

@ -12,7 +12,7 @@
#include "common.h"
#include "qe.h"
#include "asm/immap_qe.h"
#include "linux/immap_qe.h"
/* Fast or Giga ethernet
*/

2
drivers/qe/uec.c
View File

@ -11,7 +11,7 @@
#include "malloc.h"
#include "asm/errno.h"
#include "asm/io.h"
#include "asm/immap_qe.h"
#include "linux/immap_qe.h"
#include "qe.h"
#include "uccf.h"
#include "uec.h"

2
drivers/qe/uec_phy.c
View File

@ -14,7 +14,7 @@
#include "net.h"
#include "malloc.h"
#include "asm/errno.h"
#include "asm/immap_qe.h"
#include "linux/immap_qe.h"
#include "asm/io.h"
#include "qe.h"
#include "uccf.h"

2
include/configs/B4860QDS.h
View File

@ -340,7 +340,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x0) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0

2
include/configs/BSC9132QDS.h
View File

@ -354,7 +354,7 @@ combinations. this should be removed later
#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x0) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3 0x0
#endif

2
include/configs/C29XPCIE.h
View File

@ -319,7 +319,7 @@
#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x0) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3 0x0

2
include/configs/P1010RDB.h
View File

@ -537,7 +537,7 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x0) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0

479
include/configs/P1023RDS.h
View File

@ -1,479 +0,0 @@
/*
* Copyright 2010-2012 Freescale Semiconductor, Inc.
*
* Authors: Roy Zang <tie-fei.zang@freescale.com>
* Chunhe Lan <b25806@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* p1023rds board configuration file
*
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_P1023
#define CONFIG_P1023RDS
#define CONFIG_MP /* support multiple processors */
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_SYS_CLK_FREQ 66666666
#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_HWCONFIG
#define CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x1fffffff /* fix me, only 1G */
#define CONFIG_PANIC_HANG /* do not reset board on panic */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* Implement conversion of
addresses in the LBC */
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
/* These are used when DDR doesn't use SPD. */
#define CONFIG_SYS_SDRAM_SIZE 2048u /* DDR is 2GB */
/* Default settings for "stable" mode */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
#define CONFIG_SYS_DDR_TIMING_3 0x00020000
#define CONFIG_SYS_DDR_TIMING_0 0x40110104
#define CONFIG_SYS_DDR_TIMING_1 0x5C59E544
#define CONFIG_SYS_DDR_TIMING_2 0x0fA888CA
#define CONFIG_SYS_DDR_MODE_1 0x00441210
#define CONFIG_SYS_DDR_MODE_2 0x00000000
#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
#define CONFIG_SYS_DDR_INTERVAL 0x0A280100
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
#define CONFIG_SYS_DDR_CLK_CTRL 0x01800000
#define CONFIG_SYS_DDR_TIMING_4 0x00000001
#define CONFIG_SYS_DDR_TIMING_5 0x01401400
#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F605
#define CONFIG_SYS_DDR_CONTROL 0xC70C0008 /* Type = DDR3: No Interleaving */
#define CONFIG_SYS_DDR_CONTROL2 0x24401010
#define CONFIG_SYS_DDR_CDR1 0x00000000
#define CONFIG_SYS_DDR_CDR2 0x00000000
#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
#define CONFIG_SYS_DDR_SBE 0x00000000
/* Settings that differ for "performance" mode */
#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014302
#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5C58E544
#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0FA888CA
/* Type = DDR3: cs0-cs1 interleaving */
#define CONFIG_SYS_DDR_CONTROL_PERF 0xC70C4008
#define CONFIG_SYS_DDR_CDR_1 0x00000000
#define CONFIG_SYS_DDR_CDR_2 0x00000000
/*
* Memory map
*
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
*
* Localbus non-cacheable
* 0xe000_0000 0xe003_ffff BCSR 256K BCSR
* 0xee00_0000 0xefff_ffff NOR flash 32M NOR flash
* 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M
* 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
* 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
*/
/*
* Local Bus Definitions
*/
#define CONFIG_SYS_BCSR_BASE 0xe0000000 /* start of on board FPGA */
#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
#define CONFIG_SYS_FLASH_BASE 0xee000000 /* start of FLASH 32M */
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
| BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#if defined(CONFIG_SYS_SPL)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
#ifndef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE 0xffa00000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#else
#define CONFIG_SYS_NAND_BASE 0xfff00000
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#endif
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
/* NAND boot: 4K NAND loader config */
#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
/* chip select 1 - BCSR */
#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
| BR_MS_GPCM | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
| OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
| OR_GPCM_EAD)
/* Serial Port
* open - index 2
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#ifdef CONFIG_NAND_SPL
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
/*
* Pass open firmware flat tree
*/
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_OF_STDOUT_VIA_ALIAS
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
/*
* I2C2 EEPROM
*/
#define CONFIG_ID_EEPROM
#ifdef CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#endif
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_CMD_I2C
/*
* eSPI - Enhanced SPI
*/
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_HARD_SPI
#define CONFIG_FSL_ESPI
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* controller 3, Slot 1, tgtid 3, Base address b000 */
#define CONFIG_SYS_PCIE3_NAME "Slot 3"
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 2, direct to uli, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_NAME "Slot 2"
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 2, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME "Slot 1"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
#if defined(CONFIG_PCI)
#define CONFIG_E1000 /* Defind e1000 pci Ethernet card */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
/*
* Environment
*/
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000)
#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
#endif
/*
* USB
*/
#define CONFIG_HAS_FSL_DR_USB
#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI
#ifdef CONFIG_USB_EHCI
#define CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* For booting Linux, the board info and command line data
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
/*
* Environment Configuration
*/
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 1000000
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
/* Qman/Bman */
#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */
#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
/* For FM */
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHY_MARVELL
#endif
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x7
#define CONFIG_SYS_TBIPA_VALUE 8
#define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC1"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
#endif /* __CONFIG_H */

10
include/configs/T1040QDS.h
View File

@ -445,11 +445,17 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C2_SPEED 50000
#define CONFIG_SYS_FSL_I2C3_SPEED 50000
#define CONFIG_SYS_FSL_I2C4_SPEED 50000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
#define I2C_MUX_PCA_ADDR 0x77
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/

12
include/configs/T104xRDB.h
View File

@ -286,7 +286,7 @@
#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x0) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3 0x0
@ -443,11 +443,17 @@
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
#define CONFIG_SYS_FSL_I2C3_SPEED 400000
#define CONFIG_SYS_FSL_I2C4_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x70

4
include/configs/T208xQDS.h
View File

@ -11,6 +11,8 @@
#ifndef __T208xQDS_H
#define __T208xQDS_H
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_MMC
#define CONFIG_SPI_FLASH
@ -537,7 +539,7 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_SPI_FLASH
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH_STMICRO
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_RAMBOOT_PBL)
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_EON
#endif

4
include/configs/T208xRDB.h
View File

@ -11,6 +11,8 @@
#ifndef __T2080RDB_H
#define __T2080RDB_H
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_T2080RDB
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_MMC
@ -283,7 +285,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x0) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3 0x0

2
include/configs/T4240QDS.h
View File

@ -237,7 +237,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x0) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0

4
include/fsl_ifc.h
View File

@ -12,6 +12,8 @@
#include <config.h>
#include <common.h>
#define FSL_IFC_V1_1_0 0x01010000
#define FSL_IFC_V2_0_0 0x02000000
#ifdef CONFIG_SYS_FSL_IFC_LE
#define ifc_in32(a) in_le32(a)
@ -367,6 +369,8 @@
*/
/* Auto Boot Mode */
#define IFC_NAND_NCFGR_BOOT 0x80000000
/* SRAM INIT EN */
#define IFC_NAND_SRAM_INIT_EN 0x20000000
/* Addressing Mode-ROW0+n/COL0 */
#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
/* Addressing Mode-ROW0+n/COL0+n */

0
arch/powerpc/include/asm/immap_qe.h → include/linux/immap_qe.h
View File

2
include/post.h
View File

@ -38,7 +38,7 @@
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
#elif defined(CONFIG_MPC8360)
#include <asm/immap_qe.h>
#include <linux/immap_qe.h>
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
#elif defined (CONFIG_MPC85xx)