powerpc/p3041: Add various p3041 specific information
Add P3041 SoC specific information: * SERDES Table * LIODN setup * Portal configuration Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
b5debec5b5
commit
d5d2cd4331
@ -72,6 +72,7 @@ COBJS-$(CONFIG_PCI) += pci.o
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COBJS-$(CONFIG_FSL_CORENET) += portals.o
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# various SoC specific assignments
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COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
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COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
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COBJS-$(CONFIG_QE) += qe_io.o
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@ -93,6 +94,7 @@ COBJS-$(CONFIG_P1021) += p1021_serdes.o
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COBJS-$(CONFIG_P1022) += p1022_serdes.o
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COBJS-$(CONFIG_P2010) += p2020_serdes.o
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COBJS-$(CONFIG_P2020) += p2020_serdes.o
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COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
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COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
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COBJS = $(COBJS-y)
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105
arch/powerpc/cpu/mpc85xx/p3041_ids.c
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105
arch/powerpc/cpu/mpc85xx/p3041_ids.c
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@ -0,0 +1,105 @@
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/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
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/* dqrr liodn, frame data liodn, liodn off, sdest */
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SET_QP_INFO( 1, 2, 1, 0),
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SET_QP_INFO( 3, 4, 2, 1),
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SET_QP_INFO( 5, 6, 3, 2),
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SET_QP_INFO( 7, 8, 4, 3),
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SET_QP_INFO( 9, 10, 5, 4),
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SET_QP_INFO( 0, 0, 0, 5),
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SET_QP_INFO( 0, 0, 0, 6),
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SET_QP_INFO( 0, 0, 0, 7),
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SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
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SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */
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};
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struct liodn_id_table liodn_tbl[] = {
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SET_QMAN_LIODN(31),
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SET_BMAN_LIODN(32),
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SET_SDHC_LIODN(1, 64),
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SET_PME_LIODN(117),
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SET_USB_LIODN(1, "fsl-usb2-mph", 125),
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SET_USB_LIODN(2, "fsl-usb2-dr", 126),
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SET_SATA_LIODN(1, 127),
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SET_SATA_LIODN(2, 128),
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SET_PCI_LIODN(1, 193),
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SET_PCI_LIODN(2, 194),
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SET_PCI_LIODN(3, 195),
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SET_PCI_LIODN(4, 196),
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SET_DMA_LIODN(1, 197),
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SET_DMA_LIODN(2, 198),
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SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
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SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
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SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
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SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
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};
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#ifdef CONFIG_SYS_DPAA_FMAN
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struct liodn_id_table fman1_liodn_tbl[] = {
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SET_FMAN_RX_1G_LIODN(1, 0, 10),
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SET_FMAN_RX_1G_LIODN(1, 1, 11),
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SET_FMAN_RX_1G_LIODN(1, 2, 12),
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SET_FMAN_RX_1G_LIODN(1, 3, 13),
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SET_FMAN_RX_1G_LIODN(1, 4, 14),
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SET_FMAN_RX_10G_LIODN(1, 0, 15),
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};
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#endif
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struct liodn_id_table sec_liodn_tbl[] = {
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SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
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SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
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SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
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SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
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SET_SEC_RTIC_LIODN_ENTRY(a, 154),
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SET_SEC_RTIC_LIODN_ENTRY(b, 155),
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SET_SEC_RTIC_LIODN_ENTRY(c, 156),
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SET_SEC_RTIC_LIODN_ENTRY(d, 157),
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SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
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SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
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};
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struct liodn_id_table liodn_bases[] = {
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[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100),
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#ifdef CONFIG_SYS_DPAA_FMAN
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[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
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#endif
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#ifdef CONFIG_SYS_DPAA_PME
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[FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172),
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#endif
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};
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int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
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int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
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int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
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151
arch/powerpc/cpu/mpc85xx/p3041_serdes.c
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151
arch/powerpc/cpu/mpc85xx/p3041_serdes.c
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@ -0,0 +1,151 @@
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/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_serdes.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include "fsl_corenet_serdes.h"
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static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
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[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
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PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
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SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
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[0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
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PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
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SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, },
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[0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
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PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
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SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
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[0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
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AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
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NONE, NONE, SATA1, SATA2, },
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[0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
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AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
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[0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
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AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
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XAUI_FM1, XAUI_FM1, },
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[0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
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AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
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SGMII_FM1_DTSEC4, },
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[0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
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AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
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NONE, NONE, SATA1, SATA2, },
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[0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
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AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1,
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SRIO1, },
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[0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
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[0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
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NONE, NONE, },
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[0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
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NONE, NONE, SATA1, SATA2, },
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[0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE,
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SATA1, SATA2, },
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[0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
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XAUI_FM1, XAUI_FM1, },
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[0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
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SGMII_FM1_DTSEC4, },
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[0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
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NONE, NONE, SATA1, SATA2, },
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[0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
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AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
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[0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
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AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
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NONE, NONE, },
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[0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
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AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
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[0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
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AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
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NONE, NONE, },
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[0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
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AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
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XAUI_FM1, XAUI_FM1, },
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[0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
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AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
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NONE, NONE, SATA1, SATA2, },
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[0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1,
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AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
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NONE, NONE, SATA1, SATA2, },
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[0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
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NONE, NONE, },
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[0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
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AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
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NONE, NONE, SATA1, SATA2, },
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[0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
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AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
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NONE, SATA1, SATA2, },
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[0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
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XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
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[0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
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AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
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NONE, SATA1, SATA2, },
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[0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
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XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
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};
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enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
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{
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if (!serdes_lane_enabled(lane))
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return NONE;
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return serdes_cfg_tbl[cfg][lane];
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}
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int is_serdes_prtcl_valid(u32 prtcl) {
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int i;
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if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (serdes_cfg_tbl[prtcl][i] != NONE)
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return 1;
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}
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return 0;
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}
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