mmc: ca_dw_mmc: add DesignWare based DM support for CAxxxx SoCs
Initial DesignWare based DM support for Cortina Access CAxxxx SoCs. Signed-off-by: Arthur Li <arthur.li@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
This commit is contained in:
Arthur Li
Peng Fan
parent
d16e18ca6c
commit
d55e4e74ce
@ -180,6 +180,7 @@ F: board/cortina/common/
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F: drivers/gpio/cortina_gpio.c
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F: drivers/watchdog/cortina_wdt.c
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F: drivers/serial/serial_cortina.c
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F: drivers/mmc/ca_dw_mmc.c
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ARM/CZ.NIC TURRIS MOX SUPPORT
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M: Marek Behun <marek.behun@nic.cz>
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@ -672,6 +673,7 @@ F: board/cortina/common/
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F: drivers/gpio/cortina_gpio.c
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F: drivers/watchdog/cortina_wdt.c
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F: drivers/serial/serial_cortina.c
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F: drivers/mmc/ca_dw_mmc.c
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MIPS MSCC
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M: Gregory CLEMENT <gregory.clement@bootlin.com>
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@ -205,6 +205,17 @@ config MMC_DW
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block, this provides host support for SD and MMC interfaces, in both
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PIO, internal DMA mode and external DMA mode.
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config MMC_DW_CORTINA
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bool "Cortina specific extensions for Synopsys DW Memory Card Interface"
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depends on DM_MMC
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depends on MMC_DW
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depends on BLK
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default n
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help
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This selects support for Cortina SoC specific extensions to the
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Synopsys DesignWare Memory Card Interface driver. Select this option
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for platforms based on Cortina CAxxxx Soc's.
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config MMC_DW_EXYNOS
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bool "Exynos specific extensions for Synopsys DW Memory Card Interface"
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depends on ARCH_EXYNOS
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@ -20,6 +20,7 @@ endif
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obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
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obj-$(CONFIG_MMC_DAVINCI) += davinci_mmc.o
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obj-$(CONFIG_MMC_DW) += dw_mmc.o
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obj-$(CONFIG_MMC_DW_CORTINA) += ca_dw_mmc.o
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obj-$(CONFIG_MMC_DW_EXYNOS) += exynos_dw_mmc.o
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obj-$(CONFIG_MMC_DW_K3) += hi6220_dw_mmc.o
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obj-$(CONFIG_MMC_DW_ROCKCHIP) += rockchip_dw_mmc.o
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181
drivers/mmc/ca_dw_mmc.c
Normal file
181
drivers/mmc/ca_dw_mmc.c
Normal file
@ -0,0 +1,181 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Cortina Access
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* Arthur Li <arthur.li@cortina-access.com>
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*/
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#include <common.h>
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#include <dwmmc.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <malloc.h>
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#include <errno.h>
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#include <dm.h>
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#include <mapmem.h>
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#define SD_CLK_SEL_MASK (0x3)
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#define SD_DLL_DEFAULT (0x143000)
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#define SD_SCLK_MAX (200000000)
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#define SD_CLK_SEL_200MHZ (0x2)
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#define SD_CLK_SEL_100MHZ (0x1)
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#define IO_DRV_SD_DS_OFFSET (16)
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#define IO_DRV_SD_DS_MASK (0xff << IO_DRV_SD_DS_OFFSET)
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#define MIN_FREQ (400000)
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DECLARE_GLOBAL_DATA_PTR;
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struct ca_mmc_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct ca_dwmmc_priv_data {
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struct dwmci_host host;
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void __iomem *sd_dll_reg;
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void __iomem *io_drv_reg;
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u8 ds;
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};
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static void ca_dwmci_clksel(struct dwmci_host *host)
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{
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struct ca_dwmmc_priv_data *priv = host->priv;
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u32 val = readl(priv->sd_dll_reg);
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if (host->bus_hz >= 200000000) {
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val &= ~SD_CLK_SEL_MASK;
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val |= SD_CLK_SEL_200MHZ;
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} else if (host->bus_hz >= 100000000) {
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val &= ~SD_CLK_SEL_MASK;
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val |= SD_CLK_SEL_100MHZ;
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} else {
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val &= ~SD_CLK_SEL_MASK;
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}
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writel(val, priv->sd_dll_reg);
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}
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static void ca_dwmci_board_init(struct dwmci_host *host)
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{
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struct ca_dwmmc_priv_data *priv = host->priv;
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u32 val = readl(priv->io_drv_reg);
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writel(SD_DLL_DEFAULT, priv->sd_dll_reg);
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val &= ~IO_DRV_SD_DS_MASK;
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if (priv && priv->ds)
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val |= priv->ds << IO_DRV_SD_DS_OFFSET;
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writel(val, priv->io_drv_reg);
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}
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unsigned int ca_dwmci_get_mmc_clock(struct dwmci_host *host, uint freq)
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{
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struct ca_dwmmc_priv_data *priv = host->priv;
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u8 sd_clk_sel = readl(priv->sd_dll_reg) & SD_CLK_SEL_MASK;
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u8 clk_div;
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switch (sd_clk_sel) {
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case 2:
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clk_div = 1;
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break;
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case 1:
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clk_div = 2;
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break;
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default:
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clk_div = 4;
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}
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return SD_SCLK_MAX / clk_div / (host->div + 1);
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}
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static int ca_dwmmc_ofdata_to_platdata(struct udevice *dev)
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{
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struct ca_dwmmc_priv_data *priv = dev_get_priv(dev);
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struct dwmci_host *host = &priv->host;
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u32 tmp;
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host->name = dev->name;
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host->dev_index = 0;
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host->buswidth = dev_read_u32_default(dev, "bus-width", 1);
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if (host->buswidth != 1 && host->buswidth != 4)
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return -EINVAL;
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host->bus_hz = dev_read_u32_default(dev, "max-frequency", 50000000);
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priv->ds = dev_read_u32_default(dev, "io_ds", 0x33);
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host->fifo_mode = dev_read_bool(dev, "fifo-mode");
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dev_read_u32(dev, "sd_dll_ctrl", &tmp);
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priv->sd_dll_reg = map_sysmem((uintptr_t)tmp, sizeof(uintptr_t));
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if (!priv->sd_dll_reg)
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return -EINVAL;
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dev_read_u32(dev, "io_drv_ctrl", &tmp);
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priv->io_drv_reg = map_sysmem((uintptr_t)tmp, sizeof(uintptr_t));
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if (!priv->io_drv_reg)
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return -EINVAL;
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host->ioaddr = dev_read_addr_ptr(dev);
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if (host->ioaddr == (void *)FDT_ADDR_T_NONE) {
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printf("DWMMC: base address is invalid\n");
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return -EINVAL;
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}
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host->priv = priv;
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return 0;
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}
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struct dm_mmc_ops ca_dwmci_dm_ops;
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static int ca_dwmmc_probe(struct udevice *dev)
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{
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struct ca_mmc_plat *plat = dev_get_platdata(dev);
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct ca_dwmmc_priv_data *priv = dev_get_priv(dev);
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struct dwmci_host *host = &priv->host;
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memcpy(&ca_dwmci_dm_ops, &dm_dwmci_ops, sizeof(struct dm_mmc_ops));
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dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, MIN_FREQ);
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if (host->buswidth == 1) {
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(&plat->cfg)->host_caps &= ~MMC_MODE_8BIT;
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(&plat->cfg)->host_caps &= ~MMC_MODE_4BIT;
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}
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host->mmc = &plat->mmc;
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host->mmc->priv = &priv->host;
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upriv->mmc = host->mmc;
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host->mmc->dev = dev;
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host->clksel = ca_dwmci_clksel;
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host->board_init = ca_dwmci_board_init;
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host->get_mmc_clk = ca_dwmci_get_mmc_clock;
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return dwmci_probe(dev);
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}
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static int ca_dwmmc_bind(struct udevice *dev)
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{
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struct ca_mmc_plat *plat = dev_get_platdata(dev);
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return dwmci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id ca_dwmmc_ids[] = {
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{ .compatible = "snps,dw-cortina" },
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{ }
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};
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U_BOOT_DRIVER(ca_dwmmc_drv) = {
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.name = "cortina_dwmmc",
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.id = UCLASS_MMC,
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.of_match = ca_dwmmc_ids,
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.ofdata_to_platdata = ca_dwmmc_ofdata_to_platdata,
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.bind = ca_dwmmc_bind,
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.ops = &ca_dwmci_dm_ops,
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.probe = ca_dwmmc_probe,
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.priv_auto_alloc_size = sizeof(struct ca_dwmmc_priv_data),
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.platdata_auto_alloc_size = sizeof(struct ca_mmc_plat),
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};
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