gpio: add Xilinx Zynq PS GPIO driver
Most of the code is taken (and adapted) from Linux kernel driver. Just add CONFIG_ZYNQ_GPIO to you config to enable it Signed-off-by: Andrea Scian <andrea.scian@dave.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Andrea Scian
Michal Simek
parent
cc555bd4f4
commit
d37c6288a6
@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2013 Xilinx, Inc.
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* Copyright (c) 2015 DAVE Embedded Systems
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -7,4 +8,69 @@
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#ifndef _ZYNQ_GPIO_H
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#define _ZYNQ_GPIO_H
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#define ZYNQ_GPIO_BASE_ADDRESS 0xE000A000
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/* Maximum banks */
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#define ZYNQ_GPIO_MAX_BANK 4
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#define ZYNQ_GPIO_BANK0_NGPIO 32
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#define ZYNQ_GPIO_BANK1_NGPIO 22
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#define ZYNQ_GPIO_BANK2_NGPIO 32
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#define ZYNQ_GPIO_BANK3_NGPIO 32
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#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
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ZYNQ_GPIO_BANK1_NGPIO + \
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ZYNQ_GPIO_BANK2_NGPIO + \
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ZYNQ_GPIO_BANK3_NGPIO)
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#define ZYNQ_GPIO_BANK0_PIN_MIN 0
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#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \
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ZYNQ_GPIO_BANK0_NGPIO - 1)
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#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1)
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#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \
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ZYNQ_GPIO_BANK1_NGPIO - 1)
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#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1)
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#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \
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ZYNQ_GPIO_BANK2_NGPIO - 1)
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#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1)
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#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \
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ZYNQ_GPIO_BANK3_NGPIO - 1)
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/* Register offsets for the GPIO device */
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/* LSW Mask & Data -WO */
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#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
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/* MSW Mask & Data -WO */
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#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
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/* Data Register-RW */
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#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
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/* Direction mode reg-RW */
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#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
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/* Output enable reg-RW */
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#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
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/* Interrupt mask reg-RO */
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#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
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/* Interrupt enable reg-WO */
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#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
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/* Interrupt disable reg-WO */
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#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
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/* Interrupt status reg-RO */
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#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
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/* Interrupt type reg-RW */
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#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
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/* Interrupt polarity reg-RW */
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#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
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/* Interrupt on any, reg-RW */
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#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
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/* Disable all interrupts mask */
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#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
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/* Mid pin number of a bank */
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#define ZYNQ_GPIO_MID_PIN_NUM 16
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/* GPIO upper 16 bit mask */
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#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
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#define BIT(x) (1<<x)
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#endif /* _ZYNQ_GPIO_H */
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@ -43,3 +43,4 @@ oby-$(CONFIG_SX151X) += sx151x.o
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obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
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obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
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obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o
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obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o
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220
drivers/gpio/zynq_gpio.c
Normal file
220
drivers/gpio/zynq_gpio.c
Normal file
@ -0,0 +1,220 @@
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/*
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* Xilinx Zynq GPIO device driver
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*
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* Copyright (C) 2015 DAVE Embedded Systems <devel@dave.eu>
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*
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* Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
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* Copyright (C) 2009 - 2014 Xilinx, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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/**
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* zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
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* for a given pin in the GPIO device
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* @pin_num: gpio pin number within the device
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* @bank_num: an output parameter used to return the bank number of the gpio
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* pin
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* @bank_pin_num: an output parameter used to return pin number within a bank
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* for the given gpio pin
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*
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* Returns the bank number and pin offset within the bank.
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*/
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static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
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unsigned int *bank_num,
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unsigned int *bank_pin_num)
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{
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switch (pin_num) {
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case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX:
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*bank_num = 0;
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*bank_pin_num = pin_num;
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break;
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case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX:
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*bank_num = 1;
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*bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN;
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break;
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case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX:
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*bank_num = 2;
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*bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN;
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break;
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case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX:
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*bank_num = 3;
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*bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN;
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break;
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default:
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printf("invalid GPIO pin number: %u\n", pin_num);
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*bank_num = 0;
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*bank_pin_num = 0;
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break;
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}
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}
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int gpio_is_valid(unsigned gpio)
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{
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return (gpio >= 0) && (gpio < ZYNQ_GPIO_NR_GPIOS);
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}
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static int check_gpio(unsigned gpio)
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{
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if (!gpio_is_valid(gpio)) {
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printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
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return -1;
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}
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return 0;
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}
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/**
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* gpio_get_value - Get the state of the specified pin of GPIO device
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* @gpio: gpio pin number within the device
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*
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* This function reads the state of the specified pin of the GPIO device.
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*
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* Return: 0 if the pin is low, 1 if pin is high.
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*/
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int gpio_get_value(unsigned gpio)
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{
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u32 data;
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unsigned int bank_num, bank_pin_num;
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if (check_gpio(gpio) < 0)
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return -1;
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zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
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data = readl(ZYNQ_GPIO_BASE_ADDRESS +
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ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
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return (data >> bank_pin_num) & 1;
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}
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/**
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* gpio_set_value - Modify the value of the pin with specified value
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* @gpio: gpio pin number within the device
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* @value: value used to modify the value of the specified pin
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*
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* This function calculates the register offset (i.e to lower 16 bits or
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* upper 16 bits) based on the given pin number and sets the value of a
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* gpio pin to the specified value. The value is either 0 or non-zero.
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*/
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int gpio_set_value(unsigned gpio, int value)
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{
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unsigned int reg_offset, bank_num, bank_pin_num;
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if (check_gpio(gpio) < 0)
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return -1;
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zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
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if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
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/* only 16 data bits in bit maskable reg */
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bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
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reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
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} else {
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reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
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}
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/*
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* get the 32 bit value to be written to the mask/data register where
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* the upper 16 bits is the mask and lower 16 bits is the data
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*/
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value = !!value;
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value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
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((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
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writel(value, ZYNQ_GPIO_BASE_ADDRESS + reg_offset);
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return 0;
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}
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/**
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* gpio_direction_input - Set the direction of the specified GPIO pin as input
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* @gpio: gpio pin number within the device
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*
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* This function uses the read-modify-write sequence to set the direction of
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* the gpio pin as input.
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*
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* Return: -1 if invalid gpio specified, 0 if successul
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*/
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int gpio_direction_input(unsigned gpio)
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{
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u32 reg;
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unsigned int bank_num, bank_pin_num;
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if (check_gpio(gpio) < 0)
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return -1;
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zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
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/* bank 0 pins 7 and 8 are special and cannot be used as inputs */
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if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
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return -1;
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/* clear the bit in direction mode reg to set the pin as input */
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reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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reg &= ~BIT(bank_pin_num);
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writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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return 0;
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}
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/**
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* gpio_direction_output - Set the direction of the specified GPIO pin as output
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* @gpio: gpio pin number within the device
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* @value: value to be written to specified pin
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*
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* This function sets the direction of specified GPIO pin as output, configures
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* the Output Enable register for the pin and uses zynq_gpio_set to set
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* the value of the pin to the value specified.
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*
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* Return: 0 always
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*/
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int gpio_direction_output(unsigned gpio, int value)
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{
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u32 reg;
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unsigned int bank_num, bank_pin_num;
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if (check_gpio(gpio) < 0)
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return -1;
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zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
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/* set the GPIO pin as output */
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reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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reg |= BIT(bank_pin_num);
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writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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/* configure the output enable reg for the pin */
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reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
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reg |= BIT(bank_pin_num);
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writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
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/* set the state of the pin */
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gpio_set_value(gpio, value);
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return 0;
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}
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/**
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* Request a gpio before using it.
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*
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* NOTE: Argument 'label' is unused.
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*/
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int gpio_request(unsigned gpio, const char *label)
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{
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if (check_gpio(gpio) < 0)
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return -1;
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return 0;
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}
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/**
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* Reset and free the gpio after using it.
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*/
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int gpio_free(unsigned gpio)
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{
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return 0;
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}
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