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microblaze: exception: fix unaligned data access register mask

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The correct mask for getting the source/destination register from ESR in
the case of an unaligned access exception is 0x3E0. With this change, a
dummy unaligned store produces the expected info:
"""
>> swi r5, r0, 0x111

 ...
 Hardware exception at 0x111 address
 Unaligned data access exception
 Unaligned word access
 Unaligned store access
 Register R5
 Return address from exception 0x7f99dfc
 ### ERROR ### Please RESET the board ###
"""

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-6-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Ovidiu Panait 2022-02-13 10:09:24 +02:00 committed by Michal Simek
parent 339f489d52
commit d1114b8340
1 changed files with 1 additions and 1 deletions
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2
arch/microblaze/cpu/exception.c
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@ -38,7 +38,7 @@ void _hw_exception_handler (void)
printf("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
printf("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
printf("Register R%x\n", (state & 0x3E) >> 5);
printf("Register R%x\n", (state & 0x3E0) >> 5);
break;
case 0x2:
puts("Illegal op-code exception\n");