clk: imx: pllv3: add PLLV3_SYS support
Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
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@ -14,6 +14,7 @@
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#include "clk.h"
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#include "clk.h"
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#define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic"
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#define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic"
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#define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys"
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#define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
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#define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
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#define BM_PLL_POWER (0x1 << 12)
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#define BM_PLL_POWER (0x1 << 12)
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@ -102,6 +103,46 @@ static const struct clk_ops clk_pllv3_generic_ops = {
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.set_rate = clk_pllv3_generic_set_rate,
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.set_rate = clk_pllv3_generic_set_rate,
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};
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};
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static ulong clk_pllv3_sys_get_rate(struct clk *clk)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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unsigned long parent_rate = clk_get_parent_rate(clk);
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u32 div = readl(pll->base) & pll->div_mask;
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return parent_rate * div / 2;
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}
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static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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unsigned long parent_rate = clk_get_parent_rate(clk);
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unsigned long min_rate = parent_rate * 54 / 2;
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unsigned long max_rate = parent_rate * 108 / 2;
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u32 val, div;
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if (rate < min_rate || rate > max_rate)
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return -EINVAL;
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div = rate * 2 / parent_rate;
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val = readl(pll->base);
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val &= ~pll->div_mask;
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val |= div;
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writel(val, pll->base);
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/* Wait for PLL to lock */
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while (!(readl(pll->base) & BM_PLL_LOCK))
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;
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return 0;
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}
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static const struct clk_ops clk_pllv3_sys_ops = {
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.enable = clk_pllv3_generic_enable,
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.disable = clk_pllv3_generic_disable,
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.get_rate = clk_pllv3_sys_get_rate,
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.set_rate = clk_pllv3_sys_set_rate,
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};
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base,
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const char *parent_name, void __iomem *base,
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u32 div_mask)
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u32 div_mask)
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@ -123,6 +164,11 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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pll->div_shift = 0;
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pll->div_shift = 0;
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pll->powerup_set = false;
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pll->powerup_set = false;
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break;
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break;
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case IMX_PLLV3_SYS:
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drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
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pll->div_shift = 0;
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pll->powerup_set = false;
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break;
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case IMX_PLLV3_USB:
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case IMX_PLLV3_USB:
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drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
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drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
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pll->div_shift = 1;
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pll->div_shift = 1;
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@ -153,6 +199,13 @@ U_BOOT_DRIVER(clk_pllv3_generic) = {
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.flags = DM_FLAG_PRE_RELOC,
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.flags = DM_FLAG_PRE_RELOC,
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};
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};
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U_BOOT_DRIVER(clk_pllv3_sys) = {
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.name = UBOOT_DM_CLK_IMX_PLLV3_SYS,
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.id = UCLASS_CLK,
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.ops = &clk_pllv3_sys_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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U_BOOT_DRIVER(clk_pllv3_usb) = {
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U_BOOT_DRIVER(clk_pllv3_usb) = {
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.name = UBOOT_DM_CLK_IMX_PLLV3_USB,
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.name = UBOOT_DM_CLK_IMX_PLLV3_USB,
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.id = UCLASS_CLK,
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.id = UCLASS_CLK,
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