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Merge branch 'master' of git://git.denx.de/u-boot-tegra

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This commit is contained in:
Tom Rini 2016-02-19 09:25:09 -05:00
commit cf432dd595
81 changed files with 4625 additions and 2209 deletions
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9
arch/arm/dts/tegra114-dalmore.dts
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@ -18,7 +18,8 @@
i2c4 = "/i2c@7000c700";
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@78000400";
usb0 = "/usb@7d008000";
usb0 = "/usb@7d000000";
usb1 = "/usb@7d008000";
};
memory {
@ -67,6 +68,12 @@
status = "okay";
};
usb@7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
};
usb@7d008000 {
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
status = "okay";

13
arch/arm/dts/tegra124-jetson-tk1.dts
View File

@ -325,6 +325,19 @@
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;

1676
arch/arm/dts/tegra124-nyan-big.dts
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File diff suppressed because it is too large Load Diff

718
arch/arm/dts/tegra124-nyan.dtsi Normal file
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@ -0,0 +1,718 @@
#include <dt-bindings/input/input.h>
#include "tegra124.dtsi"
/ {
aliases {
rtc0 = "/i2c@0,7000d000/pmic@40";
rtc1 = "/rtc@0,7000e000";
serial0 = &uarta;
};
memory {
reg = <0x80000000 0x80000000>;
};
host1x@50000000 {
hdmi@54280000 {
status = "okay";
vdd-supply = <&vdd_3v3_hdmi>;
pll-supply = <&vdd_hdmi_pll>;
hdmi-supply = <&vdd_5v0_hdmi>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio =
<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
};
sor@54540000 {
status = "okay";
nvidia,dpaux = <&dpaux>;
nvidia,panel = <&panel>;
};
dpaux@545c0000 {
vdd-supply = <&vdd_3v3_panel>;
status = "okay";
};
};
serial@70006000 {
/* Debug connector on the bottom of the board near SD card. */
status = "okay";
};
pwm@7000a000 {
status = "okay";
};
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
acodec: audio-codec@10 {
compatible = "maxim,max98090";
reg = <0x10>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
};
temperature-sensor@4c {
compatible = "ti,tmp451";
reg = <0x4c>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
#thermal-sensor-cells = <1>;
};
};
i2c@7000c400 {
status = "okay";
clock-frequency = <100000>;
trackpad@15 {
compatible = "elan,ekth3000";
reg = <0x15>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
};
i2c@7000c500 {
status = "okay";
clock-frequency = <400000>;
tpm@20 {
compatible = "infineon,slb9645tt";
reg = <0x20>;
};
};
hdmi_ddc: i2c@7000c700 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
pmic: pmic@40 {
compatible = "ams,as3722";
reg = <0x40>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
ams,system-power-controller;
#interrupt-cells = <2>;
interrupt-controller;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&as3722_default>;
as3722_default: pinmux {
gpio0 {
pins = "gpio0";
function = "gpio";
bias-pull-down;
};
gpio1 {
pins = "gpio1";
function = "gpio";
bias-pull-up;
};
gpio2_4_7 {
pins = "gpio2", "gpio4", "gpio7";
function = "gpio";
bias-pull-up;
};
gpio3_6 {
pins = "gpio3", "gpio6";
bias-high-impedance;
};
gpio5 {
pins = "gpio5";
function = "clk32k-out";
bias-pull-down;
};
};
regulators {
vsup-sd2-supply = <&vdd_5v0_sys>;
vsup-sd3-supply = <&vdd_5v0_sys>;
vsup-sd4-supply = <&vdd_5v0_sys>;
vsup-sd5-supply = <&vdd_5v0_sys>;
vin-ldo0-supply = <&vdd_1v35_lp0>;
vin-ldo1-6-supply = <&vdd_3v3_run>;
vin-ldo2-5-7-supply = <&vddio_1v8>;
vin-ldo3-4-supply = <&vdd_3v3_sys>;
vin-ldo9-10-supply = <&vdd_5v0_sys>;
vin-ldo11-supply = <&vdd_3v3_run>;
vdd_cpu: sd0 {
regulator-name = "+VDD_CPU_AP";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-min-microamp = <3500000>;
regulator-max-microamp = <3500000>;
regulator-always-on;
regulator-boot-on;
ams,ext-control = <2>;
};
sd1 {
regulator-name = "+VDD_CORE";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-min-microamp = <2500000>;
regulator-max-microamp = <4000000>;
regulator-always-on;
regulator-boot-on;
ams,ext-control = <1>;
};
vdd_1v35_lp0: sd2 {
regulator-name = "+1.35V_LP0(sd2)";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
sd3 {
regulator-name = "+1.35V_LP0(sd3)";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
vdd_1v05_run: sd4 {
regulator-name = "+1.05V_RUN";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
vddio_1v8: sd5 {
regulator-name = "+1.8V_VDDIO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
sd6 {
regulator-name = "+VDD_GPU_AP";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1200000>;
regulator-min-microamp = <3500000>;
regulator-max-microamp = <3500000>;
regulator-boot-on;
regulator-always-on;
};
ldo0 {
regulator-name = "+1.05V_RUN_AVDD";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-boot-on;
regulator-always-on;
ams,ext-control = <1>;
};
ldo1 {
regulator-name = "+1.8V_RUN_CAM";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo2 {
regulator-name = "+1.2V_GEN_AVDD";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
ldo3 {
regulator-name = "+1.00V_LP0_VDD_RTC";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
ams,enable-tracking;
};
vdd_run_cam: ldo4 {
regulator-name = "+3.3V_RUN_CAM";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo5 {
regulator-name = "+1.2V_RUN_CAM_FRONT";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vddio_sdmmc3: ldo6 {
regulator-name = "+VDDIO_SDMMC3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
ldo7 {
regulator-name = "+1.05V_RUN_CAM_REAR";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
ldo9 {
regulator-name = "+2.8V_RUN_TOUCH";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo10 {
regulator-name = "+2.8V_RUN_CAM_AF";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
ldo11 {
regulator-name = "+1.8V_RUN_VPP_FUSE";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
};
spi@7000d400 {
status = "okay";
cros_ec: cros-ec@0 {
compatible = "google,cros-ec-spi";
spi-max-frequency = <3000000>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
reg = <0>;
google,cros-ec-spi-msg-delay = <2000>;
i2c-tunnel {
compatible = "google,cros-ec-i2c-tunnel";
#address-cells = <1>;
#size-cells = <0>;
google,remote-bus = <0>;
charger: bq24735@9 {
compatible = "ti,bq24735";
reg = <0x9>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(J, 0)
GPIO_ACTIVE_HIGH>;
ti,ac-detect-gpios = <&gpio
TEGRA_GPIO(J, 0)
GPIO_ACTIVE_HIGH>;
};
battery: sbs-battery@b {
compatible = "sbs,sbs-battery";
reg = <0xb>;
sbs,i2c-retry-count = <2>;
sbs,poll-retry-count = <10>;
power-supplies = <&charger>;
};
};
};
};
spi@7000da00 {
status = "okay";
spi-max-frequency = <25000000>;
flash@0 {
compatible = "winbond,w25q32dw";
spi-max-frequency = <25000000>;
reg = <0>;
};
};
pmc@7000e400 {
nvidia,invert-interrupt;
nvidia,suspend-mode = <0>;
nvidia,cpu-pwr-good-time = <500>;
nvidia,cpu-pwr-off-time = <300>;
nvidia,core-pwr-good-time = <641 3845>;
nvidia,core-pwr-off-time = <61036>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
};
hda@70030000 {
status = "okay";
};
sdhci0_pwrseq: sdhci0_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
};
sdhci@700b0000 { /* WiFi/BT on this bus */
status = "okay";
power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
no-1-8-v;
non-removable;
mmc-pwrseq = <&sdhci0_pwrseq>;
vmmc-supply = <&vdd_3v3_lp0>;
vqmmc-supply = <&vddio_1v8>;
keep-power-in-suspend;
};
sdhci@700b0400 { /* SD Card on this bus */
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
bus-width = <4>;
no-1-8-v;
vqmmc-supply = <&vddio_sdmmc3>;
};
sdhci@700b0600 { /* eMMC on this bus */
status = "okay";
bus-width = <8>;
no-1-8-v;
non-removable;
};
/* CPU DFLL clock */
clock@70110000 {
status = "disabled";
vdd-cpu-supply = <&vdd_cpu>;
nvidia,i2c-fs-rate = <400000>;
};
ahub@70300000 {
i2s@70301100 {
status = "okay";
};
};
usb@7d000000 { /* Rear external USB port. */
status = "okay";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
};
usb-phy@7d000000 {
status = "okay";
vbus-supply = <&vdd_usb1_vbus>;
};
usb@7d004000 { /* Internal webcam. */
status = "okay";
};
usb-phy@7d004000 {
status = "okay";
vbus-supply = <&vdd_run_cam>;
};
usb@7d008000 { /* Left external USB port. */
status = "okay";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
};
usb-phy@7d008000 {
status = "okay";
vbus-supply = <&vdd_usb3_vbus>;
};
backlight: backlight {
compatible = "pwm-backlight";
enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
power-supply = <&vdd_led>;
pwms = <&pwm 1 1000000>;
default-brightness-level = <224>;
brightness-levels =
< 0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255
256>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
cpus {
cpu@0 {
vdd-cpu-supply = <&vdd_cpu>;
};
};
cpus {
cpu@0 {
vdd-cpu-supply = <&vdd_cpu>;
};
};
gpio-keys {
compatible = "gpio-keys";
lid {
label = "Lid";
gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
linux,input-type = <5>;
linux,code = <KEY_RESERVED>;
debounce-interval = <1>;
gpio-key,wakeup;
};
power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
debounce-interval = <30>;
gpio-key,wakeup;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vdd_mux: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "+VDD_MUX";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vdd_5v0_sys: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "+5V_SYS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vdd_mux>;
};
vdd_3v3_sys: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "+3.3V_SYS";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vdd_mux>;
};
vdd_3v3_run: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "+3.3V_RUN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_3v3_sys>;
};
vdd_3v3_hdmi: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vdd_3v3_run>;
};
vdd_led: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
regulator-name = "+VDD_LED";
gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_mux>;
};
vdd_5v0_ts: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
regulator-name = "+5V_VDD_TS_SW";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_5v0_sys>;
};
vdd_usb1_vbus: regulator@7 {
compatible = "regulator-fixed";
reg = <7>;
regulator-name = "+5V_USB_HS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
enable-active-high;
gpio-open-drain;
vin-supply = <&vdd_5v0_sys>;
};
vdd_usb3_vbus: regulator@8 {
compatible = "regulator-fixed";
reg = <8>;
regulator-name = "+5V_USB_SS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
enable-active-high;
gpio-open-drain;
vin-supply = <&vdd_5v0_sys>;
};
vdd_3v3_panel: regulator@9 {
compatible = "regulator-fixed";
reg = <9>;
regulator-name = "+3.3V_PANEL";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_3v3_run>;
};
vdd_3v3_lp0: regulator@10 {
compatible = "regulator-fixed";
reg = <10>;
regulator-name = "+3.3V_LP0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
/*
* TODO: find a way to wire this up with the USB EHCI
* controllers so that it can be enabled on demand.
*/
regulator-always-on;
gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_3v3_sys>;
};
vdd_hdmi_pll: regulator@11 {
compatible = "regulator-fixed";
reg = <11>;
regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
vin-supply = <&vdd_1v05_run>;
};
vdd_5v0_hdmi: regulator@12 {
compatible = "regulator-fixed";
reg = <12>;
regulator-name = "+5V_HDMI_CON";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_5v0_sys>;
};
};
sound {
nvidia,audio-routing =
"Headphones", "HPR",
"Headphones", "HPL",
"Speakers", "SPKR",
"Speakers", "SPKL",
"Mic Jack", "MICBIAS",
"DMICL", "Int Mic",
"DMICR", "Int Mic",
"IN34", "Mic Jack";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&acodec>;
clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA124_CLK_EXTERN1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
nvidia,mic-det-gpios =
<&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
};
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
priority = <200>;
};
};
#include "cros-ec-keyboard.dtsi"

14
arch/arm/dts/tegra124-venice2.dts
View File

@ -93,4 +93,18 @@
status = "okay";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
};

693
arch/arm/dts/tegra124.dtsi
View File

@ -1,14 +1,18 @@
#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/memory/tegra124-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/tegra124-car.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra124";
interrupt-parent = <&gic>;
interrupt-parent = <&lic>;
pcie-controller@01003000 {
compatible = "nvidia,tegra124-pcie";
@ -100,6 +104,8 @@
resets = <&tegra_car 27>;
reset-names = "dc";
iommus = <&mc TEGRA_SWGROUP_DC>;
nvidia,head = <0>;
};
@ -113,6 +119,8 @@
resets = <&tegra_car 26>;
reset-names = "dc";
iommus = <&mc TEGRA_SWGROUP_DCB>;
nvidia,head = <1>;
};
@ -165,49 +173,68 @@
<0x50046000 0x2000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-parent = <&gic>;
};
gpu@57000000 {
compatible = "nvidia,gk20a";
reg = <0x57000000 0x01000000>,
<0x58000000 0x01000000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";
clocks = <&tegra_car TEGRA124_CLK_GPU>,
<&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
clock-names = "gpu", "pwr";
resets = <&tegra_car 184>;
reset-names = "gpu";
iommus = <&mc TEGRA_SWGROUP_GPU>;
status = "disabled";
};
lic: interrupt-controller@60004000 {
compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
};
timer@60005000 {
compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
reg = <0x60005000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_TIMER>;
};
tegra_car: clock@60006000 {
compatible = "nvidia,tegra124-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
nvidia,external-memory-controller = <&emc>;
};
apbdma: dma@60020000 {
compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
reg = <0x60020000 0x1400>;
interrupts = <0 104 0x04
0 105 0x04
0 106 0x04
0 107 0x04
0 108 0x04
0 109 0x04
0 110 0x04
0 111 0x04
0 112 0x04
0 113 0x04
0 114 0x04
0 115 0x04
0 116 0x04
0 117 0x04
0 118 0x04
0 119 0x04
0 128 0x04
0 129 0x04
0 130 0x04
0 131 0x04
0 132 0x04
0 133 0x04
0 134 0x04
0 135 0x04
0 136 0x04
0 137 0x04
0 138 0x04
0 139 0x04
0 140 0x04
0 141 0x04
0 142 0x04
0 143 0x04>;
flow-controller@60007000 {
compatible = "nvidia,tegra124-flowctrl";
reg = <0x60007000 0x1000>;
};
actmon@6000c800 {
compatible = "nvidia,tegra124-actmon";
reg = <0x6000c800 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
<&tegra_car TEGRA124_CLK_EMC>;
clock-names = "actmon", "emc";
resets = <&tegra_car 119>;
reset-names = "actmon";
};
gpio: gpio@6000d000 {
@ -225,68 +252,73 @@
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
/*
gpio-ranges = <&pinmux 0 0 251>;
*/
};
i2c@7000c000 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>;
status = "disabled";
apbdma: dma@60020000 {
compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
reg = <0x60020000 0x1400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
resets = <&tegra_car 34>;
reset-names = "dma";
#dma-cells = <1>;
};
i2c@7000c400 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000c400 0x100>;
interrupts = <0 84 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 54>;
status = "disabled";
apbmisc@70000800 {
compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
reg = <0x70000800 0x64>, /* Chip revision */
<0x7000e864 0x04>; /* Strapping options */
};
i2c@7000c500 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000c500 0x100>;
interrupts = <0 92 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 67>;
status = "disabled";
};
i2c@7000c700 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000c700 0x100>;
interrupts = <0 120 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 103>;
status = "disabled";
};
i2c@7000d000 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000d000 0x100>;
interrupts = <0 53 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>;
status = "disabled";
};
i2c@7000d100 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000d100 0x100>;
interrupts = <0 53 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>;
status = "disabled";
pinmux: pinmux@70000868 {
compatible = "nvidia,tegra124-pinmux";
reg = <0x70000868 0x164>, /* Pad control registers */
<0x70003000 0x434>, /* Mux registers */
<0x70000820 0x008>; /* MIPI pad control */
};
/*
* There are two serial driver i.e. 8250 based simple serial
* driver and APB DMA based serial driver for higher baudrate
* and performace. To enable the 8250 based driver, the compatible
* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
* the APB DMA based serial driver, the comptible is
* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
*/
uarta: serial@70006000 {
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
@ -339,19 +371,6 @@
status = "disabled";
};
uarte: serial@70006400 {
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
reg = <0x70006400 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_UARTE>;
resets = <&tegra_car 66>;
reset-names = "serial";
dmas = <&apbdma 20>, <&apbdma 20>;
dma-names = "rx", "tx";
status = "disabled";
};
pwm: pwm@7000a000 {
compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
@ -362,75 +381,254 @@
status = "disabled";
};
i2c@7000c000 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000c000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_I2C1>;
clock-names = "div-clk";
resets = <&tegra_car 12>;
reset-names = "i2c";
dmas = <&apbdma 21>, <&apbdma 21>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c@7000c400 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000c400 0x100>;
interrupts = <0 84 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 54>;
status = "disabled";
};
i2c@7000c500 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000c500 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_I2C3>;
clock-names = "div-clk";
resets = <&tegra_car 67>;
reset-names = "i2c";
dmas = <&apbdma 23>, <&apbdma 23>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c@7000c700 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000c700 0x100>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_I2C4>;
clock-names = "div-clk";
resets = <&tegra_car 103>;
reset-names = "i2c";
dmas = <&apbdma 26>, <&apbdma 26>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c@7000d000 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000d000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_I2C5>;
clock-names = "div-clk";
resets = <&tegra_car 47>;
reset-names = "i2c";
dmas = <&apbdma 24>, <&apbdma 24>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c@7000d100 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000d100 0x100>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_I2C6>;
clock-names = "div-clk";
resets = <&tegra_car 166>;
reset-names = "i2c";
dmas = <&apbdma 30>, <&apbdma 30>;
dma-names = "rx", "tx";
status = "disabled";
};
spi@7000d400 {
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
reg = <0x7000d400 0x200>;
interrupts = <0 59 0x04>;
nvidia,dma-request-selector = <&apbdma 15>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_SBC1>;
clock-names = "spi";
resets = <&tegra_car 41>;
reset-names = "spi";
dmas = <&apbdma 15>, <&apbdma 15>;
dma-names = "rx", "tx";
status = "disabled";
clocks = <&tegra_car 41>;
};
spi@7000d600 {
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
reg = <0x7000d600 0x200>;
interrupts = <0 82 0x04>;
nvidia,dma-request-selector = <&apbdma 16>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_SBC2>;
clock-names = "spi";
resets = <&tegra_car 44>;
reset-names = "spi";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
status = "disabled";
clocks = <&tegra_car 44>;
};
spi@7000d800 {
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
reg = <0x7000d800 0x200>;
interrupts = <0 83 0x04>;
nvidia,dma-request-selector = <&apbdma 17>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_SBC3>;
clock-names = "spi";
resets = <&tegra_car 46>;
reset-names = "spi";
dmas = <&apbdma 17>, <&apbdma 17>;
dma-names = "rx", "tx";
status = "disabled";
clocks = <&tegra_car 46>;
};
spi@7000da00 {
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
reg = <0x7000da00 0x200>;
interrupts = <0 93 0x04>;
nvidia,dma-request-selector = <&apbdma 18>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_SBC4>;
clock-names = "spi";
resets = <&tegra_car 68>;
reset-names = "spi";
dmas = <&apbdma 18>, <&apbdma 18>;
dma-names = "rx", "tx";
status = "disabled";
clocks = <&tegra_car 68>;
};
spi@7000dc00 {
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
reg = <0x7000dc00 0x200>;
interrupts = <0 94 0x04>;
nvidia,dma-request-selector = <&apbdma 27>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_SBC5>;
clock-names = "spi";
resets = <&tegra_car 104>;
reset-names = "spi";
dmas = <&apbdma 27>, <&apbdma 27>;
dma-names = "rx", "tx";
status = "disabled";
clocks = <&tegra_car 104>;
};
spi@7000de00 {
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
reg = <0x7000de00 0x200>;
interrupts = <0 79 0x04>;
nvidia,dma-request-selector = <&apbdma 28>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_SBC6>;
clock-names = "spi";
resets = <&tegra_car 105>;
reset-names = "spi";
dmas = <&apbdma 28>, <&apbdma 28>;
dma-names = "rx", "tx";
status = "disabled";
clocks = <&tegra_car 105>;
};
rtc@7000e000 {
compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_RTC>;
};
pmc@7000e400 {
compatible = "nvidia,tegra124-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
};
fuse@7000f800 {
compatible = "nvidia,tegra124-efuse";
reg = <0x7000f800 0x400>;
clocks = <&tegra_car TEGRA124_CLK_FUSE>;
clock-names = "fuse";
resets = <&tegra_car 39>;
reset-names = "fuse";
};
mc: memory-controller@70019000 {
compatible = "nvidia,tegra124-mc";
reg = <0x70019000 0x1000>;
clocks = <&tegra_car TEGRA124_CLK_MC>;
clock-names = "mc";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
};
emc: emc@7001b000 {
compatible = "nvidia,tegra124-emc";
reg = <0x7001b000 0x1000>;
nvidia,memory-controller = <&mc>;
};
sata@70020000 {
compatible = "nvidia,tegra124-ahci";
reg = <0x70027000 0x2000>, /* AHCI */
<0x70020000 0x7000>; /* SATA */
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SATA>,
<&tegra_car TEGRA124_CLK_SATA_OOB>,
<&tegra_car TEGRA124_CLK_CML1>,
<&tegra_car TEGRA124_CLK_PLL_E>;
clock-names = "sata", "sata-oob", "cml1", "pll_e";
resets = <&tegra_car 124>,
<&tegra_car 123>,
<&tegra_car 129>;
reset-names = "sata", "sata-oob", "sata-cold";
phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
phy-names = "sata-phy";
status = "disabled";
};
hda@70030000 {
compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
reg = <0x70030000 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_HDA>,
<&tegra_car TEGRA124_CLK_HDA2HDMI>,
<&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
clock-names = "hda", "hda2hdmi", "hda2codec_2x";
resets = <&tegra_car 125>, /* hda */
<&tegra_car 128>, /* hda2hdmi */
<&tegra_car 111>; /* hda2codec_2x */
reset-names = "hda", "hda2hdmi", "hda2codec_2x";
status = "disabled";
};
padctl: padctl@7009f000 {
@ -445,32 +643,76 @@
sdhci@700b0000 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x700b0000 0x200>;
interrupts = <0 14 0x04>;
clocks = <&tegra_car 14>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
resets = <&tegra_car 14>;
reset-names = "sdhci";
status = "disabled";
};
sdhci@700b0200 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x700b0200 0x200>;
interrupts = <0 15 0x04>;
clocks = <&tegra_car 9>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
resets = <&tegra_car 9>;
reset-names = "sdhci";
status = "disabled";
};
sdhci@700b0400 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x700b0400 0x200>;
interrupts = <0 19 0x04>;
clocks = <&tegra_car 69>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
resets = <&tegra_car 69>;
reset-names = "sdhci";
status = "disabled";
};
sdhci@700b0600 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x700b0600 0x200>;
interrupts = <0 31 0x04>;
clocks = <&tegra_car 15>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
resets = <&tegra_car 15>;
reset-names = "sdhci";
status = "disabled";
};
soctherm: thermal-sensor@700e2000 {
compatible = "nvidia,tegra124-soctherm";
reg = <0x700e2000 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
<&tegra_car TEGRA124_CLK_SOC_THERM>;
clock-names = "tsensor", "soctherm";
resets = <&tegra_car 78>;
reset-names = "soctherm";
#thermal-sensor-cells = <1>;
};
dfll: clock@70110000 {
compatible = "nvidia,tegra124-dfll";
reg = <0x70110000 0x100>, /* DFLL control */
<0x70110000 0x100>, /* I2C output control */
<0x70110100 0x100>, /* Integrated I2C controller */
<0x70110200 0x100>; /* Look-up table RAM */
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
<&tegra_car TEGRA124_CLK_DFLL_REF>,
<&tegra_car TEGRA124_CLK_I2C5>;
clock-names = "soc", "ref", "i2c";
resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
reset-names = "dvco";
#clock-cells = <0>;
clock-output-names = "dfllCPU_out";
nvidia,sample-rate = <12500>;
nvidia,droop-ctrl = <0x00000f00>;
nvidia,force-mode = <1>;
nvidia,cf = <10>;
nvidia,ci = <0>;
nvidia,cg = <2>;
status = "disabled";
};
@ -580,27 +822,206 @@
usb@7d000000 {
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
reg = <0x7d000000 0x4000>;
interrupts = < 52 >;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
clocks = <&tegra_car TEGRA124_CLK_USBD>;
resets = <&tegra_car 22>;
reset-names = "usb";
nvidia,phy = <&phy1>;
status = "disabled";
};
phy1: usb-phy@7d000000 {
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x7d000000 0x4000>,
<0x7d000000 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USBD>,
<&tegra_car TEGRA124_CLK_PLL_U>,
<&tegra_car TEGRA124_CLK_USBD>;
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 22>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
nvidia,hssync-start-delay = <0>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
nvidia,term-range-adj = <6>;
nvidia,xcvr-setup = <9>;
nvidia,xcvr-lsfslew = <0>;
nvidia,xcvr-lsrslew = <3>;
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
nvidia,has-utmi-pad-registers;
status = "disabled";
};
usb@7d004000 {
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
reg = <0x7d004000 0x4000>;
interrupts = < 53 >;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "hsic";
clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
clocks = <&tegra_car TEGRA124_CLK_USB2>;
resets = <&tegra_car 58>;
reset-names = "usb";
nvidia,phy = <&phy2>;
status = "disabled";
};
phy2: usb-phy@7d004000 {
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x7d004000 0x4000>,
<0x7d000000 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USB2>,
<&tegra_car TEGRA124_CLK_PLL_U>,
<&tegra_car TEGRA124_CLK_USBD>;
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 58>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
nvidia,hssync-start-delay = <0>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
nvidia,term-range-adj = <6>;
nvidia,xcvr-setup = <9>;
nvidia,xcvr-lsfslew = <0>;
nvidia,xcvr-lsrslew = <3>;
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
status = "disabled";
};
usb@7d008000 {
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
reg = <0x7d008000 0x4000>;
interrupts = < 129 >;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
clocks = <&tegra_car TEGRA124_CLK_USB3>;
resets = <&tegra_car 59>;
reset-names = "usb";
nvidia,phy = <&phy3>;
status = "disabled";
};
phy3: usb-phy@7d008000 {
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x7d008000 0x4000>,
<0x7d000000 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USB3>,
<&tegra_car TEGRA124_CLK_PLL_U>,
<&tegra_car TEGRA124_CLK_USBD>;
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 59>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
nvidia,hssync-start-delay = <0>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
nvidia,term-range-adj = <6>;
nvidia,xcvr-setup = <9>;
nvidia,xcvr-lsfslew = <0>;
nvidia,xcvr-lsrslew = <3>;
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
status = "disabled";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
<&tegra_car TEGRA124_CLK_CCLK_LP>,
<&tegra_car TEGRA124_CLK_PLL_X>,
<&tegra_car TEGRA124_CLK_PLL_P>,
<&dfll>;
clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
/* FIXME: what's the actual transition time? */
clock-latency = <300000>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <3>;
};
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&{/cpus/cpu@0}>,
<&{/cpus/cpu@1}>,
<&{/cpus/cpu@2}>,
<&{/cpus/cpu@3}>;
};
thermal-zones {
cpu {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors =
<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
};
mem {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors =
<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
};
gpu {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors =
<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
};
pllx {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors =
<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
};
};

22
arch/arm/dts/tegra20-colibri.dts
View File

@ -20,7 +20,7 @@
sdhci0 = "/sdhci@c8000600";
};
host1x {
host1x@50000000 {
status = "okay";
dc@54200000 {
status = "okay";
@ -32,16 +32,19 @@
};
usb@c5000000 {
statuc = "okay";
dr_mode = "otg";
};
usb@c5004000 {
statuc = "okay";
/* VBUS_LAN */
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
};
usb@c5008000 {
statuc = "okay";
/* USBH_PEN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
};
@ -88,6 +91,23 @@
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
pwm: pwm@7000a000 {
status = "okay";
};
lcd_panel: panel {
clock = <25175000>;
xres = <640>;

44
arch/arm/dts/tegra20-harmony.dts
View File

@ -21,7 +21,7 @@
reg = <0x00000000 0x40000000>;
};
host1x {
host1x@50000000 {
status = "okay";
dc@54200000 {
status = "okay";
@ -46,30 +46,15 @@
};
};
i2c@7000c000 {
status = "disabled";
};
i2c@7000c400 {
status = "disabled";
};
i2c@7000c500 {
status = "disabled";
};
i2c@7000d000 {
status = "disabled";
};
usb@c5000000 {
status = "disabled";
};
usb@c5004000 {
statuc = "okay";
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
};
usb@c5008000 {
status = "okay";
};
sdhci@c8000200 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@ -86,6 +71,23 @@
bus-width = <8>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
pwm: pwm@7000a000 {
status = "okay";
};
lcd_panel: panel {
clock = <42430000>;
xres = <1024>;

26
arch/arm/dts/tegra20-medcom-wide.dts
View File

@ -19,7 +19,7 @@
reg = <0x00000000 0x20000000>;
};
host1x {
host1x@50000000 {
status = "okay";
dc@54200000 {
@ -36,28 +36,12 @@
clock-frequency = <216000000>;
};
i2c@7000c000 {
status = "disabled";
usb@c5008000 {
status = "okay";
};
i2c@7000c400 {
status = "disabled";
};
i2c@7000c500 {
status = "disabled";
};
i2c@7000d000 {
status = "disabled";
};
usb@c5000000 {
status = "disabled";
};
usb@c5004000 {
status = "disabled";
pwm: pwm@7000a000 {
status = "okay";
};
lcd_panel: panel {

43
arch/arm/dts/tegra20-paz00.dts
View File

@ -20,7 +20,7 @@
reg = <0x00000000 0x20000000>;
};
host1x {
host1x@50000000 {
status = "okay";
dc@54200000 {
status = "okay";
@ -35,28 +35,8 @@
clock-frequency = < 216000000 >;
};
i2c@7000c000 {
status = "disabled";
};
i2c@7000c400 {
status = "disabled";
};
i2c@7000c500 {
status = "disabled";
};
i2c@7000d000 {
status = "disabled";
};
usb@c5000000 {
status = "disabled";
};
usb@c5004000 {
status = "disabled";
usb@c5008000 {
status = "okay";
};
sdhci@c8000000 {
@ -72,6 +52,23 @@
bus-width = <8>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
pwm: pwm@7000a000 {
status = "okay";
};
lcd_panel: panel {
/* PAZ00 has 1024x600 */
clock = <54030000>;

8
arch/arm/dts/tegra20-plutux.dts
View File

@ -38,12 +38,4 @@
i2c@7000d000 {
status = "disabled";
};
usb@c5000000 {
status = "disabled";
};
usb@c5004000 {
status = "disabled";
};
};

36
arch/arm/dts/tegra20-seaboard.dts
View File

@ -31,7 +31,7 @@
reg = < 0x00000000 0x40000000 >;
};
host1x {
host1x@50000000 {
status = "okay";
dc@54200000 {
status = "okay";
@ -40,10 +40,15 @@
nvidia,panel = <&lcd_panel>;
};
};
dc@54240000 {
status = "disabled";
};
};
/* This is not used in U-Boot, but is expected to be in kernel .dts */
i2c@7000d000 {
status = "okay";
clock-frequency = <100000>;
pmic@34 {
compatible = "ti,tps6586x";
@ -75,18 +80,21 @@
};
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000c400 {
status = "disabled";
status = "okay";
};
i2c@7000c500 {
status = "okay";
clock-frequency = <100000>;
};
kbc@7000e200 {
status = "okay";
linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
@ -114,6 +122,8 @@
};
emc@7000f400 {
#address-cells = <1>;
#size-cells = <0>;
emc-table@190000 {
reg = < 190000 >;
compatible = "nvidia,tegra20-emc-table";
@ -151,6 +161,7 @@
};
usb@c5000000 {
status = "okay";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
dr_mode = "otg";
};
@ -159,6 +170,10 @@
status = "disabled";
};
usb@c5008000 {
status = "okay";
};
sdhci@c8000400 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@ -172,6 +187,23 @@
bus-width = <8>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
pwm: pwm@7000a000 {
status = "okay";
};
lcd_panel: panel {
/* Seaboard has 1366x768 */
clock = <70600000>;

15
arch/arm/dts/tegra20-tamonten.dtsi
View File

@ -8,7 +8,7 @@
reg = <0x00000000 0x20000000>;
};
host1x {
host1x@50000000 {
hdmi {
vdd-supply = <&hdmi_vdd_reg>;
pll-supply = <&hdmi_pll_reg>;
@ -483,6 +483,19 @@
status = "okay";
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
regulators {
compatible = "simple-bus";

10
arch/arm/dts/tegra20-tec.dts
View File

@ -19,7 +19,7 @@
reg = <0x00000000 0x20000000>;
};
host1x {
host1x@50000000 {
status = "okay";
dc@54200000 {
@ -52,12 +52,8 @@
status = "disabled";
};
usb@c5000000 {
status = "disabled";
};
usb@c5004000 {
status = "disabled";
pwm: pwm@7000a000 {
status = "okay";
};
lcd_panel: panel {

34
arch/arm/dts/tegra20-trimslice.dts
View File

@ -26,27 +26,11 @@
clock-frequency = <216000000>;
};
i2c@7000c000 {
status = "disabled";
};
spi@7000c380 {
status = "okay";
spi-max-frequency = <25000000>;
};
i2c@7000c400 {
status = "disabled";
};
i2c@7000c500 {
status = "disabled";
};
i2c@7000d000 {
status = "disabled";
};
pcie-controller@80003000 {
status = "okay";
@ -62,13 +46,10 @@
};
usb@c5000000 {
status = "okay";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
};
usb@c5004000 {
status = "disabled";
};
sdhci@c8000000 {
status = "okay";
bus-width = <4>;
@ -81,6 +62,19 @@
bus-width = <4>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;

43
arch/arm/dts/tegra20-ventana.dts
View File

@ -20,7 +20,7 @@
reg = <0x00000000 0x40000000>;
};
host1x {
host1x@50000000 {
status = "okay";
dc@54200000 {
status = "okay";
@ -35,28 +35,8 @@
clock-frequency = < 216000000 >;
};
i2c@7000c000 {
status = "disabled";
};
i2c@7000c400 {
status = "disabled";
};
i2c@7000c500 {
status = "disabled";
};
i2c@7000d000 {
status = "disabled";
};
usb@c5000000 {
status = "disabled";
};
usb@c5004000 {
status = "disabled";
usb@c5008000 {
status = "okay";
};
sdhci@c8000400 {
@ -72,6 +52,23 @@
bus-width = <8>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
pwm: pwm@7000a000 {
status = "okay";
};
lcd_panel: panel {
clock = <72072000>;
xres = <1366>;

35
arch/arm/dts/tegra20-whistler.dts
View File

@ -26,19 +26,8 @@
clock-frequency = < 216000000 >;
};
i2c@7000c000 {
status = "disabled";
};
i2c@7000c400 {
status = "disabled";
};
i2c@7000c500 {
status = "disabled";
};
i2c@7000d000 {
status = "okay";
clock-frequency = <100000>;
pmic@3c {
@ -56,12 +45,8 @@
};
};
usb@c5000000 {
status = "disabled";
};
usb@c5004000 {
status = "disabled";
usb@c5008000 {
status = "okay";
};
sdhci@c8000400 {
@ -74,4 +59,18 @@
status = "okay";
bus-width = <8>;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock@0 {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
};

541
arch/arm/dts/tegra20.dtsi
View File

@ -1,72 +1,94 @@
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra20";
interrupt-parent = <&intc>;
interrupt-parent = <&lic>;
host1x {
host1x@50000000 {
u-boot,dm-pre-reloc;
compatible = "nvidia,tegra20-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
interrupts = <0 65 0x04 /* mpcore syncpt */
0 67 0x04>; /* mpcore general */
status = "disabled";
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
resets = <&tegra_car 28>;
reset-names = "host1x";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x54000000 0x54000000 0x04000000>;
/* video-encoding/decoding */
mpe {
mpe@54040000 {
compatible = "nvidia,tegra20-mpe";
reg = <0x54040000 0x00040000>;
interrupts = <0 68 0x04>;
status = "disabled";
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_MPE>;
resets = <&tegra_car 60>;
reset-names = "mpe";
};
/* video input */
vi {
vi@54080000 {
compatible = "nvidia,tegra20-vi";
reg = <0x54080000 0x00040000>;
interrupts = <0 69 0x04>;
status = "disabled";
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_VI>;
resets = <&tegra_car 20>;
reset-names = "vi";
};
/* EPP */
epp {
epp@540c0000 {
compatible = "nvidia,tegra20-epp";
reg = <0x540c0000 0x00040000>;
interrupts = <0 70 0x04>;
status = "disabled";
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_EPP>;
resets = <&tegra_car 19>;
reset-names = "epp";
};
/* ISP */
isp {
isp@54100000 {
compatible = "nvidia,tegra20-isp";
reg = <0x54100000 0x00040000>;
interrupts = <0 71 0x04>;
status = "disabled";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_ISP>;
resets = <&tegra_car 23>;
reset-names = "isp";
};
/* 2D engine */
gr2d {
gr2d@54140000 {
compatible = "nvidia,tegra20-gr2d";
reg = <0x54140000 0x00040000>;
interrupts = <0 72 0x04>;
status = "disabled";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
resets = <&tegra_car 21>;
reset-names = "2d";
};
/* 3D engine */
gr3d {
gr3d@54180000 {
compatible = "nvidia,tegra20-gr3d";
reg = <0x54180000 0x00040000>;
status = "disabled";
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
resets = <&tegra_car 24>;
reset-names = "3d";
};
/* display controllers */
dc@54200000 {
u-boot,dm-pre-reloc;
compatible = "nvidia,tegra20-dc";
reg = <0x54200000 0x00040000>;
interrupts = <0 73 0x04>;
status = "disabled";
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_DISP1>,
<&tegra_car TEGRA20_CLK_PLL_P>;
clock-names = "dc", "parent";
resets = <&tegra_car 27>;
reset-names = "dc";
nvidia,head = <0>;
rgb {
status = "disabled";
@ -76,69 +98,138 @@
dc@54240000 {
compatible = "nvidia,tegra20-dc";
reg = <0x54240000 0x00040000>;
interrupts = <0 74 0x04>;
status = "disabled";
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_DISP2>,
<&tegra_car TEGRA20_CLK_PLL_P>;
clock-names = "dc", "parent";
resets = <&tegra_car 26>;
reset-names = "dc";
nvidia,head = <1>;
rgb {
status = "disabled";
};
};
/* outputs */
hdmi {
hdmi@54280000 {
compatible = "nvidia,tegra20-hdmi";
reg = <0x54280000 0x00040000>;
interrupts = <0 75 0x04>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_HDMI>,
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
clock-names = "hdmi", "parent";
resets = <&tegra_car 51>;
reset-names = "hdmi";
status = "disabled";
};
tvo {
tvo@542c0000 {
compatible = "nvidia,tegra20-tvo";
reg = <0x542c0000 0x00040000>;
interrupts = <0 76 0x04>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_TVO>;
status = "disabled";
};
dsi {
dsi@54300000 {
compatible = "nvidia,tegra20-dsi";
reg = <0x54300000 0x00040000>;
clocks = <&tegra_car TEGRA20_CLK_DSI>;
resets = <&tegra_car 48>;
reset-names = "dsi";
status = "disabled";
};
};
timer@50040600 {
compatible = "arm,cortex-a9-twd-timer";
interrupt-parent = <&intc>;
reg = <0x50040600 0x20>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&tegra_car TEGRA20_CLK_TWD>;
};
intc: interrupt-controller@50041000 {
compatible = "nvidia,tegra20-gic";
compatible = "arm,cortex-a9-gic";
reg = <0x50041000 0x1000
0x50040100 0x0100>;
interrupt-controller;
#interrupt-cells = <1>;
reg = < 0x50041000 0x1000 >,
< 0x50040100 0x0100 >;
#interrupt-cells = <3>;
interrupt-parent = <&intc>;
};
cache-controller@50043000 {
compatible = "arm,pl310-cache";
reg = <0x50043000 0x1000>;
arm,data-latency = <5 5 2>;
arm,tag-latency = <4 4 2>;
cache-unified;
cache-level = <2>;
};
lic: interrupt-controller@60004000 {
compatible = "nvidia,tegra20-ictlr";
reg = <0x60004000 0x100>,
<0x60004100 0x50>,
<0x60004200 0x50>,
<0x60004300 0x50>;
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&intc>;
};
timer@60005000 {
compatible = "nvidia,tegra20-timer";
reg = <0x60005000 0x60>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_TIMER>;
};
tegra_car: clock@60006000 {
compatible = "nvidia,tegra20-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
apbdma: dma {
flow-controller@60007000 {
compatible = "nvidia,tegra20-flowctrl";
reg = <0x60007000 0x1000>;
};
apbdma: dma@6000a000 {
compatible = "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1200>;
interrupts = <0 104 0x04
0 105 0x04
0 106 0x04
0 107 0x04
0 108 0x04
0 109 0x04
0 110 0x04
0 111 0x04
0 112 0x04
0 113 0x04
0 114 0x04
0 115 0x04
0 116 0x04
0 117 0x04
0 118 0x04
0 119 0x04>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
resets = <&tegra_car 34>;
reset-names = "dma";
#dma-cells = <1>;
};
ahb@6000c000 {
compatible = "nvidia,tegra20-ahb";
reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
};
gpio: gpio@6000d000 {
@ -155,41 +246,73 @@
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
/*
gpio-ranges = <&pinmux 0 0 224>;
*/
};
pinmux: pinmux@70000000 {
apbmisc@70000800 {
compatible = "nvidia,tegra20-apbmisc";
reg = <0x70000800 0x64 /* Chip revision */
0x70000008 0x04>; /* Strapping options */
};
pinmux: pinmux@70000014 {
compatible = "nvidia,tegra20-pinmux";
reg = < 0x70000014 0x10 /* Tri-state registers */
0x70000080 0x20 /* Mux registers */
0x700000a0 0x14 /* Pull-up/down registers */
0x70000868 0xa8 >; /* Pad control registers */
reg = <0x70000014 0x10 /* Tri-state registers */
0x70000080 0x20 /* Mux registers */
0x700000a0 0x14 /* Pull-up/down registers */
0x70000868 0xa8>; /* Pad control registers */
};
das@70000c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra20-das";
reg = <0x70000c00 0x80>;
};
i2s@70002800 {
#address-cells = <1>;
#size-cells = <0>;
tegra_ac97: ac97@70002000 {
compatible = "nvidia,tegra20-ac97";
reg = <0x70002000 0x200>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_AC97>;
resets = <&tegra_car 3>;
reset-names = "ac97";
dmas = <&apbdma 12>, <&apbdma 12>;
dma-names = "rx", "tx";
status = "disabled";
};
tegra_i2s1: i2s@70002800 {
compatible = "nvidia,tegra20-i2s";
reg = <0x70002800 0x200>;
interrupts = < 45 >;
dma-channel = < 2 >;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_I2S1>;
resets = <&tegra_car 11>;
reset-names = "i2s";
dmas = <&apbdma 2>, <&apbdma 2>;
dma-names = "rx", "tx";
status = "disabled";
};
i2s@70002a00 {
#address-cells = <1>;
#size-cells = <0>;
tegra_i2s2: i2s@70002a00 {
compatible = "nvidia,tegra20-i2s";
reg = <0x70002a00 0x200>;
interrupts = < 35 >;
dma-channel = < 1 >;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_I2S2>;
resets = <&tegra_car 18>;
reset-names = "i2s";
dmas = <&apbdma 1>, <&apbdma 1>;
dma-names = "rx", "tx";
status = "disabled";
};
/*
* There are two serial driver i.e. 8250 based simple serial
* driver and APB DMA based serial driver for higher baudrate
* and performace. To enable the 8250 based driver, the compatible
* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
* driver, the comptible is "nvidia,tegra20-hsuart".
*/
uarta: serial@70006000 {
compatible = "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
@ -266,58 +389,95 @@
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
clocks = <&tegra_car TEGRA20_CLK_PWM>;
resets = <&tegra_car 17>;
reset-names = "pwm";
status = "disabled";
};
rtc@7000e000 {
compatible = "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_RTC>;
};
i2c@7000c000 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra20-i2c";
reg = <0x7000C000 0x100>;
interrupts = < 70 >;
/* PERIPH_ID_I2C1, PLL_P_OUT3 */
clocks = <&tegra_car 12>, <&tegra_car 124>;
clocks = <&tegra_car TEGRA20_CLK_I2C1>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
resets = <&tegra_car 12>;
reset-names = "i2c";
dmas = <&apbdma 21>, <&apbdma 21>;
dma-names = "rx", "tx";
status = "disabled";
};
spi@7000c380 {
compatible = "nvidia,tegra20-sflash";
reg = <0x7000c380 0x80>;
interrupts = <0 39 0x04>;
nvidia,dma-request-selector = <&apbdma 11>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA20_CLK_SPI>;
resets = <&tegra_car 43>;
reset-names = "spi";
dmas = <&apbdma 11>, <&apbdma 11>;
dma-names = "rx", "tx";
status = "disabled";
/* PERIPH_ID_SPI1, PLLP_OUT0 */
clocks = <&tegra_car 43>;
};
i2c@7000c400 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c400 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra20-i2c";
reg = <0x7000C400 0x100>;
interrupts = < 116 >;
/* PERIPH_ID_I2C2, PLL_P_OUT3 */
clocks = <&tegra_car 54>, <&tegra_car 124>;
clocks = <&tegra_car TEGRA20_CLK_I2C2>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
resets = <&tegra_car 54>;
reset-names = "i2c";
dmas = <&apbdma 22>, <&apbdma 22>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c@7000c500 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c500 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra20-i2c";
reg = <0x7000C500 0x100>;
interrupts = < 124 >;
/* PERIPH_ID_I2C3, PLL_P_OUT3 */
clocks = <&tegra_car 67>, <&tegra_car 124>;
clocks = <&tegra_car TEGRA20_CLK_I2C3>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
resets = <&tegra_car 67>;
reset-names = "i2c";
dmas = <&apbdma 23>, <&apbdma 23>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c@7000d000 {
compatible = "nvidia,tegra20-i2c-dvc";
reg = <0x7000d000 0x200>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra20-i2c-dvc";
reg = <0x7000D000 0x200>;
interrupts = < 85 >;
/* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
clocks = <&tegra_car 47>, <&tegra_car 124>;
clocks = <&tegra_car TEGRA20_CLK_DVC>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
clock-names = "div-clk", "fast-clk";
resets = <&tegra_car 47>;
reset-names = "i2c";
dmas = <&apbdma 24>, <&apbdma 24>;
dma-names = "rx", "tx";
status = "disabled";
};
spi@7000d400 {
@ -376,17 +536,50 @@
status = "disabled";
};
kbc@7000e200 {
compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x0078>;
reg = <0x7000e200 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_KBC>;
resets = <&tegra_car 36>;
reset-names = "kbc";
status = "disabled";
};
emc@7000f400 {
#address-cells = < 1 >;
#size-cells = < 0 >;
pmc@7000e400 {
compatible = "nvidia,tegra20-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
};
memory-controller@7000f000 {
compatible = "nvidia,tegra20-mc";
reg = <0x7000f000 0x024
0x7000f03c 0x3c4>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
};
iommu@7000f024 {
compatible = "nvidia,tegra20-gart";
reg = <0x7000f024 0x00000018 /* controller registers */
0x58000000 0x02000000>; /* GART aperture */
};
memory-controller@7000f400 {
compatible = "nvidia,tegra20-emc";
reg = <0x7000f400 0x200>;
#address-cells = <1>;
#size-cells = <0>;
};
fuse@7000f800 {
compatible = "nvidia,tegra20-efuse";
reg = <0x7000f800 0x400>;
clocks = <&tegra_car TEGRA20_CLK_FUSE>;
clock-names = "fuse";
resets = <&tegra_car 39>;
reset-names = "fuse";
};
pcie-controller@80003000 {
@ -416,9 +609,12 @@
clocks = <&tegra_car TEGRA20_CLK_PEX>,
<&tegra_car TEGRA20_CLK_AFI>,
<&tegra_car TEGRA20_CLK_PCIE_XCLK>,
<&tegra_car TEGRA20_CLK_PLL_E>;
clock-names = "pex", "afi", "pcie_xclk", "pll_e";
clock-names = "pex", "afi", "pll_e";
resets = <&tegra_car 70>,
<&tegra_car 72>,
<&tegra_car 74>;
reset-names = "pex", "afi", "pcie_x";
status = "disabled";
pci@1,0 {
@ -451,57 +647,158 @@
usb@c5000000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5000000 0x4000>;
interrupts = < 52 >;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
nvidia,has-legacy-mode;
clocks = <&tegra_car TEGRA20_CLK_USBD>;
resets = <&tegra_car 22>;
reset-names = "usb";
nvidia,needs-double-reset;
nvidia,phy = <&phy1>;
status = "disabled";
};
phy1: usb-phy@c5000000 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA20_CLK_USBD>,
<&tegra_car TEGRA20_CLK_PLL_U>,
<&tegra_car TEGRA20_CLK_CLK_M>,
<&tegra_car TEGRA20_CLK_USBD>;
clock-names = "reg", "pll_u", "timer", "utmi-pads";
resets = <&tegra_car 22>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
nvidia,has-legacy-mode;
nvidia,hssync-start-delay = <9>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
nvidia,term-range-adj = <6>;
nvidia,xcvr-setup = <9>;
nvidia,xcvr-lsfslew = <1>;
nvidia,xcvr-lsrslew = <1>;
nvidia,has-utmi-pad-registers;
status = "disabled";
};
usb@c5004000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5004000 0x4000>;
interrupts = < 53 >;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "ulpi";
clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
clocks = <&tegra_car TEGRA20_CLK_USB2>;
resets = <&tegra_car 58>;
reset-names = "usb";
nvidia,phy = <&phy2>;
status = "disabled";
};
phy2: usb-phy@c5004000 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5004000 0x4000>;
phy_type = "ulpi";
clocks = <&tegra_car TEGRA20_CLK_USB2>,
<&tegra_car TEGRA20_CLK_PLL_U>,
<&tegra_car TEGRA20_CLK_CDEV2>;
clock-names = "reg", "pll_u", "ulpi-link";
resets = <&tegra_car 58>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
status = "disabled";
};
usb@c5008000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5008000 0x4000>;
interrupts = < 129 >;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
clocks = <&tegra_car TEGRA20_CLK_USB3>;
resets = <&tegra_car 59>;
reset-names = "usb";
nvidia,phy = <&phy3>;
status = "disabled";
};
phy3: usb-phy@c5008000 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA20_CLK_USB3>,
<&tegra_car TEGRA20_CLK_PLL_U>,
<&tegra_car TEGRA20_CLK_CLK_M>,
<&tegra_car TEGRA20_CLK_USBD>;
clock-names = "reg", "pll_u", "timer", "utmi-pads";
resets = <&tegra_car 59>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
nvidia,hssync-start-delay = <9>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
nvidia,term-range-adj = <6>;
nvidia,xcvr-setup = <9>;
nvidia,xcvr-lsfslew = <2>;
nvidia,xcvr-lsrslew = <2>;
status = "disabled";
};
sdhci@c8000000 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000000 0x200>;
interrupts = <0 14 0x04>;
clocks = <&tegra_car 14>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
resets = <&tegra_car 14>;
reset-names = "sdhci";
status = "disabled";
};
sdhci@c8000200 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000200 0x200>;
interrupts = <0 15 0x04>;
clocks = <&tegra_car 9>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
resets = <&tegra_car 9>;
reset-names = "sdhci";
status = "disabled";
};
sdhci@c8000400 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000400 0x200>;
interrupts = <0 19 0x04>;
clocks = <&tegra_car 69>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
resets = <&tegra_car 69>;
reset-names = "sdhci";
status = "disabled";
};
sdhci@c8000600 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000600 0x200>;
interrupts = <0 31 0x04>;
clocks = <&tegra_car 15>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
resets = <&tegra_car 15>;
reset-names = "sdhci";
status = "disabled";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
};
};

5
arch/arm/include/asm/arch-tegra/dc.h
View File

@ -566,9 +566,4 @@ enum {
#define DC_N_WINDOWS 5
#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5)
struct display_timing;
int display_init(void *lcdbase, int fb_bits_per_pixel,
struct display_timing *timing);
#endif /* __ASM_ARCH_TEGRA_DC_H */

30
arch/arm/include/asm/arch-tegra/pwm.h
View File

@ -27,34 +27,4 @@ struct pwm_ctlr {
#define PWM_DIVIDER_SHIFT 0
#define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT)
/**
* Program the PWM with the given parameters.
*
* @param channel PWM channel to update
* @param rate Clock rate to use for PWM, or 0 to leave alone
* @param pulse_width high pulse width: 0=always low, 1=1/256 pulse high,
* n = n/256 pulse high
* @param freq_divider frequency divider value (1 to use rate as is)
*/
void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider);
/**
* Request a pwm channel as referenced by a device tree node.
*
* This channel can then be passed to pwm_enable().
*
* @param blob Device tree blob
* @param node Node containing reference to pwm
* @param prop_name Property name of pwm reference
* @return channel number, if ok, else -1
*/
int pwm_request(const void *blob, int node, const char *prop_name);
/**
* Set up the pwm controller, by looking it up in the fdt.
*
* @return 0 if ok, -1 if the device tree node was not found or invalid.
*/
int pwm_init(const void *blob);
#endif /* __ASM_ARCH_TEGRA_PWM_H */

108
arch/arm/include/asm/arch-tegra20/display.h
View File

@ -9,8 +9,6 @@
#define __ASM_ARCH_TEGRA_DISPLAY_H
#include <asm/arch-tegra/dc.h>
#include <fdtdec.h>
#include <asm/gpio.h>
/* This holds information about a window which can be displayed */
struct disp_ctl_win {
@ -28,110 +26,4 @@ struct disp_ctl_win {
unsigned out_h; /* Height of output window in pixels */
};
#define FDT_LCD_TIMINGS 4
enum {
FDT_LCD_TIMING_REF_TO_SYNC,
FDT_LCD_TIMING_SYNC_WIDTH,
FDT_LCD_TIMING_BACK_PORCH,
FDT_LCD_TIMING_FRONT_PORCH,
FDT_LCD_TIMING_COUNT,
};
enum lcd_cache_t {
FDT_LCD_CACHE_OFF = 0,
FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0,
FDT_LCD_CACHE_WRITE_BACK = 1 << 1,
FDT_LCD_CACHE_FLUSH = 1 << 2,
FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK |
FDT_LCD_CACHE_FLUSH,
};
/* Information about the display controller */
struct fdt_disp_config {
int valid; /* config is valid */
int width; /* width in pixels */
int height; /* height in pixels */
int bpp; /* number of bits per pixel */
/*
* log2 of number of bpp, in general, unless it bpp is 24 in which
* case this field holds 24 also! This is a U-Boot thing.
*/
int log2_bpp;
struct disp_ctlr *disp; /* Display controller to use */
fdt_addr_t frame_buffer; /* Address of frame buffer */
unsigned pixel_clock; /* Pixel clock in Hz */
uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */
uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */
int panel_node; /* node offset of panel information */
};
/* Information about the LCD panel */
struct fdt_panel_config {
int pwm_channel; /* PWM channel to use for backlight */
enum lcd_cache_t cache_type;
struct gpio_desc backlight_en; /* GPIO for backlight enable */
struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */
struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */
struct gpio_desc panel_vdd; /* GPIO for panel vdd */
/*
* Panel required timings
* Timing 1: delay between panel_vdd-rise and data-rise
* Timing 2: delay between data-rise and backlight_vdd-rise
* Timing 3: delay between backlight_vdd and pwm-rise
* Timing 4: delay between pwm-rise and backlight_en-rise
*/
uint panel_timings[FDT_LCD_TIMINGS];
};
/**
* Register a new display based on device tree configuration.
*
* The frame buffer can be positioned by U-Boot or overriden by the fdt.
* You should pass in the U-Boot address here, and check the contents of
* struct fdt_disp_config to see what was actually chosen.
*
* @param blob Device tree blob
* @param default_lcd_base Default address of LCD frame buffer
* @return 0 if ok, -1 on error (unsupported bits per pixel)
*/
int tegra_display_probe(const void *blob, void *default_lcd_base);
/**
* Return the current display configuration
*
* @return pointer to display configuration, or NULL if there is no valid
* config
*/
struct fdt_disp_config *tegra_display_get_config(void);
/**
* Perform the next stage of the LCD init if it is time to do so.
*
* LCD init can be time-consuming because of the number of delays we need
* while waiting for the backlight power supply, etc. This function can
* be called at various times during U-Boot operation to advance the
* initialization of the LCD to the next stage if sufficient time has
* passed since the last stage. It keeps track of what stage it is up to
* and the time that it is permitted to move to the next stage.
*
* The final call should have wait=1 to complete the init.
*
* @param blob fdt blob containing LCD information
* @param wait 1 to wait until all init is complete, and then return
* 0 to return immediately, potentially doing nothing if it is
* not yet time for the next init.
*/
int tegra_lcd_check_next_stage(const void *blob, int wait);
/**
* Set up the maximum LCD size so we can size the frame buffer.
*
* @param blob fdt blob containing LCD information
*/
void tegra_lcd_early_init(const void *blob);
#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/

3
arch/arm/mach-tegra/Kconfig
View File

@ -9,11 +9,12 @@ config TEGRA_COMMON
select DM_KEYBOARD
select DM_PCI
select DM_PCI_COMPAT
select DM_PWM
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select OF_CONTROL
select VIDCONSOLE_AS_LCD
select VIDCONSOLE_AS_LCD if DM_VIDEO
config TEGRA_ARMV7_COMMON
bool "Tegra 32-bit common options"

1
arch/arm/mach-tegra/Makefile
View File

@ -12,7 +12,6 @@ obj-y += spl.o
obj-y += cpu.o
else
obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
obj-$(CONFIG_PWM_TEGRA) += pwm.o
endif
obj-$(CONFIG_ARM64) += arm64-mmu.o

24
arch/arm/mach-tegra/board2.c
View File

@ -13,15 +13,9 @@
#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#ifdef CONFIG_LCD
#include <asm/arch/display.h>
#endif
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/pmu.h>
#ifdef CONFIG_PWM_TEGRA
#include <asm/arch/pwm.h>
#endif
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/ap.h>
#include <asm/arch-tegra/board.h>
@ -134,13 +128,9 @@ int board_init(void)
pin_mux_spi();
#endif
#ifdef CONFIG_PWM_TEGRA
if (pwm_init(gd->fdt_blob))
debug("%s: Failed to init pwm\n", __func__);
#endif
#ifdef CONFIG_LCD
/* Init is handled automatically in the driver-model case */
#if defined(CONFIG_DM_VIDEO)
pin_mux_display();
tegra_lcd_check_next_stage(gd->fdt_blob, 0);
#endif
/* boot param addr */
gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
@ -168,12 +158,11 @@ int board_init(void)
pin_mux_usb();
#endif
#ifdef CONFIG_LCD
#if defined(CONFIG_DM_VIDEO)
board_id = tegra_board_id();
err = tegra_lcd_pmic_init(board_id);
if (err)
return err;
tegra_lcd_check_next_stage(gd->fdt_blob, 0);
#endif
#ifdef CONFIG_TEGRA_NAND
@ -221,9 +210,6 @@ int board_early_init_f(void)
/* Initialize periph GPIOs */
gpio_early_init();
gpio_early_init_uart();
#ifdef CONFIG_LCD
tegra_lcd_early_init(gd->fdt_blob);
#endif
return 0;
}
@ -231,10 +217,6 @@ int board_early_init_f(void)
int board_late_init(void)
{
#ifdef CONFIG_LCD
/* Make sure we finish initing the LCD */
tegra_lcd_check_next_stage(gd->fdt_blob, 1);
#endif
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
if (tegra_cpu_is_non_secure()) {
printf("CPU is in NS mode\n");

89
arch/arm/mach-tegra/pwm.c
View File

@ -1,89 +0,0 @@
/*
* Tegra pulse width frequency modulator definitions
*
* Copyright (c) 2011 The Chromium OS Authors.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <fdtdec.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/pwm.h>
struct pwm_info {
struct pwm_ctlr *pwm; /* Registers for our pwm controller */
int pwm_node; /* PWM device tree node */
} local;
void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider)
{
u32 reg;
assert(channel < PWM_NUM_CHANNELS);
/* TODO: Can we use clock_adjust_periph_pll_div() here? */
if (rate) {
clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ,
rate);
}
reg = PWM_ENABLE_MASK;
reg |= pulse_width << PWM_WIDTH_SHIFT;
reg |= freq_divider << PWM_DIVIDER_SHIFT;
writel(reg, &local.pwm[channel].control);
debug("%s: channel=%d, rate=%d\n", __func__, channel, rate);
}
int pwm_request(const void *blob, int node, const char *prop_name)
{
int pwm_node;
u32 data[3];
if (fdtdec_get_int_array(blob, node, prop_name, data,
ARRAY_SIZE(data))) {
debug("%s: Cannot decode PWM property '%s'\n", __func__,
prop_name);
return -1;
}
pwm_node = fdt_node_offset_by_phandle(blob, data[0]);
if (pwm_node != local.pwm_node) {
debug("%s: PWM property '%s' phandle %d not recognised"
"- expecting %d\n", __func__, prop_name, data[0],
local.pwm_node);
return -1;
}
if (data[1] >= PWM_NUM_CHANNELS) {
debug("%s: PWM property '%s': invalid channel %u\n", __func__,
prop_name, data[1]);
return -1;
}
/*
* TODO: We could maintain a list of requests, but it might not be
* worth it for U-Boot.
*/
return data[1];
}
int pwm_init(const void *blob)
{
local.pwm_node = fdtdec_next_compatible(blob, 0,
COMPAT_NVIDIA_TEGRA20_PWM);
if (local.pwm_node < 0) {
debug("%s: Cannot find device tree node\n", __func__);
return -1;
}
local.pwm = (struct pwm_ctlr *)fdtdec_get_addr(blob, local.pwm_node,
"reg");
if (local.pwm == (struct pwm_ctlr *)FDT_ADDR_T_NONE) {
debug("%s: Cannot find pwm reg address\n", __func__);
return -1;
}
debug("Tegra PWM at %p, node %d\n", local.pwm, local.pwm_node);
return 0;
}

2
arch/arm/mach-tegra/tegra20/Makefile
View File

@ -6,8 +6,6 @@
ifdef CONFIG_SPL_BUILD
obj-y += cpu.o
else
obj-$(CONFIG_VIDEO_TEGRA) += display.o
endif
# The AVP is ARMv4T architecture so we must use special compiler

378
arch/arm/mach-tegra/tegra20/display.c
View File

@ -14,381 +14,3 @@
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/timer.h>
static struct fdt_disp_config config;
static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
{
unsigned h_dda, v_dda;
unsigned long val;
val = readl(&dc->cmd.disp_win_header);
val |= WINDOW_A_SELECT;
writel(val, &dc->cmd.disp_win_header);
writel(win->fmt, &dc->win.color_depth);
clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
val = win->out_x << H_POSITION_SHIFT;
val |= win->out_y << V_POSITION_SHIFT;
writel(val, &dc->win.pos);
val = win->out_w << H_SIZE_SHIFT;
val |= win->out_h << V_SIZE_SHIFT;
writel(val, &dc->win.size);
val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
val |= win->h << V_PRESCALED_SIZE_SHIFT;
writel(val, &dc->win.prescaled_size);
writel(0, &dc->win.h_initial_dda);
writel(0, &dc->win.v_initial_dda);
h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
val = h_dda << H_DDA_INC_SHIFT;
val |= v_dda << V_DDA_INC_SHIFT;
writel(val, &dc->win.dda_increment);
writel(win->stride, &dc->win.line_stride);
writel(0, &dc->win.buf_stride);
val = WIN_ENABLE;
if (win->bpp < 24)
val |= COLOR_EXPAND;
writel(val, &dc->win.win_opt);
writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
writel(win->x, &dc->winbuf.addr_h_offset);
writel(win->y, &dc->winbuf.addr_v_offset);
writel(0xff00, &dc->win.blend_nokey);
writel(0xff00, &dc->win.blend_1win);
val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
val |= GENERAL_UPDATE | WIN_A_UPDATE;
writel(val, &dc->cmd.state_ctrl);
}
static void write_pair(struct fdt_disp_config *config, int item, u32 *reg)
{
writel(config->horiz_timing[item] |
(config->vert_timing[item] << 16), reg);
}
static int update_display_mode(struct dc_disp_reg *disp,
struct fdt_disp_config *config)
{
unsigned long val;
unsigned long rate;
unsigned long div;
writel(0x0, &disp->disp_timing_opt);
write_pair(config, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync);
write_pair(config, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width);
write_pair(config, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch);
write_pair(config, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch);
writel(config->width | (config->height << 16), &disp->disp_active);
val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
writel(val, &disp->data_enable_opt);
val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
writel(val, &disp->disp_interface_ctrl);
/*
* The pixel clock divider is in 7.1 format (where the bottom bit
* represents 0.5). Here we calculate the divider needed to get from
* the display clock (typically 600MHz) to the pixel clock. We round
* up or down as requried.
*/
rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2;
debug("Display clock %lu, divider %lu\n", rate, div);
writel(0x00010001, &disp->shift_clk_opt);
val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
val |= div << SHIFT_CLK_DIVIDER_SHIFT;
writel(val, &disp->disp_clk_ctrl);
return 0;
}
/* Start up the display and turn on power to PWMs */
static void basic_init(struct dc_cmd_reg *cmd)
{
u32 val;
writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
writel(0x0000011a, &cmd->cont_syncpt_vsync);
writel(0x00000000, &cmd->int_type);
writel(0x00000000, &cmd->int_polarity);
writel(0x00000000, &cmd->int_mask);
writel(0x00000000, &cmd->int_enb);
val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
val |= PM1_ENABLE;
writel(val, &cmd->disp_pow_ctrl);
val = readl(&cmd->disp_cmd);
val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
writel(val, &cmd->disp_cmd);
}
static void basic_init_timer(struct dc_disp_reg *disp)
{
writel(0x00000020, &disp->mem_high_pri);
writel(0x00000001, &disp->mem_high_pri_timer);
}
static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
0x00000000,
0x01000000,
0x00000000,
0x00000000,
};
static const u32 rgb_data_tab[PIN_REG_COUNT] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00210222,
0x00002200,
0x00020000,
};
static void rgb_enable(struct dc_com_reg *com)
{
int i;
for (i = 0; i < PIN_REG_COUNT; i++) {
writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
writel(rgb_data_tab[i], &com->pin_output_data[i]);
}
for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
}
static int setup_window(struct disp_ctl_win *win,
struct fdt_disp_config *config)
{
win->x = 0;
win->y = 0;
win->w = config->width;
win->h = config->height;
win->out_x = 0;
win->out_y = 0;
win->out_w = config->width;
win->out_h = config->height;
win->phys_addr = config->frame_buffer;
win->stride = config->width * (1 << config->log2_bpp) / 8;
debug("%s: depth = %d\n", __func__, config->log2_bpp);
switch (config->log2_bpp) {
case 5:
case 24:
win->fmt = COLOR_DEPTH_R8G8B8A8;
win->bpp = 32;
break;
case 4:
win->fmt = COLOR_DEPTH_B5G6R5;
win->bpp = 16;
break;
default:
debug("Unsupported LCD bit depth");
return -1;
}
return 0;
}
struct fdt_disp_config *tegra_display_get_config(void)
{
return config.valid ? &config : NULL;
}
static void debug_timing(const char *name, unsigned int timing[])
{
#ifdef DEBUG
int i;
debug("%s timing: ", name);
for (i = 0; i < FDT_LCD_TIMING_COUNT; i++)
debug("%d ", timing[i]);
debug("\n");
#endif
}
/**
* Decode panel information from the fdt, according to a standard binding
*
* @param blob fdt blob
* @param node offset of fdt node to read from
* @param config structure to store fdt config into
* @return 0 if ok, -ve on error
*/
static int tegra_decode_panel(const void *blob, int node,
struct fdt_disp_config *config)
{
int front, back, ref;
config->width = fdtdec_get_int(blob, node, "xres", -1);
config->height = fdtdec_get_int(blob, node, "yres", -1);
config->pixel_clock = fdtdec_get_int(blob, node, "clock", 0);
if (!config->pixel_clock || config->width == -1 ||
config->height == -1) {
debug("%s: Pixel parameters missing\n", __func__);
return -FDT_ERR_NOTFOUND;
}
back = fdtdec_get_int(blob, node, "left-margin", -1);
front = fdtdec_get_int(blob, node, "right-margin", -1);
ref = fdtdec_get_int(blob, node, "hsync-len", -1);
if ((back | front | ref) == -1) {
debug("%s: Horizontal parameters missing\n", __func__);
return -FDT_ERR_NOTFOUND;
}
/* Use a ref-to-sync of 1 always, and take this from the front porch */
config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
config->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
config->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
config->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
debug_timing("horiz", config->horiz_timing);
back = fdtdec_get_int(blob, node, "upper-margin", -1);
front = fdtdec_get_int(blob, node, "lower-margin", -1);
ref = fdtdec_get_int(blob, node, "vsync-len", -1);
if ((back | front | ref) == -1) {
debug("%s: Vertical parameters missing\n", __func__);
return -FDT_ERR_NOTFOUND;
}
config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
config->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
config->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
config->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC];
debug_timing("vert", config->vert_timing);
return 0;
}
/**
* Decode the display controller information from the fdt.
*
* @param blob fdt blob
* @param config structure to store fdt config into
* @return 0 if ok, -ve on error
*/
static int tegra_display_decode_config(const void *blob,
struct fdt_disp_config *config)
{
int node, rgb;
int bpp, bit;
/* TODO: Support multiple controllers */
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_DC);
if (node < 0) {
debug("%s: Cannot find display controller node in fdt\n",
__func__);
return node;
}
config->disp = (struct disp_ctlr *)fdtdec_get_addr(blob, node, "reg");
if (!config->disp) {
debug("%s: No display controller address\n", __func__);
return -1;
}
rgb = fdt_subnode_offset(blob, node, "rgb");
config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
if (config->panel_node < 0) {
debug("%s: Cannot find panel information\n", __func__);
return -1;
}
if (tegra_decode_panel(blob, config->panel_node, config)) {
debug("%s: Failed to decode panel information\n", __func__);
return -1;
}
bpp = fdtdec_get_int(blob, config->panel_node, "nvidia,bits-per-pixel",
-1);
bit = ffs(bpp) - 1;
if (bpp == (1 << bit))
config->log2_bpp = bit;
else
config->log2_bpp = bpp;
if (bpp == -1) {
debug("%s: Pixel bpp parameters missing\n", __func__);
return -FDT_ERR_NOTFOUND;
}
config->bpp = bpp;
config->valid = 1; /* we have a valid configuration */
return 0;
}
int tegra_display_probe(const void *blob, void *default_lcd_base)
{
struct disp_ctl_win window;
struct dc_ctlr *dc;
if (tegra_display_decode_config(blob, &config))
return -1;
config.frame_buffer = (u32)default_lcd_base;
dc = (struct dc_ctlr *)config.disp;
/*
* A header file for clock constants was NAKed upstream.
* TODO: Put this into the FDT and fdt_lcd struct when we have clock
* support there
*/
clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
144 * 1000000);
clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
600 * 1000000);
basic_init(&dc->cmd);
basic_init_timer(&dc->disp);
rgb_enable(&dc->com);
if (config.pixel_clock)
update_display_mode(&dc->disp, &config);
if (setup_window(&window, &config))
return -1;
update_window(dc, &window);
return 0;
}

2
board/compal/paz00/paz00.c
View File

@ -41,7 +41,7 @@ void pin_mux_mmc(void)
}
#endif
#ifdef CONFIG_LCD
#ifdef CONFIG_DM_VIDEO
/* this is a weak define that we are overriding */
void pin_mux_display(void)
{

2
board/toradex/colibri_t20/colibri_t20.c
View File

@ -114,7 +114,7 @@ void pin_mux_usb(void)
}
#endif
#ifdef CONFIG_VIDEO_TEGRA
#ifdef CONFIG_VIDEO_TEGRA20
/*
* Routine: pin_mux_display
* Description: setup the pin muxes/tristate values for the LCD interface)

6
configs/colibri_t20_defconfig
View File

@ -11,7 +11,13 @@ CONFIG_SYS_PROMPT="Colibri T20 # "
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_NFS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
CONFIG_USE_PRIVATE_LIBGCC=y

6
configs/harmony_defconfig
View File

@ -12,7 +12,13 @@ CONFIG_SYS_PROMPT="Tegra20 (Harmony) # "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
CONFIG_USE_PRIVATE_LIBGCC=y

6
configs/medcom-wide_defconfig
View File

@ -12,7 +12,13 @@ CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
CONFIG_USE_PRIVATE_LIBGCC=y

10
configs/nyan-big_defconfig
View File

@ -12,6 +12,8 @@ CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_CROS_EC_KEYB=y
@ -20,6 +22,11 @@ CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_TPM_TIS_INFINEON=y
@ -27,6 +34,9 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DISPLAY=y
CONFIG_I2C_EDID=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA124=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y

6
configs/paz00_defconfig
View File

@ -12,7 +12,13 @@ CONFIG_SYS_PROMPT="Tegra20 (Paz00) MOD # "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
CONFIG_USE_PRIVATE_LIBGCC=y

6
configs/seaboard_defconfig
View File

@ -12,7 +12,13 @@ CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
CONFIG_USE_PRIVATE_LIBGCC=y

6
configs/tec_defconfig
View File

@ -12,7 +12,13 @@ CONFIG_SYS_PROMPT="Tegra20 (TEC) # "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
CONFIG_USE_PRIVATE_LIBGCC=y

6
configs/ventana_defconfig
View File

@ -12,7 +12,13 @@ CONFIG_SYS_PROMPT="Tegra20 (Ventana) # "
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_PWM=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
CONFIG_USE_PRIVATE_LIBGCC=y

5
drivers/gpio/tegra_gpio.c
View File

@ -177,7 +177,10 @@ static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
debug("%s: pin = %d (port %d:bit %d)\n", __func__,
gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
if (get_direction(gpio) == DIRECTION_INPUT)
val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
else
val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]);
return (val >> GPIO_BIT(gpio)) & 1;
}

2
drivers/input/tegra-kbc.c
View File

@ -312,6 +312,7 @@ static int tegra_kbd_probe(struct udevice *dev)
__func__, ret);
return ret;
}
input_add_tables(input, false);
if (priv->matrix.fn_keycode) {
ret = input_add_table(input, KEY_FN, -1,
priv->matrix.fn_keycode,
@ -326,7 +327,6 @@ static int tegra_kbd_probe(struct udevice *dev)
priv->input = input;
input->dev = dev;
input->read_keys = tegra_kbc_check;
input_add_tables(input, false);
strcpy(sdev->name, "tegra-kbc");
ret = input_stdio_register(sdev);
if (ret) {

4
drivers/mmc/tegra_mmc.c
View File

@ -674,7 +674,7 @@ void tegra_mmc_init(void)
CONFIG_SYS_MMC_MAX_DEVICE);
debug("%s: count of Tegra210 sdhci nodes is %d\n", __func__, count);
if (process_nodes(blob, node_list, count)) {
printf("%s: Error processing T30 mmc node(s)!\n", __func__);
printf("%s: Error processing T210 mmc node(s)!\n", __func__);
return;
}
@ -684,7 +684,7 @@ void tegra_mmc_init(void)
CONFIG_SYS_MMC_MAX_DEVICE);
debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count);
if (process_nodes(blob, node_list, count)) {
printf("%s: Error processing T30 mmc node(s)!\n", __func__);
printf("%s: Error processing T124 mmc node(s)!\n", __func__);
return;
}

9
drivers/pwm/Kconfig
View File

@ -17,3 +17,12 @@ config PWM_ROCKCHIP
programmable period and duty cycle. A 32-bit counter is used.
Various options provided in the hardware (such as capture mode and
continuous/single-shot) are not supported by the driver.
config PWM_TEGRA
bool "Enable support for the Tegra PWM"
depends on DM_PWM
help
This PWM is found on Tegra 20 and other Nvidia SoCs. It supports
four channels with a programmable period and duty cycle. Only a
32KHz clock is supported by the driver but the duty cycle is
configurable.

3
drivers/pwm/Makefile
View File

@ -13,3 +13,6 @@
obj-$(CONFIG_DM_PWM) += pwm-uclass.o
obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o
obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
ifdef CONFIG_DM_PWM
obj-$(CONFIG_PWM_TEGRA) += tegra_pwm.o
endif

85
drivers/pwm/tegra_pwm.c Normal file
View File

@ -0,0 +1,85 @@
/*
* Copyright 2016 Google Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <pwm.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/pwm.h>
DECLARE_GLOBAL_DATA_PTR;
struct tegra_pwm_priv {
struct pwm_ctlr *regs;
};
static int tegra_pwm_set_config(struct udevice *dev, uint channel,
uint period_ns, uint duty_ns)
{
struct tegra_pwm_priv *priv = dev_get_priv(dev);
struct pwm_ctlr *regs = priv->regs;
uint pulse_width;
u32 reg;
if (channel >= 4)
return -EINVAL;
debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
/* We ignore the period here and just use 32KHz */
clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, 32768);
pulse_width = duty_ns * 255 / period_ns;
reg = pulse_width << PWM_WIDTH_SHIFT;
reg |= 1 << PWM_DIVIDER_SHIFT;
writel(reg, &regs[channel].control);
debug("%s: pulse_width=%u\n", __func__, pulse_width);
return 0;
}
static int tegra_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
{
struct tegra_pwm_priv *priv = dev_get_priv(dev);
struct pwm_ctlr *regs = priv->regs;
if (channel >= 4)
return -EINVAL;
debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel);
clrsetbits_le32(&regs[channel].control, PWM_ENABLE_MASK,
enable ? PWM_ENABLE_MASK : 0);
return 0;
}
static int tegra_pwm_ofdata_to_platdata(struct udevice *dev)
{
struct tegra_pwm_priv *priv = dev_get_priv(dev);
priv->regs = (struct pwm_ctlr *)dev_get_addr(dev);
return 0;
}
static const struct pwm_ops tegra_pwm_ops = {
.set_config = tegra_pwm_set_config,
.set_enable = tegra_pwm_set_enable,
};
static const struct udevice_id tegra_pwm_ids[] = {
{ .compatible = "nvidia,tegra124-pwm" },
{ .compatible = "nvidia,tegra20-pwm" },
{ }
};
U_BOOT_DRIVER(tegra_pwm) = {
.name = "tegra_pwm",
.id = UCLASS_PWM,
.of_match = tegra_pwm_ids,
.ops = &tegra_pwm_ops,
.ofdata_to_platdata = tegra_pwm_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct tegra_pwm_priv),
};

10
drivers/video/Kconfig
View File

@ -381,8 +381,18 @@ config VIDEO_SANDBOX_SDL
console device and can display stdout output. Within U-Boot is is
a normal bitmap display and can display images as well as text.
config VIDEO_TEGRA20
bool "Enable LCD support on Tegra20"
depends on OF_CONTROL
help
Tegra20 supports video output to an attached LCD panel as well as
other options such as HDMI. Only the LCD is supported in U-Boot.
This option enables this support which can be used on devices which
have an LCD display connected.
config VIDEO_TEGRA124
bool "Enable video support on Tegra124"
depends on DM_VIDEO
help
Tegra124 supports many video output options including eDP and
HDMI. At present only eDP is supported by U-Boot. This option

2
drivers/video/Makefile
View File

@ -57,7 +57,7 @@ obj-$(CONFIG_VIDEO_SED13806) += sed13806.o
obj-$(CONFIG_VIDEO_SM501) += sm501.o
obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o
obj-$(CONFIG_VIDEO_TEGRA) += tegra.o
obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
obj-$(CONFIG_VIDEO_VESA) += vesa_fb.o
obj-$(CONFIG_FORMIKE) += formike.o

1
drivers/video/simple_panel.c
View File

@ -85,6 +85,7 @@ static const struct panel_ops simple_panel_ops = {
static const struct udevice_id simple_panel_ids[] = {
{ .compatible = "simple-panel" },
{ .compatible = "auo,b133xtn01" },
{ }
};

678
drivers/video/tegra.c
View File

@ -4,11 +4,13 @@
*/
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <lcd.h>
#include <pwm.h>
#include <video.h>
#include <asm/system.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
@ -30,165 +32,347 @@ enum stage_t {
STAGE_DONE,
};
static enum stage_t stage; /* Current stage we are at */
static unsigned long timer_next; /* Time we can move onto next stage */
#define FDT_LCD_TIMINGS 4
/* Our LCD config, set up in handle_stage() */
static struct fdt_panel_config config;
struct fdt_disp_config *disp_config; /* Display controller config */
enum {
FDT_LCD_TIMING_REF_TO_SYNC,
FDT_LCD_TIMING_SYNC_WIDTH,
FDT_LCD_TIMING_BACK_PORCH,
FDT_LCD_TIMING_FRONT_PORCH,
FDT_LCD_TIMING_COUNT,
};
enum lcd_cache_t {
FDT_LCD_CACHE_OFF = 0,
FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0,
FDT_LCD_CACHE_WRITE_BACK = 1 << 1,
FDT_LCD_CACHE_FLUSH = 1 << 2,
FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK |
FDT_LCD_CACHE_FLUSH,
};
/* Information about the display controller */
struct tegra_lcd_priv {
enum stage_t stage; /* Current stage we are at */
unsigned long timer_next; /* Time we can move onto next stage */
int width; /* width in pixels */
int height; /* height in pixels */
/*
* log2 of number of bpp, in general, unless it bpp is 24 in which
* case this field holds 24 also! This is a U-Boot thing.
*/
int log2_bpp;
struct disp_ctlr *disp; /* Display controller to use */
fdt_addr_t frame_buffer; /* Address of frame buffer */
unsigned pixel_clock; /* Pixel clock in Hz */
uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */
uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */
struct udevice *pwm;
int pwm_channel; /* PWM channel to use for backlight */
enum lcd_cache_t cache_type;
struct gpio_desc backlight_en; /* GPIO for backlight enable */
struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */
struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */
struct gpio_desc panel_vdd; /* GPIO for panel vdd */
/*
* Panel required timings
* Timing 1: delay between panel_vdd-rise and data-rise
* Timing 2: delay between data-rise and backlight_vdd-rise
* Timing 3: delay between backlight_vdd and pwm-rise
* Timing 4: delay between pwm-rise and backlight_en-rise
*/
uint panel_timings[FDT_LCD_TIMINGS];
};
enum {
/* Maximum LCD size we support */
LCD_MAX_WIDTH = 1366,
LCD_MAX_HEIGHT = 768,
LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */
LCD_MAX_LOG2_BPP = VIDEO_BPP16,
};
vidinfo_t panel_info = {
/* Insert a value here so that we don't end up in the BSS */
.vl_col = -1,
};
#if !CONFIG_IS_ENABLED(OF_CONTROL)
#error "You must enable CONFIG_OF_CONTROL to get Tegra LCD support"
#endif
static void update_panel_size(struct fdt_disp_config *config)
static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
{
panel_info.vl_col = config->width;
panel_info.vl_row = config->height;
panel_info.vl_bpix = config->log2_bpp;
unsigned h_dda, v_dda;
unsigned long val;
val = readl(&dc->cmd.disp_win_header);
val |= WINDOW_A_SELECT;
writel(val, &dc->cmd.disp_win_header);
writel(win->fmt, &dc->win.color_depth);
clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
val = win->out_x << H_POSITION_SHIFT;
val |= win->out_y << V_POSITION_SHIFT;
writel(val, &dc->win.pos);
val = win->out_w << H_SIZE_SHIFT;
val |= win->out_h << V_SIZE_SHIFT;
writel(val, &dc->win.size);
val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
val |= win->h << V_PRESCALED_SIZE_SHIFT;
writel(val, &dc->win.prescaled_size);
writel(0, &dc->win.h_initial_dda);
writel(0, &dc->win.v_initial_dda);
h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
val = h_dda << H_DDA_INC_SHIFT;
val |= v_dda << V_DDA_INC_SHIFT;
writel(val, &dc->win.dda_increment);
writel(win->stride, &dc->win.line_stride);
writel(0, &dc->win.buf_stride);
val = WIN_ENABLE;
if (win->bpp < 24)
val |= COLOR_EXPAND;
writel(val, &dc->win.win_opt);
writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
writel(win->x, &dc->winbuf.addr_h_offset);
writel(win->y, &dc->winbuf.addr_v_offset);
writel(0xff00, &dc->win.blend_nokey);
writel(0xff00, &dc->win.blend_1win);
val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
val |= GENERAL_UPDATE | WIN_A_UPDATE;
writel(val, &dc->cmd.state_ctrl);
}
/*
* Main init function called by lcd driver.
* Inits and then prints test pattern if required.
*/
void lcd_ctrl_init(void *lcdbase)
static void write_pair(struct tegra_lcd_priv *priv, int item, u32 *reg)
{
int type = DCACHE_OFF;
int size;
assert(disp_config);
/* Make sure that we can acommodate the selected LCD */
assert(disp_config->width <= LCD_MAX_WIDTH);
assert(disp_config->height <= LCD_MAX_HEIGHT);
assert(disp_config->log2_bpp <= LCD_MAX_LOG2_BPP);
if (disp_config->width <= LCD_MAX_WIDTH
&& disp_config->height <= LCD_MAX_HEIGHT
&& disp_config->log2_bpp <= LCD_MAX_LOG2_BPP)
update_panel_size(disp_config);
size = lcd_get_size(&lcd_line_length);
/* Set up the LCD caching as requested */
if (config.cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
type = DCACHE_WRITETHROUGH;
else if (config.cache_type & FDT_LCD_CACHE_WRITE_BACK)
type = DCACHE_WRITEBACK;
mmu_set_region_dcache_behaviour(disp_config->frame_buffer, size, type);
/* Enable flushing after LCD writes if requested */
lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH);
debug("LCD frame buffer at %pa\n", &disp_config->frame_buffer);
writel(priv->horiz_timing[item] |
(priv->vert_timing[item] << 16), reg);
}
ulong calc_fbsize(void)
static int update_display_mode(struct dc_disp_reg *disp,
struct tegra_lcd_priv *priv)
{
return (panel_info.vl_col * panel_info.vl_row *
NBITS(panel_info.vl_bpix)) / 8;
}
unsigned long val;
unsigned long rate;
unsigned long div;
void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
{
}
writel(0x0, &disp->disp_timing_opt);
write_pair(priv, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync);
write_pair(priv, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width);
write_pair(priv, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch);
write_pair(priv, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch);
writel(priv->width | (priv->height << 16), &disp->disp_active);
val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
writel(val, &disp->data_enable_opt);
val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
writel(val, &disp->disp_interface_ctrl);
void tegra_lcd_early_init(const void *blob)
{
/*
* Go with the maximum size for now. We will fix this up after
* relocation. These values are only used for memory alocation.
* The pixel clock divider is in 7.1 format (where the bottom bit
* represents 0.5). Here we calculate the divider needed to get from
* the display clock (typically 600MHz) to the pixel clock. We round
* up or down as requried.
*/
panel_info.vl_col = LCD_MAX_WIDTH;
panel_info.vl_row = LCD_MAX_HEIGHT;
panel_info.vl_bpix = LCD_MAX_LOG2_BPP;
rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
debug("Display clock %lu, divider %lu\n", rate, div);
writel(0x00010001, &disp->shift_clk_opt);
val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
val |= div << SHIFT_CLK_DIVIDER_SHIFT;
writel(val, &disp->disp_clk_ctrl);
return 0;
}
/* Start up the display and turn on power to PWMs */
static void basic_init(struct dc_cmd_reg *cmd)
{
u32 val;
writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
writel(0x0000011a, &cmd->cont_syncpt_vsync);
writel(0x00000000, &cmd->int_type);
writel(0x00000000, &cmd->int_polarity);
writel(0x00000000, &cmd->int_mask);
writel(0x00000000, &cmd->int_enb);
val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
val |= PM1_ENABLE;
writel(val, &cmd->disp_pow_ctrl);
val = readl(&cmd->disp_cmd);
val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
writel(val, &cmd->disp_cmd);
}
static void basic_init_timer(struct dc_disp_reg *disp)
{
writel(0x00000020, &disp->mem_high_pri);
writel(0x00000001, &disp->mem_high_pri_timer);
}
static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
0x00000000,
0x01000000,
0x00000000,
0x00000000,
};
static const u32 rgb_data_tab[PIN_REG_COUNT] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00210222,
0x00002200,
0x00020000,
};
static void rgb_enable(struct dc_com_reg *com)
{
int i;
for (i = 0; i < PIN_REG_COUNT; i++) {
writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
writel(rgb_data_tab[i], &com->pin_output_data[i]);
}
for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
}
static int setup_window(struct disp_ctl_win *win,
struct tegra_lcd_priv *priv)
{
win->x = 0;
win->y = 0;
win->w = priv->width;
win->h = priv->height;
win->out_x = 0;
win->out_y = 0;
win->out_w = priv->width;
win->out_h = priv->height;
win->phys_addr = priv->frame_buffer;
win->stride = priv->width * (1 << priv->log2_bpp) / 8;
debug("%s: depth = %d\n", __func__, priv->log2_bpp);
switch (priv->log2_bpp) {
case 5:
case 24:
win->fmt = COLOR_DEPTH_R8G8B8A8;
win->bpp = 32;
break;
case 4:
win->fmt = COLOR_DEPTH_B5G6R5;
win->bpp = 16;
break;
default:
debug("Unsupported LCD bit depth");
return -1;
}
return 0;
}
static void debug_timing(const char *name, unsigned int timing[])
{
#ifdef DEBUG
int i;
debug("%s timing: ", name);
for (i = 0; i < FDT_LCD_TIMING_COUNT; i++)
debug("%d ", timing[i]);
debug("\n");
#endif
}
/**
* Decode the panel information from the fdt.
* Register a new display based on device tree configuration.
*
* @param blob fdt blob
* @param config structure to store fdt config into
* @return 0 if ok, -ve on error
* The frame buffer can be positioned by U-Boot or overriden by the fdt.
* You should pass in the U-Boot address here, and check the contents of
* struct tegra_lcd_priv to see what was actually chosen.
*
* @param blob Device tree blob
* @param priv Driver's private data
* @param default_lcd_base Default address of LCD frame buffer
* @return 0 if ok, -1 on error (unsupported bits per pixel)
*/
static int fdt_decode_lcd(const void *blob, struct fdt_panel_config *config)
static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
void *default_lcd_base)
{
int display_node;
struct disp_ctl_win window;
struct dc_ctlr *dc;
disp_config = tegra_display_get_config();
if (!disp_config) {
debug("%s: Display controller is not configured\n", __func__);
priv->frame_buffer = (u32)default_lcd_base;
dc = (struct dc_ctlr *)priv->disp;
/*
* A header file for clock constants was NAKed upstream.
* TODO: Put this into the FDT and fdt_lcd struct when we have clock
* support there
*/
clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
144 * 1000000);
clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
600 * 1000000);
basic_init(&dc->cmd);
basic_init_timer(&dc->disp);
rgb_enable(&dc->com);
if (priv->pixel_clock)
update_display_mode(&dc->disp, priv);
if (setup_window(&window, priv))
return -1;
}
display_node = disp_config->panel_node;
if (display_node < 0) {
debug("%s: No panel configuration available\n", __func__);
return -1;
}
config->pwm_channel = pwm_request(blob, display_node, "nvidia,pwm");
if (config->pwm_channel < 0) {
debug("%s: Unable to request PWM channel\n", __func__);
return -1;
}
update_window(dc, &window);
config->cache_type = fdtdec_get_int(blob, display_node,
"nvidia,cache-type",
FDT_LCD_CACHE_WRITE_BACK_FLUSH);
/* These GPIOs are all optional */
gpio_request_by_name_nodev(blob, display_node,
"nvidia,backlight-enable-gpios", 0,
&config->backlight_en, GPIOD_IS_OUT);
gpio_request_by_name_nodev(blob, display_node,
"nvidia,lvds-shutdown-gpios", 0,
&config->lvds_shutdown, GPIOD_IS_OUT);
gpio_request_by_name_nodev(blob, display_node,
"nvidia,backlight-vdd-gpios", 0,
&config->backlight_vdd, GPIOD_IS_OUT);
gpio_request_by_name_nodev(blob, display_node,
"nvidia,panel-vdd-gpios", 0,
&config->panel_vdd, GPIOD_IS_OUT);
return fdtdec_get_int_array(blob, display_node, "nvidia,panel-timings",
config->panel_timings, FDT_LCD_TIMINGS);
return 0;
}
/**
* Handle the next stage of device init
*/
static int handle_stage(const void *blob)
static int handle_stage(const void *blob, struct tegra_lcd_priv *priv)
{
debug("%s: stage %d\n", __func__, stage);
debug("%s: stage %d\n", __func__, priv->stage);
/* do the things for this stage */
switch (stage) {
switch (priv->stage) {
case STAGE_START:
/* Initialize the Tegra display controller */
if (tegra_display_probe(gd->fdt_blob, (void *)gd->fb_base)) {
printf("%s: Failed to probe display driver\n",
__func__);
return -1;
}
/* get panel details */
if (fdt_decode_lcd(blob, &config)) {
printf("No valid LCD information in device tree\n");
return -1;
}
/*
* It is possible that the FDT has requested that the LCD be
* disabled. We currently don't support this. It would require
@ -202,52 +386,71 @@ static int handle_stage(const void *blob)
funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
break;
case STAGE_PANEL_VDD:
if (dm_gpio_is_valid(&config.panel_vdd))
dm_gpio_set_value(&config.panel_vdd, 1);
if (dm_gpio_is_valid(&priv->panel_vdd))
dm_gpio_set_value(&priv->panel_vdd, 1);
break;
case STAGE_LVDS:
if (dm_gpio_is_valid(&config.lvds_shutdown))
dm_gpio_set_value(&config.lvds_shutdown, 1);
if (dm_gpio_is_valid(&priv->lvds_shutdown))
dm_gpio_set_value(&priv->lvds_shutdown, 1);
break;
case STAGE_BACKLIGHT_VDD:
if (dm_gpio_is_valid(&config.backlight_vdd))
dm_gpio_set_value(&config.backlight_vdd, 1);
if (dm_gpio_is_valid(&priv->backlight_vdd))
dm_gpio_set_value(&priv->backlight_vdd, 1);
break;
case STAGE_PWM:
/* Enable PWM at 15/16 high, 32768 Hz with divider 1 */
pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
pinmux_tristate_disable(PMUX_PINGRP_GPU);
pwm_enable(config.pwm_channel, 32768, 0xdf, 1);
pwm_set_config(priv->pwm, priv->pwm_channel, 0xdf, 0xff);
pwm_set_enable(priv->pwm, priv->pwm_channel, true);
break;
case STAGE_BACKLIGHT_EN:
if (dm_gpio_is_valid(&config.backlight_en))
dm_gpio_set_value(&config.backlight_en, 1);
if (dm_gpio_is_valid(&priv->backlight_en))
dm_gpio_set_value(&priv->backlight_en, 1);
break;
case STAGE_DONE:
break;
}
/* set up timer for next stage */
timer_next = timer_get_us();
if (stage < FDT_LCD_TIMINGS)
timer_next += config.panel_timings[stage] * 1000;
priv->timer_next = timer_get_us();
if (priv->stage < FDT_LCD_TIMINGS)
priv->timer_next += priv->panel_timings[priv->stage] * 1000;
/* move to next stage */
stage++;
priv->stage++;
return 0;
}
int tegra_lcd_check_next_stage(const void *blob, int wait)
/**
* Perform the next stage of the LCD init if it is time to do so.
*
* LCD init can be time-consuming because of the number of delays we need
* while waiting for the backlight power supply, etc. This function can
* be called at various times during U-Boot operation to advance the
* initialization of the LCD to the next stage if sufficient time has
* passed since the last stage. It keeps track of what stage it is up to
* and the time that it is permitted to move to the next stage.
*
* The final call should have wait=1 to complete the init.
*
* @param blob fdt blob containing LCD information
* @param wait 1 to wait until all init is complete, and then return
* 0 to return immediately, potentially doing nothing if it is
* not yet time for the next init.
*/
static int tegra_lcd_check_next_stage(const void *blob,
struct tegra_lcd_priv *priv, int wait)
{
if (stage == STAGE_DONE)
if (priv->stage == STAGE_DONE)
return 0;
do {
/* wait if we need to */
debug("%s: stage %d\n", __func__, stage);
if (stage != STAGE_START) {
int delay = timer_next - timer_get_us();
debug("%s: stage %d\n", __func__, priv->stage);
if (priv->stage != STAGE_START) {
int delay = priv->timer_next - timer_get_us();
if (delay > 0) {
if (wait)
@ -257,29 +460,188 @@ int tegra_lcd_check_next_stage(const void *blob, int wait)
}
}
if (handle_stage(blob))
if (handle_stage(blob, priv))
return -1;
} while (wait && stage != STAGE_DONE);
if (stage == STAGE_DONE)
} while (wait && priv->stage != STAGE_DONE);
if (priv->stage == STAGE_DONE)
debug("%s: LCD init complete\n", __func__);
return 0;
}
void lcd_enable(void)
static int tegra_lcd_probe(struct udevice *dev)
{
/*
* Backlight and power init will be done separately in
* tegra_lcd_check_next_stage(), which should be called in
* board_late_init().
*
* U-Boot code supports only colour depth, selected at compile time.
* The device tree setting should match this. Otherwise the display
* will not look right, and U-Boot may crash.
*/
if (disp_config->log2_bpp != LCD_BPP) {
printf("%s: Error: LCD depth configured in FDT (%d = %dbpp)"
" must match setting of LCD_BPP (%d)\n", __func__,
disp_config->log2_bpp, disp_config->bpp, LCD_BPP);
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct tegra_lcd_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
int type = DCACHE_OFF;
/* Initialize the Tegra display controller */
if (tegra_display_probe(blob, priv, (void *)plat->base)) {
printf("%s: Failed to probe display driver\n", __func__);
return -1;
}
tegra_lcd_check_next_stage(blob, priv, 1);
/* Set up the LCD caching as requested */
if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
type = DCACHE_WRITETHROUGH;
else if (priv->cache_type & FDT_LCD_CACHE_WRITE_BACK)
type = DCACHE_WRITEBACK;
mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, type);
/* Enable flushing after LCD writes if requested */
video_set_flush_dcache(dev, priv->cache_type & FDT_LCD_CACHE_FLUSH);
uc_priv->xsize = priv->width;
uc_priv->ysize = priv->height;
uc_priv->bpix = priv->log2_bpp;
debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
plat->size);
return 0;
}
static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
{
struct tegra_lcd_priv *priv = dev_get_priv(dev);
struct fdtdec_phandle_args args;
const void *blob = gd->fdt_blob;
int node = dev->of_offset;
int front, back, ref;
int panel_node;
int rgb;
int bpp, bit;
int ret;
priv->disp = (struct disp_ctlr *)dev_get_addr(dev);
if (!priv->disp) {
debug("%s: No display controller address\n", __func__);
return -EINVAL;
}
rgb = fdt_subnode_offset(blob, node, "rgb");
panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
if (panel_node < 0) {
debug("%s: Cannot find panel information\n", __func__);
return -EINVAL;
}
priv->width = fdtdec_get_int(blob, panel_node, "xres", -1);
priv->height = fdtdec_get_int(blob, panel_node, "yres", -1);
priv->pixel_clock = fdtdec_get_int(blob, panel_node, "clock", 0);
if (!priv->pixel_clock || priv->width == -1 || priv->height == -1) {
debug("%s: Pixel parameters missing\n", __func__);
return -EINVAL;
}
back = fdtdec_get_int(blob, panel_node, "left-margin", -1);
front = fdtdec_get_int(blob, panel_node, "right-margin", -1);
ref = fdtdec_get_int(blob, panel_node, "hsync-len", -1);
if ((back | front | ref) == -1) {
debug("%s: Horizontal parameters missing\n", __func__);
return -EINVAL;
}
/* Use a ref-to-sync of 1 always, and take this from the front porch */
priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
priv->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
priv->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
priv->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
debug_timing("horiz", priv->horiz_timing);
back = fdtdec_get_int(blob, panel_node, "upper-margin", -1);
front = fdtdec_get_int(blob, panel_node, "lower-margin", -1);
ref = fdtdec_get_int(blob, panel_node, "vsync-len", -1);
if ((back | front | ref) == -1) {
debug("%s: Vertical parameters missing\n", __func__);
return -EINVAL;
}
priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
priv->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
priv->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
priv->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC];
debug_timing("vert", priv->vert_timing);
bpp = fdtdec_get_int(blob, panel_node, "nvidia,bits-per-pixel", -1);
bit = ffs(bpp) - 1;
if (bpp == (1 << bit))
priv->log2_bpp = bit;
else
priv->log2_bpp = bpp;
if (bpp == -1) {
debug("%s: Pixel bpp parameters missing\n", __func__);
return -EINVAL;
}
if (fdtdec_parse_phandle_with_args(blob, panel_node, "nvidia,pwm",
"#pwm-cells", 0, 0, &args)) {
debug("%s: Unable to decode PWM\n", __func__);
return -EINVAL;
}
ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, &priv->pwm);
if (ret) {
debug("%s: Unable to find PWM\n", __func__);
return -EINVAL;
}
priv->pwm_channel = args.args[0];
priv->cache_type = fdtdec_get_int(blob, panel_node, "nvidia,cache-type",
FDT_LCD_CACHE_WRITE_BACK_FLUSH);
/* These GPIOs are all optional */
gpio_request_by_name_nodev(blob, panel_node,
"nvidia,backlight-enable-gpios", 0,
&priv->backlight_en, GPIOD_IS_OUT);
gpio_request_by_name_nodev(blob, panel_node,
"nvidia,lvds-shutdown-gpios", 0,
&priv->lvds_shutdown, GPIOD_IS_OUT);
gpio_request_by_name_nodev(blob, panel_node,
"nvidia,backlight-vdd-gpios", 0,
&priv->backlight_vdd, GPIOD_IS_OUT);
gpio_request_by_name_nodev(blob, panel_node,
"nvidia,panel-vdd-gpios", 0,
&priv->panel_vdd, GPIOD_IS_OUT);
if (fdtdec_get_int_array(blob, panel_node, "nvidia,panel-timings",
priv->panel_timings, FDT_LCD_TIMINGS))
return -EINVAL;
return 0;
}
static int tegra_lcd_bind(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << LCD_MAX_LOG2_BPP) / 8;
return 0;
}
static const struct video_ops tegra_lcd_ops = {
};
static const struct udevice_id tegra_lcd_ids[] = {
{ .compatible = "nvidia,tegra20-dc" },
{ }
};
U_BOOT_DRIVER(tegra_lcd) = {
.name = "tegra_lcd",
.id = UCLASS_VIDEO,
.of_match = tegra_lcd_ids,
.ops = &tegra_lcd_ops,
.bind = tegra_lcd_bind,
.probe = tegra_lcd_probe,
.ofdata_to_platdata = tegra_lcd_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct tegra_lcd_priv),
};

1
drivers/video/tegra124/Makefile
View File

@ -7,4 +7,3 @@
obj-y += display.o
obj-y += dp.o
obj-y += sor.o
obj-y += tegra124-lcd.o

190
drivers/video/tegra124/display.c
View File

@ -14,11 +14,13 @@
#include <edid.h>
#include <fdtdec.h>
#include <lcd.h>
#include <video.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/pwm.h>
#include <asm/arch-tegra/dc.h>
#include <dm/uclass-internal.h>
#include "displayport.h"
DECLARE_GLOBAL_DATA_PTR;
@ -333,73 +335,46 @@ static int display_update_config_from_edid(struct udevice *dp_dev,
return 0;
}
/* Somewhat torturous method */
static int get_backlight_info(const void *blob, struct gpio_desc *vdd,
struct gpio_desc *enable, int *pwmp)
{
int sor, panel, backlight, power;
const u32 *prop;
int len;
int ret;
*pwmp = 0;
sor = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_SOR);
if (sor < 0)
return -ENOENT;
panel = fdtdec_lookup_phandle(blob, sor, "nvidia,panel");
if (panel < 0)
return -ENOENT;
backlight = fdtdec_lookup_phandle(blob, panel, "backlight");
if (backlight < 0)
return -ENOENT;
ret = gpio_request_by_name_nodev(blob, backlight, "enable-gpios", 0,
enable, GPIOD_IS_OUT);
if (ret)
return ret;
prop = fdt_getprop(blob, backlight, "pwms", &len);
if (!prop || len != 3 * sizeof(u32))
return -EINVAL;
*pwmp = fdt32_to_cpu(prop[1]);
power = fdtdec_lookup_phandle(blob, backlight, "power-supply");
if (power < 0)
return -ENOENT;
ret = gpio_request_by_name_nodev(blob, power, "gpio", 0, vdd,
GPIOD_IS_OUT);
if (ret)
goto err;
return 0;
err:
dm_gpio_free(NULL, enable);
return ret;
}
int display_init(void *lcdbase, int fb_bits_per_pixel,
struct display_timing *timing)
static int display_init(struct udevice *dev, void *lcdbase,
int fb_bits_per_pixel, struct display_timing *timing)
{
struct display_plat *disp_uc_plat;
struct dc_ctlr *dc_ctlr;
const void *blob = gd->fdt_blob;
struct udevice *dp_dev;
const int href_to_sync = 1, vref_to_sync = 1;
int panel_bpp = 18; /* default 18 bits per pixel */
u32 plld_rate;
struct gpio_desc vdd_gpio, enable_gpio;
int pwm;
int node;
int ret;
ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev);
if (ret)
/*
* Before we probe the display device (eDP), tell it that this device
* is are the source of the display data.
*/
ret = uclass_find_first_device(UCLASS_DISPLAY, &dp_dev);
if (ret) {
debug("%s: device '%s' display not found (ret=%d)\n", __func__,
dev->name, ret);
return ret;
}
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC);
if (node < 0)
return -ENOENT;
dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
if (fdtdec_decode_display_timing(blob, node, 0, timing))
disp_uc_plat = dev_get_uclass_platdata(dp_dev);
debug("Found device '%s', disp_uc_priv=%p\n", dp_dev->name,
disp_uc_plat);
disp_uc_plat->src_dev = dev;
ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev);
if (ret) {
debug("%s: Failed to probe eDP, ret=%d\n", __func__, ret);
return ret;
}
dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, dev->of_offset,
"reg");
if (fdtdec_decode_display_timing(blob, dev->of_offset, 0, timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
}
ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing);
if (ret) {
@ -407,12 +382,6 @@ int display_init(void *lcdbase, int fb_bits_per_pixel,
dump_config(panel_bpp, timing);
}
if (!get_backlight_info(blob, &vdd_gpio, &enable_gpio, &pwm)) {
dm_gpio_set_value(&vdd_gpio, 1);
debug("%s: backlight vdd setting gpio %08x to %d\n",
__func__, gpio_get_number(&vdd_gpio), 1);
}
/*
* The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
* and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
@ -443,22 +412,99 @@ int display_init(void *lcdbase, int fb_bits_per_pixel,
/* Enable dp */
ret = display_enable(dp_dev, panel_bpp, timing);
if (ret)
if (ret) {
debug("dc: failed to enable display: ret=%d\n", ret);
return ret;
}
ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing);
if (ret)
if (ret) {
debug("dc: failed to update window\n");
return ret;
/* Set up Tegra PWM to drive the panel backlight */
pwm_enable(pwm, 0, 220, 0x2e);
udelay(10 * 1000);
if (dm_gpio_is_valid(&enable_gpio)) {
dm_gpio_set_value(&enable_gpio, 1);
debug("%s: backlight enable setting gpio %08x to %d\n",
__func__, gpio_get_number(&enable_gpio), 1);
}
return 0;
}
enum {
/* Maximum LCD size we support */
LCD_MAX_WIDTH = 1920,
LCD_MAX_HEIGHT = 1200,
LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */
};
static int tegra124_lcd_init(struct udevice *dev, void *lcdbase,
enum video_log2_bpp l2bpp)
{
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct display_timing timing;
int ret;
clock_set_up_plldp();
clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
clock_enable(PERIPH_ID_HOST1X);
clock_enable(PERIPH_ID_DISP1);
clock_enable(PERIPH_ID_PWM);
clock_enable(PERIPH_ID_DPAUX);
clock_enable(PERIPH_ID_SOR0);
udelay(2);
reset_set_enable(PERIPH_ID_HOST1X, 0);
reset_set_enable(PERIPH_ID_DISP1, 0);
reset_set_enable(PERIPH_ID_PWM, 0);
reset_set_enable(PERIPH_ID_DPAUX, 0);
reset_set_enable(PERIPH_ID_SOR0, 0);
ret = display_init(dev, lcdbase, 1 << l2bpp, &timing);
if (ret)
return ret;
uc_priv->xsize = roundup(timing.hactive.typ, 16);
uc_priv->ysize = timing.vactive.typ;
uc_priv->bpix = l2bpp;
video_set_flush_dcache(dev, 1);
debug("%s: done\n", __func__);
return 0;
}
static int tegra124_lcd_probe(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
ulong start;
int ret;
start = get_timer(0);
ret = tegra124_lcd_init(dev, (void *)plat->base, VIDEO_BPP16);
debug("LCD init took %lu ms\n", get_timer(start));
if (ret)
printf("%s: Error %d\n", __func__, ret);
return 0;
}
static int tegra124_lcd_bind(struct udevice *dev)
{
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << VIDEO_BPP16) / 8;
debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
return 0;
}
static const struct udevice_id tegra124_lcd_ids[] = {
{ .compatible = "nvidia,tegra124-dc" },
{ }
};
U_BOOT_DRIVER(tegra124_dc) = {
.name = "tegra124-dc",
.id = UCLASS_VIDEO,
.of_match = tegra124_lcd_ids,
.bind = tegra124_lcd_bind,
.probe = tegra124_lcd_probe,
};

53
drivers/video/tegra124/dp.c
View File

@ -11,6 +11,7 @@
#include <div64.h>
#include <errno.h>
#include <fdtdec.h>
#include <video_bridge.h>
#include <asm/io.h>
#include <asm/arch-tegra/dc.h>
#include "display.h"
@ -26,9 +27,15 @@ struct tegra_dp_plat {
ulong base;
};
/**
* struct tegra_dp_priv - private displayport driver info
*
* @dc_dev: Display controller device that is sending the video feed
*/
struct tegra_dp_priv {
struct udevice *sor;
struct udevice *dc_dev;
struct dpaux_ctlr *regs;
struct tegra_dc_sor_data *sor;
u8 revision;
int enabled;
};
@ -710,8 +717,8 @@ static int tegra_dc_dp_init_max_link_cfg(
return 0;
}
static int tegra_dc_dp_set_assr(struct tegra_dp_priv *dp,
struct tegra_dc_sor_data *sor, int ena)
static int tegra_dc_dp_set_assr(struct tegra_dp_priv *priv,
struct udevice *sor, int ena)
{
int ret;
@ -719,7 +726,7 @@ static int tegra_dc_dp_set_assr(struct tegra_dp_priv *dp,
DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_ENABLE :
DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_DISABLE;
ret = tegra_dc_dp_dpcd_write(dp, DP_EDP_CONFIGURATION_SET,
ret = tegra_dc_dp_dpcd_write(priv, DP_EDP_CONFIGURATION_SET,
dpcd_data);
if (ret)
return ret;
@ -730,7 +737,7 @@ static int tegra_dc_dp_set_assr(struct tegra_dp_priv *dp,
}
static int tegra_dp_set_link_bandwidth(struct tegra_dp_priv *dp,
struct tegra_dc_sor_data *sor,
struct udevice *sor,
u8 link_bw)
{
tegra_dc_sor_set_link_bandwidth(sor, link_bw);
@ -741,7 +748,7 @@ static int tegra_dp_set_link_bandwidth(struct tegra_dp_priv *dp,
static int tegra_dp_set_lane_count(struct tegra_dp_priv *dp,
const struct tegra_dp_link_config *link_cfg,
struct tegra_dc_sor_data *sor)
struct udevice *sor)
{
u8 dpcd_data;
int ret;
@ -1002,7 +1009,7 @@ fail:
static int tegra_dp_lt_config(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4],
u32 pc[4], const struct tegra_dp_link_config *cfg)
{
struct tegra_dc_sor_data *sor = dp->sor;
struct udevice *sor = dp->sor;
u32 n_lanes = cfg->lane_count;
u8 pc_supported = cfg->tps3_supported;
u32 cnt;
@ -1186,7 +1193,7 @@ static int tegra_dc_dp_full_link_training(struct tegra_dp_priv *dp,
const struct display_timing *timing,
struct tegra_dp_link_config *cfg)
{
struct tegra_dc_sor_data *sor = dp->sor;
struct udevice *sor = dp->sor;
int err;
u32 pe[4], vs[4], pc[4];
@ -1229,7 +1236,7 @@ fail:
*/
static int tegra_dc_dp_fast_link_training(struct tegra_dp_priv *dp,
const struct tegra_dp_link_config *link_cfg,
struct tegra_dc_sor_data *sor)
struct udevice *sor)
{
u8 link_bw;
u8 lane_count;
@ -1301,7 +1308,7 @@ static int tegra_dc_dp_fast_link_training(struct tegra_dp_priv *dp,
static int tegra_dp_do_link_training(struct tegra_dp_priv *dp,
struct tegra_dp_link_config *link_cfg,
const struct display_timing *timing,
struct tegra_dc_sor_data *sor)
struct udevice *sor)
{
u8 link_bw;
u8 lane_count;
@ -1344,7 +1351,7 @@ static int tegra_dp_do_link_training(struct tegra_dp_priv *dp,
static int tegra_dc_dp_explore_link_cfg(struct tegra_dp_priv *dp,
struct tegra_dp_link_config *link_cfg,
struct tegra_dc_sor_data *sor,
struct udevice *sor,
const struct display_timing *timing)
{
struct tegra_dp_link_config temp_cfg;
@ -1444,7 +1451,7 @@ static int tegra_dc_dp_check_sink(struct tegra_dp_priv *dp,
printf("DP: Out of sync after %d retries\n", max_retry);
return -EIO;
}
ret = tegra_dc_sor_detach(dp->sor);
ret = tegra_dc_sor_detach(dp->dc_dev, dp->sor);
if (ret)
return ret;
if (tegra_dc_dp_explore_link_cfg(dp, link_cfg, dp->sor,
@ -1454,7 +1461,7 @@ static int tegra_dc_dp_check_sink(struct tegra_dp_priv *dp,
}
tegra_dc_sor_set_power_state(dp->sor, 1);
tegra_dc_sor_attach(dp->sor, link_cfg, timing);
tegra_dc_sor_attach(dp->dc_dev, dp->sor, link_cfg, timing);
/* Increase delay_frame for next try in case the sink is
skipping more frames */
@ -1467,7 +1474,7 @@ int tegra_dp_enable(struct udevice *dev, int panel_bpp,
{
struct tegra_dp_priv *priv = dev_get_priv(dev);
struct tegra_dp_link_config slink_cfg, *link_cfg = &slink_cfg;
struct tegra_dc_sor_data *sor;
struct udevice *sor;
int data;
int retry;
int ret;
@ -1489,9 +1496,11 @@ int tegra_dp_enable(struct udevice *dev, int panel_bpp,
return -ENOLINK;
}
ret = tegra_dc_sor_init(&sor);
if (ret)
ret = uclass_first_device(UCLASS_VIDEO_BRIDGE, &sor);
if (ret || !sor) {
debug("dp: failed to find SOR device: ret=%d\n", ret);
return ret;
}
priv->sor = sor;
ret = tegra_dc_sor_enable_dp(sor, link_cfg);
if (ret)
@ -1531,7 +1540,7 @@ int tegra_dp_enable(struct udevice *dev, int panel_bpp,
}
tegra_dc_sor_set_power_state(sor, 1);
ret = tegra_dc_sor_attach(sor, link_cfg, timing);
ret = tegra_dc_sor_attach(priv->dc_dev, sor, link_cfg, timing);
if (ret && ret != -EEXIST)
return ret;
@ -1548,6 +1557,12 @@ int tegra_dp_enable(struct udevice *dev, int panel_bpp,
/* Power down the unused lanes to save power - a few hundred mW */
tegra_dc_sor_power_down_unused_lanes(sor, link_cfg);
ret = video_bridge_set_backlight(sor, 80);
if (ret) {
debug("dp: failed to set backlight\n");
return ret;
}
priv->enabled = true;
error_enable:
return 0;
@ -1583,10 +1598,14 @@ static int dp_tegra_probe(struct udevice *dev)
{
struct tegra_dp_plat *plat = dev_get_platdata(dev);
struct tegra_dp_priv *priv = dev_get_priv(dev);
struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
priv->regs = (struct dpaux_ctlr *)plat->base;
priv->enabled = false;
/* Remember the display controller that is sending us video */
priv->dc_dev = disp_uc_plat->src_dev;
return 0;
}

174
drivers/video/tegra124/sor.c
View File

@ -5,9 +5,12 @@
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
#include <panel.h>
#include <video_bridge.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/dc.h>
@ -37,6 +40,14 @@ DECLARE_GLOBAL_DATA_PTR;
#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF (0 << 25)
#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON (1 << 25)
struct tegra_dc_sor_data {
void *base;
void *pmc_base;
u8 portnum; /* 0 or 1 */
int power_is_up;
struct udevice *panel;
};
static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
{
return readl((u32 *)sor->base + reg);
@ -57,15 +68,19 @@ static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor,
tegra_sor_writel(sor, reg, reg_val);
}
void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor)
void tegra_dp_disable_tx_pu(struct udevice *dev)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
DP_PADCTL_TX_PU_MASK, DP_PADCTL_TX_PU_DISABLE);
}
void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, u32 pe_reg,
void tegra_dp_set_pe_vs_pc(struct udevice *dev, u32 mask, u32 pe_reg,
u32 vs_reg, u32 pc_reg, u8 pc_supported)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
tegra_sor_write_field(sor, PR(sor->portnum), mask, pe_reg);
tegra_sor_write_field(sor, DC(sor->portnum), mask, vs_reg);
if (pc_supported) {
@ -95,8 +110,9 @@ static int tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, u32 reg,
return -ETIMEDOUT;
}
int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd)
int tegra_dc_sor_set_power_state(struct udevice *dev, int pu_pd)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
u32 reg_val;
u32 orig_val;
@ -123,10 +139,11 @@ int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd)
return 0;
}
void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena,
void tegra_dc_sor_set_dp_linkctl(struct udevice *dev, int ena,
u8 training_pattern,
const struct tegra_dp_link_config *link_cfg)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
u32 reg_val;
reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
@ -194,9 +211,10 @@ static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor,
return 0;
}
static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor,
static int tegra_dc_sor_power_dplanes(struct udevice *dev,
u32 lane_count, int pu)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
u32 reg_val;
reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
@ -218,15 +236,15 @@ static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor,
}
tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
tegra_dc_sor_set_lane_count(sor, lane_count);
tegra_dc_sor_set_lane_count(dev, lane_count);
}
return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0);
}
void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
int power_up)
void tegra_dc_sor_set_panel_power(struct udevice *dev, int power_up)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
u32 reg_val;
reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
@ -255,14 +273,15 @@ static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
}
}
static void tegra_dc_sor_set_dp_mode(struct tegra_dc_sor_data *sor,
static void tegra_dc_sor_set_dp_mode(struct udevice *dev,
const struct tegra_dp_link_config *link_cfg)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
u32 reg_val;
tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw);
tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_none, link_cfg);
tegra_dc_sor_set_dp_linkctl(dev, 1, training_pattern_none, link_cfg);
reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum));
reg_val &= ~DP_CONFIG_WATERMARK_MASK;
reg_val |= link_cfg->watermark;
@ -351,8 +370,9 @@ static int tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up)
return 0;
}
void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int)
void tegra_dc_sor_set_internal_panel(struct udevice *dev, int is_int)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
u32 reg_val;
reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum));
@ -366,9 +386,10 @@ void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int)
tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val);
}
void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
void tegra_dc_sor_read_link_config(struct udevice *dev, u8 *link_bw,
u8 *lane_count)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
u32 reg_val;
reg_val = tegra_sor_readl(sor, CLK_CNTRL);
@ -395,15 +416,18 @@ void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
}
}
void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw)
void tegra_dc_sor_set_link_bandwidth(struct udevice *dev, u8 link_bw)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
tegra_sor_write_field(sor, CLK_CNTRL,
CLK_CNTRL_DP_LINK_SPEED_MASK,
link_bw << CLK_CNTRL_DP_LINK_SPEED_SHIFT);
}
void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count)
void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
u32 reg_val;
reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
@ -439,15 +463,16 @@ void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count)
* 4 1 0 0 0 0 0 1
* 5 0 0 0 0 0 0 1
*/
static int tegra_dc_sor_power_up(struct tegra_dc_sor_data *sor, int is_lvds)
static int tegra_dc_sor_power_up(struct udevice *dev, int is_lvds)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
int ret;
if (sor->power_is_up)
return 0;
/* Set link bw */
tegra_dc_sor_set_link_bandwidth(sor, is_lvds ?
tegra_dc_sor_set_link_bandwidth(dev, is_lvds ?
CLK_CNTRL_DP_LINK_SPEED_LVDS :
CLK_CNTRL_DP_LINK_SPEED_G1_62);
@ -655,9 +680,10 @@ static void tegra_dc_sor_enable_dc(struct dc_ctlr *disp_ctrl)
writel(reg_val, &disp_ctrl->cmd.state_access);
}
int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor,
int tegra_dc_sor_enable_dp(struct udevice *dev,
const struct tegra_dp_link_config *link_cfg)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
int ret;
tegra_sor_write_field(sor, CLK_CNTRL,
@ -701,7 +727,7 @@ int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor,
PLL2_AUX2_OVERRIDE_POWERDOWN |
PLL2_AUX7_PORT_POWERDOWN_DISABLE);
ret = tegra_dc_sor_power_up(sor, 0);
ret = tegra_dc_sor_power_up(dev, 0);
if (ret) {
debug("DP failed to power up\n");
return ret;
@ -711,18 +737,19 @@ int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor,
clock_sor_enable_edp_clock();
/* Power up lanes */
tegra_dc_sor_power_dplanes(sor, link_cfg->lane_count, 1);
tegra_dc_sor_power_dplanes(dev, link_cfg->lane_count, 1);
tegra_dc_sor_set_dp_mode(sor, link_cfg);
tegra_dc_sor_set_dp_mode(dev, link_cfg);
debug("%s ret\n", __func__);
return 0;
}
int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor,
int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *dev,
const struct tegra_dp_link_config *link_cfg,
const struct display_timing *timing)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
struct dc_ctlr *disp_ctrl;
u32 reg_val;
@ -730,9 +757,7 @@ int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor,
/* Use the first display controller */
debug("%s\n", __func__);
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC);
if (node < 0)
return -ENOENT;
node = dc_dev->of_offset;
disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
tegra_dc_sor_enable_dc(disp_ctrl);
@ -798,9 +823,11 @@ int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor,
return 0;
}
void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
void tegra_dc_sor_set_lane_parm(struct udevice *dev,
const struct tegra_dp_link_config *link_cfg)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),
link_cfg->drive_current);
tegra_sor_writel(sor, PR(sor->portnum),
@ -809,8 +836,8 @@ void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
link_cfg->postcursor);
tegra_sor_writel(sor, LVDS, 0);
tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);
tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw);
tegra_dc_sor_set_lane_count(dev, link_cfg->lane_count);
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
DP_PADCTL_TX_PU_ENABLE |
@ -825,9 +852,10 @@ void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0);
}
int tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor,
int tegra_dc_sor_set_voltage_swing(struct udevice *dev,
const struct tegra_dp_link_config *link_cfg)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
u32 drive_current = 0;
u32 pre_emphasis = 0;
@ -851,9 +879,10 @@ int tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor,
return 0;
}
void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor,
void tegra_dc_sor_power_down_unused_lanes(struct udevice *dev,
const struct tegra_dp_link_config *link_cfg)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
u32 pad_ctrl = 0;
int err = 0;
@ -891,9 +920,10 @@ void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor,
}
}
int tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor,
int tegra_sor_precharge_lanes(struct udevice *dev,
const struct tegra_dp_link_config *cfg)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
u32 val = 0;
switch (cfg->lane_count) {
@ -931,8 +961,9 @@ static void tegra_dc_sor_enable_sor(struct dc_ctlr *disp_ctrl, bool enable)
writel(reg_val, &disp_ctrl->disp.disp_win_opt);
}
int tegra_dc_sor_detach(struct tegra_dc_sor_data *sor)
int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *dev)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
int dc_reg_ctx[DC_REG_SAVE_SPACE];
const void *blob = gd->fdt_blob;
struct dc_ctlr *disp_ctrl;
@ -942,11 +973,7 @@ int tegra_dc_sor_detach(struct tegra_dc_sor_data *sor)
debug("%s\n", __func__);
/* Use the first display controller */
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC);
if (node < 0) {
ret = -ENOENT;
goto err;
}
node = dc_dev->of_offset;
disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
/* Sleep mode */
@ -997,28 +1024,61 @@ err:
return ret;
}
int tegra_dc_sor_init(struct tegra_dc_sor_data **sorp)
static int tegra_sor_set_backlight(struct udevice *dev, int percent)
{
const void *blob = gd->fdt_blob;
struct tegra_dc_sor_data *sor;
int node;
struct tegra_dc_sor_data *priv = dev_get_priv(dev);
int ret;
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_SOR);
if (node < 0)
return -ENOENT;
sor = calloc(1, sizeof(*sor));
if (!sor)
return -ENOMEM;
sor->base = (void *)fdtdec_get_addr(blob, node, "reg");
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC);
if (node < 0)
return -ENOENT;
sor->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg");
sor->power_is_up = 0;
sor->portnum = 0;
*sorp = sor;
ret = panel_enable_backlight(priv->panel);
if (ret) {
debug("sor: Cannot enable panel backlight\n");
return ret;
}
return 0;
}
static int tegra_sor_ofdata_to_platdata(struct udevice *dev)
{
struct tegra_dc_sor_data *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
int node;
int ret;
priv->base = (void *)fdtdec_get_addr(blob, dev->of_offset, "reg");
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC);
if (node < 0) {
debug("%s: Cannot find PMC\n", __func__);
return -ENOENT;
}
priv->pmc_base = (void *)fdtdec_get_addr(blob, node, "reg");
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "nvidia,panel",
&priv->panel);
if (ret) {
debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
dev->name, ret);
return ret;
}
return 0;
}
static const struct video_bridge_ops tegra_sor_ops = {
.set_backlight = tegra_sor_set_backlight,
};
static const struct udevice_id tegra_sor_ids[] = {
{ .compatible = "nvidia,tegra124-sor" },
{ }
};
U_BOOT_DRIVER(sor_tegra) = {
.name = "sor_tegra",
.id = UCLASS_VIDEO_BRIDGE,
.of_match = tegra_sor_ids,
.ofdata_to_platdata = tegra_sor_ofdata_to_platdata,
.ops = &tegra_sor_ops,
.priv_auto_alloc_size = sizeof(struct tegra_dc_sor_data),
};

45
drivers/video/tegra124/sor.h
View File

@ -873,44 +873,37 @@ struct tegra_dp_link_config {
u8 tps3_supported;
};
struct tegra_dc_sor_data {
void *base;
void *pmc_base;
u8 portnum; /* 0 or 1 */
int power_is_up;
};
#define TEGRA_SOR_TIMEOUT_MS 1000
#define TEGRA_SOR_ATTACH_TIMEOUT_MS 1000
int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor,
int tegra_dc_sor_enable_dp(struct udevice *sor,
const struct tegra_dp_link_config *link_cfg);
int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd);
void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena,
int tegra_dc_sor_set_power_state(struct udevice *sor, int pu_pd);
void tegra_dc_sor_set_dp_linkctl(struct udevice *dev, int ena,
u8 training_pattern, const struct tegra_dp_link_config *link_cfg);
void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw);
void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count);
void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor,
void tegra_dc_sor_set_link_bandwidth(struct udevice *dev, u8 link_bw);
void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count);
void tegra_dc_sor_set_panel_power(struct udevice *sor,
int power_up);
void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int);
void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw,
void tegra_dc_sor_set_internal_panel(struct udevice *dev, int is_int);
void tegra_dc_sor_read_link_config(struct udevice *dev, u8 *link_bw,
u8 *lane_count);
void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
void tegra_dc_sor_set_lane_parm(struct udevice *dev,
const struct tegra_dp_link_config *link_cfg);
void tegra_dc_sor_power_down_unused_lanes(struct udevice *sor,
const struct tegra_dp_link_config *link_cfg);
void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor,
const struct tegra_dp_link_config *link_cfg);
int tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor,
int tegra_dc_sor_set_voltage_swing(struct udevice *sor,
const struct tegra_dp_link_config *link_cfg);
int tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor,
int tegra_sor_precharge_lanes(struct udevice *dev,
const struct tegra_dp_link_config *cfg);
void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor);
void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask,
u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported);
void tegra_dp_disable_tx_pu(struct udevice *sor);
void tegra_dp_set_pe_vs_pc(struct udevice *dev, u32 mask, u32 pe_reg,
u32 vs_reg, u32 pc_reg, u8 pc_supported);
int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor,
int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *sor,
const struct tegra_dp_link_config *link_cfg,
const struct display_timing *timing);
int tegra_dc_sor_detach(struct tegra_dc_sor_data *sor);
int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *sor);
void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl,
int *dc_reg_ctx);
@ -918,5 +911,5 @@ int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl);
void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl,
int *dc_reg_ctx);
int tegra_dc_sor_init(struct tegra_dc_sor_data **sorp);
int tegra_dc_sor_init(struct udevice **sorp);
#endif

95
drivers/video/tegra124/tegra124-lcd.c
View File

@ -1,95 +0,0 @@
/*
* Copyright 2014 Google Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
*/
#include <common.h>
#include <errno.h>
#include <fdtdec.h>
#include <lcd.h>
#include <asm/gpio.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/dc.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
enum {
/* Maximum LCD size we support */
LCD_MAX_WIDTH = 1920,
LCD_MAX_HEIGHT = 1200,
LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */
};
vidinfo_t panel_info = {
/* Insert a value here so that we don't end up in the BSS */
.vl_col = -1,
};
int tegra_lcd_check_next_stage(const void *blob, int wait)
{
return 0;
}
void tegra_lcd_early_init(const void *blob)
{
/*
* Go with the maximum size for now. We will fix this up after
* relocation. These values are only used for memory alocation.
*/
panel_info.vl_col = LCD_MAX_WIDTH;
panel_info.vl_row = LCD_MAX_HEIGHT;
panel_info.vl_bpix = LCD_MAX_LOG2_BPP;
}
static int tegra124_lcd_init(void *lcdbase)
{
struct display_timing timing;
int ret;
clock_set_up_plldp();
clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
clock_enable(PERIPH_ID_HOST1X);
clock_enable(PERIPH_ID_DISP1);
clock_enable(PERIPH_ID_PWM);
clock_enable(PERIPH_ID_DPAUX);
clock_enable(PERIPH_ID_SOR0);
udelay(2);
reset_set_enable(PERIPH_ID_HOST1X, 0);
reset_set_enable(PERIPH_ID_DISP1, 0);
reset_set_enable(PERIPH_ID_PWM, 0);
reset_set_enable(PERIPH_ID_DPAUX, 0);
reset_set_enable(PERIPH_ID_SOR0, 0);
ret = display_init(lcdbase, 1 << LCD_BPP, &timing);
if (ret)
return ret;
panel_info.vl_col = roundup(timing.hactive.typ, 16);
panel_info.vl_row = timing.vactive.typ;
lcd_set_flush_dcache(1);
return 0;
}
void lcd_ctrl_init(void *lcdbase)
{
ulong start;
int ret;
start = get_timer(0);
ret = tegra124_lcd_init(lcdbase);
debug("LCD init took %lu ms\n", get_timer(start));
if (ret)
printf("%s: Error %d\n", __func__, ret);
}
void lcd_enable(void)
{
}

1
drivers/video/vidconsole-uclass.c
View File

@ -170,6 +170,7 @@ static void vidconsole_puts(struct stdio_dev *sdev, const char *s)
while (*s)
vidconsole_put_char(dev, *s++);
video_sync(dev->parent);
}
/* Set up the number of rows and colours (rotated drivers override this) */

1
include/configs/apalis_t30.h
View File

@ -43,7 +43,6 @@
/* USB host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB

1
include/configs/beaver.h
View File

@ -51,7 +51,6 @@
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB

5
include/configs/colibri_t20.h
View File

@ -38,7 +38,6 @@
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_ULPI
#define CONFIG_USB_ULPI_VIEWPORT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
@ -53,10 +52,6 @@
#define CONFIG_TFTP_TSIZE
/* LCD support */
#define CONFIG_LCD
#define CONFIG_PWM_TEGRA
#define CONFIG_VIDEO_TEGRA
#define LCD_BPP LCD_COLOR16
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_CONSOLE_SCROLL_LINES 10
#define CONFIG_CMD_BMP

1
include/configs/colibri_t30.h
View File

@ -43,7 +43,6 @@
/* USB host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB

1
include/configs/dalmore.h
View File

@ -58,6 +58,7 @@
/* General networking support */
#define CONFIG_CMD_DHCP
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */

1
include/configs/e2220-1170.h
View File

@ -44,7 +44,6 @@
/* USB2.0 Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB

5
include/configs/harmony.h
View File

@ -42,7 +42,6 @@
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */
/* USB Host support */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_ULPI
@ -60,10 +59,6 @@
#define CONFIG_CMD_DHCP
/* LCD support */
#define CONFIG_LCD
#define CONFIG_PWM_TEGRA
#define CONFIG_VIDEO_TEGRA
#define LCD_BPP LCD_COLOR16
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_CONSOLE_SCROLL_LINES 10

1
include/configs/jetson-tk1.h
View File

@ -48,7 +48,6 @@
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB

4
include/configs/medcom-wide.h
View File

@ -48,10 +48,6 @@
#define CONFIG_CMD_DHCP
/* LCD support */
#define CONFIG_LCD
#define CONFIG_PWM_TEGRA
#define CONFIG_VIDEO_TEGRA
#define LCD_BPP LCD_COLOR16
#define CONFIG_SYS_WHITE_ON_BLACK
/* support the new (FDT-based) image format */

4
include/configs/nyan-big.h
View File

@ -38,10 +38,7 @@
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/* LCD support */
#define CONFIG_LCD
#define CONFIG_PWM_TEGRA
#define CONFIG_AS3722_POWER
#define LCD_BPP LCD_COLOR16
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_CMD_BMP
@ -58,7 +55,6 @@
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB

1
include/configs/p2371-0000.h
View File

@ -44,7 +44,6 @@
/* USB2.0 Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB

1
include/configs/p2371-2180.h
View File

@ -44,7 +44,6 @@
/* USB2.0 Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB

1
include/configs/p2571.h
View File

@ -45,7 +45,6 @@
/* USB2.0 Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB

4
include/configs/paz00.h
View File

@ -48,10 +48,6 @@
#define CONFIG_CMD_DHCP
/* LCD support */
#define CONFIG_LCD
#define CONFIG_PWM_TEGRA
#define CONFIG_VIDEO_TEGRA
#define LCD_BPP LCD_COLOR16
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_CONSOLE_SCROLL_LINES 10

5
include/configs/seaboard.h
View File

@ -45,7 +45,6 @@
#define CONFIG_SYS_MMC_ENV_PART 2
/* USB Host support */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_STORAGE
@ -66,10 +65,6 @@
#define CONFIG_USB_KEYBOARD
/* LCD support */
#define CONFIG_LCD
#define CONFIG_PWM_TEGRA
#define CONFIG_VIDEO_TEGRA
#define LCD_BPP LCD_COLOR16
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_CONSOLE_SCROLL_LINES 10

4
include/configs/tec.h
View File

@ -48,10 +48,6 @@
#define CONFIG_CMD_DHCP
/* LCD support */
#define CONFIG_LCD
#define CONFIG_PWM_TEGRA
#define CONFIG_VIDEO_TEGRA
#define LCD_BPP LCD_COLOR16
#define CONFIG_SYS_WHITE_ON_BLACK
/* support the new (FDT-based) image format */

10
include/configs/tegra-common-post.h
View File

@ -53,6 +53,12 @@
#define STDOUT_LCD ""
#endif
#ifdef CONFIG_DM_VIDEO
#define STDOUT_VIDEO ",vidconsole"
#else
#define STDOUT_VIDEO ""
#endif
#ifdef CONFIG_CROS_EC_KEYB
#define STDOUT_CROS_EC ",cros-ec-keyb"
#else
@ -61,8 +67,8 @@
#define TEGRA_DEVICE_SETTINGS \
"stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB STDOUT_CROS_EC "\0" \
"stdout=serial" STDOUT_LCD "\0" \
"stderr=serial" STDOUT_LCD "\0" \
"stdout=serial" STDOUT_LCD STDOUT_VIDEO "\0" \
"stderr=serial" STDOUT_LCD STDOUT_VIDEO "\0" \
""
#ifndef BOARD_EXTRA_ENV_SETTINGS

1
include/configs/trimslice.h
View File

@ -44,7 +44,6 @@
#define CONFIG_ENV_OFFSET (512 * 1024)
/* USB Host support */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_STORAGE

1
include/configs/venice2.h
View File

@ -45,7 +45,6 @@
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB

4
include/configs/ventana.h
View File

@ -49,10 +49,6 @@
#define CONFIG_USB_KEYBOARD
/* LCD support */
#define CONFIG_LCD
#define CONFIG_PWM_TEGRA
#define CONFIG_VIDEO_TEGRA
#define LCD_BPP LCD_COLOR16
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_CONSOLE_SCROLL_LINES 10

345
include/dt-bindings/clock/tegra124-car-common.h Normal file
View File

@ -0,0 +1,345 @@
/*
* This header provides constants for binding nvidia,tegra124-car or
* nvidia,tegra132-car.
*
* The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 185 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 185 and
* above.
*/
#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
/* 0 */
/* 1 */
/* 2 */
#define TEGRA124_CLK_ISPB 3
#define TEGRA124_CLK_RTC 4
#define TEGRA124_CLK_TIMER 5
#define TEGRA124_CLK_UARTA 6
/* 7 (register bit affects uartb and vfir) */
/* 8 */
#define TEGRA124_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA124_CLK_I2S1 11
#define TEGRA124_CLK_I2C1 12
/* 13 */
#define TEGRA124_CLK_SDMMC1 14
#define TEGRA124_CLK_SDMMC4 15
/* 16 */
#define TEGRA124_CLK_PWM 17
#define TEGRA124_CLK_I2S2 18
/* 20 (register bit affects vi and vi_sensor) */
/* 21 */
#define TEGRA124_CLK_USBD 22
#define TEGRA124_CLK_ISP 23
/* 26 */
/* 25 */
#define TEGRA124_CLK_DISP2 26
#define TEGRA124_CLK_DISP1 27
#define TEGRA124_CLK_HOST1X 28
#define TEGRA124_CLK_VCP 29
#define TEGRA124_CLK_I2S0 30
/* 31 */
#define TEGRA124_CLK_MC 32
/* 33 */
#define TEGRA124_CLK_APBDMA 34
/* 35 */
#define TEGRA124_CLK_KBC 36
/* 37 */
/* 38 */
/* 39 (register bit affects fuse and fuse_burn) */
#define TEGRA124_CLK_KFUSE 40
#define TEGRA124_CLK_SBC1 41
#define TEGRA124_CLK_NOR 42
/* 43 */
#define TEGRA124_CLK_SBC2 44
/* 45 */
#define TEGRA124_CLK_SBC3 46
#define TEGRA124_CLK_I2C5 47
#define TEGRA124_CLK_DSIA 48
/* 49 */
#define TEGRA124_CLK_MIPI 50
#define TEGRA124_CLK_HDMI 51
#define TEGRA124_CLK_CSI 52
/* 53 */
#define TEGRA124_CLK_I2C2 54
#define TEGRA124_CLK_UARTC 55
#define TEGRA124_CLK_MIPI_CAL 56
#define TEGRA124_CLK_EMC 57
#define TEGRA124_CLK_USB2 58
#define TEGRA124_CLK_USB3 59
/* 60 */
#define TEGRA124_CLK_VDE 61
#define TEGRA124_CLK_BSEA 62
#define TEGRA124_CLK_BSEV 63
/* 64 */
#define TEGRA124_CLK_UARTD 65
/* 66 */
#define TEGRA124_CLK_I2C3 67
#define TEGRA124_CLK_SBC4 68
#define TEGRA124_CLK_SDMMC3 69
#define TEGRA124_CLK_PCIE 70
#define TEGRA124_CLK_OWR 71
#define TEGRA124_CLK_AFI 72
#define TEGRA124_CLK_CSITE 73
/* 74 */
/* 75 */
#define TEGRA124_CLK_LA 76
#define TEGRA124_CLK_TRACE 77
#define TEGRA124_CLK_SOC_THERM 78
#define TEGRA124_CLK_DTV 79
/* 80 */
#define TEGRA124_CLK_I2CSLOW 81
#define TEGRA124_CLK_DSIB 82
#define TEGRA124_CLK_TSEC 83
/* 84 */
/* 85 */
/* 86 */
/* 87 */
/* 88 */
#define TEGRA124_CLK_XUSB_HOST 89
/* 90 */
#define TEGRA124_CLK_MSENC 91
#define TEGRA124_CLK_CSUS 92
/* 93 */
/* 94 */
/* 95 (bit affects xusb_dev and xusb_dev_src) */
/* 96 */
/* 97 */
/* 98 */
#define TEGRA124_CLK_MSELECT 99
#define TEGRA124_CLK_TSENSOR 100
#define TEGRA124_CLK_I2S3 101
#define TEGRA124_CLK_I2S4 102
#define TEGRA124_CLK_I2C4 103
#define TEGRA124_CLK_SBC5 104
#define TEGRA124_CLK_SBC6 105
#define TEGRA124_CLK_D_AUDIO 106
#define TEGRA124_CLK_APBIF 107
#define TEGRA124_CLK_DAM0 108
#define TEGRA124_CLK_DAM1 109
#define TEGRA124_CLK_DAM2 110
#define TEGRA124_CLK_HDA2CODEC_2X 111
/* 112 */
#define TEGRA124_CLK_AUDIO0_2X 113
#define TEGRA124_CLK_AUDIO1_2X 114
#define TEGRA124_CLK_AUDIO2_2X 115
#define TEGRA124_CLK_AUDIO3_2X 116
#define TEGRA124_CLK_AUDIO4_2X 117
#define TEGRA124_CLK_SPDIF_2X 118
#define TEGRA124_CLK_ACTMON 119
#define TEGRA124_CLK_EXTERN1 120
#define TEGRA124_CLK_EXTERN2 121
#define TEGRA124_CLK_EXTERN3 122
#define TEGRA124_CLK_SATA_OOB 123
#define TEGRA124_CLK_SATA 124
#define TEGRA124_CLK_HDA 125
/* 126 */
#define TEGRA124_CLK_SE 127
#define TEGRA124_CLK_HDA2HDMI 128
#define TEGRA124_CLK_SATA_COLD 129
/* 130 */
/* 131 */
/* 132 */
/* 133 */
/* 134 */
/* 135 */
/* 136 */
/* 137 */
/* 138 */
/* 139 */
/* 140 */
/* 141 */
/* 142 */
/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
/* xusb_host_src and xusb_ss_src) */
#define TEGRA124_CLK_CILAB 144
#define TEGRA124_CLK_CILCD 145
#define TEGRA124_CLK_CILE 146
#define TEGRA124_CLK_DSIALP 147
#define TEGRA124_CLK_DSIBLP 148
#define TEGRA124_CLK_ENTROPY 149
#define TEGRA124_CLK_DDS 150
/* 151 */
#define TEGRA124_CLK_DP2 152
#define TEGRA124_CLK_AMX 153
#define TEGRA124_CLK_ADX 154
/* 155 (bit affects dfll_ref and dfll_soc) */
#define TEGRA124_CLK_XUSB_SS 156
/* 157 */
/* 158 */
/* 159 */
/* 160 */
/* 161 */
/* 162 */
/* 163 */
/* 164 */
/* 165 */
#define TEGRA124_CLK_I2C6 166
/* 167 */
/* 168 */
/* 169 */
/* 170 */
#define TEGRA124_CLK_VIM2_CLK 171
/* 172 */
/* 173 */
/* 174 */
/* 175 */
#define TEGRA124_CLK_HDMI_AUDIO 176
#define TEGRA124_CLK_CLK72MHZ 177
#define TEGRA124_CLK_VIC03 178
/* 179 */
#define TEGRA124_CLK_ADX1 180
#define TEGRA124_CLK_DPAUX 181
#define TEGRA124_CLK_SOR0 182
/* 183 */
#define TEGRA124_CLK_GPU 184
#define TEGRA124_CLK_AMX1 185
/* 186 */
/* 187 */
/* 188 */
/* 189 */
/* 190 */
/* 191 */
#define TEGRA124_CLK_UARTB 192
#define TEGRA124_CLK_VFIR 193
#define TEGRA124_CLK_SPDIF_IN 194
#define TEGRA124_CLK_SPDIF_OUT 195
#define TEGRA124_CLK_VI 196
#define TEGRA124_CLK_VI_SENSOR 197
#define TEGRA124_CLK_FUSE 198
#define TEGRA124_CLK_FUSE_BURN 199
#define TEGRA124_CLK_CLK_32K 200
#define TEGRA124_CLK_CLK_M 201
#define TEGRA124_CLK_CLK_M_DIV2 202
#define TEGRA124_CLK_CLK_M_DIV4 203
#define TEGRA124_CLK_PLL_REF 204
#define TEGRA124_CLK_PLL_C 205
#define TEGRA124_CLK_PLL_C_OUT1 206
#define TEGRA124_CLK_PLL_C2 207
#define TEGRA124_CLK_PLL_C3 208
#define TEGRA124_CLK_PLL_M 209
#define TEGRA124_CLK_PLL_M_OUT1 210
#define TEGRA124_CLK_PLL_P 211
#define TEGRA124_CLK_PLL_P_OUT1 212
#define TEGRA124_CLK_PLL_P_OUT2 213
#define TEGRA124_CLK_PLL_P_OUT3 214
#define TEGRA124_CLK_PLL_P_OUT4 215
#define TEGRA124_CLK_PLL_A 216
#define TEGRA124_CLK_PLL_A_OUT0 217
#define TEGRA124_CLK_PLL_D 218
#define TEGRA124_CLK_PLL_D_OUT0 219
#define TEGRA124_CLK_PLL_D2 220
#define TEGRA124_CLK_PLL_D2_OUT0 221
#define TEGRA124_CLK_PLL_U 222
#define TEGRA124_CLK_PLL_U_480M 223
#define TEGRA124_CLK_PLL_U_60M 224
#define TEGRA124_CLK_PLL_U_48M 225
#define TEGRA124_CLK_PLL_U_12M 226
/* 227 */
/* 228 */
#define TEGRA124_CLK_PLL_RE_VCO 229
#define TEGRA124_CLK_PLL_RE_OUT 230
#define TEGRA124_CLK_PLL_E 231
#define TEGRA124_CLK_SPDIF_IN_SYNC 232
#define TEGRA124_CLK_I2S0_SYNC 233
#define TEGRA124_CLK_I2S1_SYNC 234
#define TEGRA124_CLK_I2S2_SYNC 235
#define TEGRA124_CLK_I2S3_SYNC 236
#define TEGRA124_CLK_I2S4_SYNC 237
#define TEGRA124_CLK_VIMCLK_SYNC 238
#define TEGRA124_CLK_AUDIO0 239
#define TEGRA124_CLK_AUDIO1 240
#define TEGRA124_CLK_AUDIO2 241
#define TEGRA124_CLK_AUDIO3 242
#define TEGRA124_CLK_AUDIO4 243
#define TEGRA124_CLK_SPDIF 244
#define TEGRA124_CLK_CLK_OUT_1 245
#define TEGRA124_CLK_CLK_OUT_2 246
#define TEGRA124_CLK_CLK_OUT_3 247
#define TEGRA124_CLK_BLINK 248
/* 249 */
/* 250 */
/* 251 */
#define TEGRA124_CLK_XUSB_HOST_SRC 252
#define TEGRA124_CLK_XUSB_FALCON_SRC 253
#define TEGRA124_CLK_XUSB_FS_SRC 254
#define TEGRA124_CLK_XUSB_SS_SRC 255
#define TEGRA124_CLK_XUSB_DEV_SRC 256
#define TEGRA124_CLK_XUSB_DEV 257
#define TEGRA124_CLK_XUSB_HS_SRC 258
#define TEGRA124_CLK_SCLK 259
#define TEGRA124_CLK_HCLK 260
#define TEGRA124_CLK_PCLK 261
/* 262 */
/* 263 */
#define TEGRA124_CLK_DFLL_REF 264
#define TEGRA124_CLK_DFLL_SOC 265
#define TEGRA124_CLK_VI_SENSOR2 266
#define TEGRA124_CLK_PLL_P_OUT5 267
#define TEGRA124_CLK_CML0 268
#define TEGRA124_CLK_CML1 269
#define TEGRA124_CLK_PLL_C4 270
#define TEGRA124_CLK_PLL_DP 271
#define TEGRA124_CLK_PLL_E_MUX 272
#define TEGRA124_CLK_PLL_D_DSI_OUT 273
/* 274 */
/* 275 */
/* 276 */
/* 277 */
/* 278 */
/* 279 */
/* 280 */
/* 281 */
/* 282 */
/* 283 */
/* 284 */
/* 285 */
/* 286 */
/* 287 */
/* 288 */
/* 289 */
/* 290 */
/* 291 */
/* 292 */
/* 293 */
/* 294 */
/* 295 */
/* 296 */
/* 297 */
/* 298 */
/* 299 */
#define TEGRA124_CLK_AUDIO0_MUX 300
#define TEGRA124_CLK_AUDIO1_MUX 301
#define TEGRA124_CLK_AUDIO2_MUX 302
#define TEGRA124_CLK_AUDIO3_MUX 303
#define TEGRA124_CLK_AUDIO4_MUX 304
#define TEGRA124_CLK_SPDIF_MUX 305
#define TEGRA124_CLK_CLK_OUT_1_MUX 306
#define TEGRA124_CLK_CLK_OUT_2_MUX 307
#define TEGRA124_CLK_CLK_OUT_3_MUX 308
/* 309 */
/* 310 */
#define TEGRA124_CLK_SOR0_LVDS 311
#define TEGRA124_CLK_XUSB_SS_DIV2 312
#define TEGRA124_CLK_PLL_M_UD 313
#define TEGRA124_CLK_PLL_C_UD 314
#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */

341
include/dt-bindings/clock/tegra124-car.h
View File

@ -1,342 +1,19 @@
/*
* This header provides constants for binding nvidia,tegra124-car.
*
* The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
* registers. These IDs often match those in the CAR's RST_DEVICES registers,
* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
* this case, those clocks are assigned IDs above 185 in order to highlight
* this issue. Implementations that interpret these clock IDs as bit values
* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
* explicitly handle these special cases.
*
* The balance of the clocks controlled by the CAR are assigned IDs of 185 and
* above.
* This header provides Tegra124-specific constants for binding
* nvidia,tegra124-car.
*/
#include <dt-bindings/clock/tegra124-car-common.h>
#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
/* 0 */
/* 1 */
/* 2 */
#define TEGRA124_CLK_ISPB 3
#define TEGRA124_CLK_RTC 4
#define TEGRA124_CLK_TIMER 5
#define TEGRA124_CLK_UARTA 6
/* 7 (register bit affects uartb and vfir) */
/* 8 */
#define TEGRA124_CLK_SDMMC2 9
/* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA124_CLK_I2S1 11
#define TEGRA124_CLK_I2C1 12
#define TEGRA124_CLK_NDFLASH 13
#define TEGRA124_CLK_SDMMC1 14
#define TEGRA124_CLK_SDMMC4 15
/* 16 */
#define TEGRA124_CLK_PWM 17
#define TEGRA124_CLK_I2S2 18
/* 20 (register bit affects vi and vi_sensor) */
/* 21 */
#define TEGRA124_CLK_USBD 22
#define TEGRA124_CLK_ISP 23
/* 26 */
/* 25 */
#define TEGRA124_CLK_DISP2 26
#define TEGRA124_CLK_DISP1 27
#define TEGRA124_CLK_HOST1X 28
#define TEGRA124_CLK_VCP 29
#define TEGRA124_CLK_I2S0 30
/* 31 */
#define TEGRA124_CLK_PLL_X 227
#define TEGRA124_CLK_PLL_X_OUT0 228
/* 32 */
/* 33 */
#define TEGRA124_CLK_APBDMA 34
/* 35 */
#define TEGRA124_CLK_KBC 36
/* 37 */
/* 38 */
/* 39 (register bit affects fuse and fuse_burn) */
#define TEGRA124_CLK_KFUSE 40
#define TEGRA124_CLK_SBC1 41
#define TEGRA124_CLK_NOR 42
/* 43 */
#define TEGRA124_CLK_SBC2 44
/* 45 */
#define TEGRA124_CLK_SBC3 46
#define TEGRA124_CLK_I2C5 47
#define TEGRA124_CLK_DSIA 48
/* 49 */
#define TEGRA124_CLK_MIPI 50
#define TEGRA124_CLK_HDMI 51
#define TEGRA124_CLK_CSI 52
/* 53 */
#define TEGRA124_CLK_I2C2 54
#define TEGRA124_CLK_UARTC 55
#define TEGRA124_CLK_MIPI_CAL 56
#define TEGRA124_CLK_EMC 57
#define TEGRA124_CLK_USB2 58
#define TEGRA124_CLK_USB3 59
/* 60 */
#define TEGRA124_CLK_VDE 61
#define TEGRA124_CLK_BSEA 62
#define TEGRA124_CLK_BSEV 63
#define TEGRA124_CLK_CCLK_G 262
#define TEGRA124_CLK_CCLK_LP 263
/* 64 */
#define TEGRA124_CLK_UARTD 65
#define TEGRA124_CLK_UARTE 66
#define TEGRA124_CLK_I2C3 67
#define TEGRA124_CLK_SBC4 68
#define TEGRA124_CLK_SDMMC3 69
#define TEGRA124_CLK_PCIE 70
#define TEGRA124_CLK_OWR 71
#define TEGRA124_CLK_AFI 72
#define TEGRA124_CLK_CSITE 73
/* 74 */
/* 75 */
#define TEGRA124_CLK_LA 76
#define TEGRA124_CLK_TRACE 77
#define TEGRA124_CLK_SOC_THERM 78
#define TEGRA124_CLK_DTV 79
#define TEGRA124_CLK_NDSPEED 80
#define TEGRA124_CLK_I2CSLOW 81
#define TEGRA124_CLK_DSIB 82
#define TEGRA124_CLK_TSEC 83
/* 84 */
/* 85 */
/* 86 */
/* 87 */
/* 88 */
#define TEGRA124_CLK_XUSB_HOST 89
/* 90 */
#define TEGRA124_CLK_MSENC 91
#define TEGRA124_CLK_CSUS 92
/* 93 */
/* 94 */
/* 95 (bit affects xusb_dev and xusb_dev_src) */
/* 96 */
/* 97 */
/* 98 */
#define TEGRA124_CLK_MSELECT 99
#define TEGRA124_CLK_TSENSOR 100
#define TEGRA124_CLK_I2S3 101
#define TEGRA124_CLK_I2S4 102
#define TEGRA124_CLK_I2C4 103
#define TEGRA124_CLK_SBC5 104
#define TEGRA124_CLK_SBC6 105
#define TEGRA124_CLK_D_AUDIO 106
#define TEGRA124_CLK_APBIF 107
#define TEGRA124_CLK_DAM0 108
#define TEGRA124_CLK_DAM1 109
#define TEGRA124_CLK_DAM2 110
#define TEGRA124_CLK_HDA2CODEC_2X 111
/* 112 */
#define TEGRA124_CLK_AUDIO0_2X 113
#define TEGRA124_CLK_AUDIO1_2X 114
#define TEGRA124_CLK_AUDIO2_2X 115
#define TEGRA124_CLK_AUDIO3_2X 116
#define TEGRA124_CLK_AUDIO4_2X 117
#define TEGRA124_CLK_SPDIF_2X 118
#define TEGRA124_CLK_ACTMON 119
#define TEGRA124_CLK_EXTERN1 120
#define TEGRA124_CLK_EXTERN2 121
#define TEGRA124_CLK_EXTERN3 122
#define TEGRA124_CLK_SATA_OOB 123
#define TEGRA124_CLK_SATA 124
#define TEGRA124_CLK_HDA 125
/* 126 */
#define TEGRA124_CLK_SE 127
#define TEGRA124_CLK_HDA2HDMI 128
#define TEGRA124_CLK_SATA_COLD 129
/* 130 */
/* 131 */
/* 132 */
/* 133 */
/* 134 */
/* 135 */
/* 136 */
/* 137 */
/* 138 */
/* 139 */
/* 140 */
/* 141 */
/* 142 */
/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
/* xusb_host_src and xusb_ss_src) */
#define TEGRA124_CLK_CILAB 144
#define TEGRA124_CLK_CILCD 145
#define TEGRA124_CLK_CILE 146
#define TEGRA124_CLK_DSIALP 147
#define TEGRA124_CLK_DSIBLP 148
#define TEGRA124_CLK_ENTROPY 149
#define TEGRA124_CLK_DDS 150
/* 151 */
#define TEGRA124_CLK_DP2 152
#define TEGRA124_CLK_AMX 153
#define TEGRA124_CLK_ADX 154
/* 155 (bit affects dfll_ref and dfll_soc) */
#define TEGRA124_CLK_XUSB_SS 156
/* 157 */
/* 158 */
/* 159 */
/* 160 */
/* 161 */
/* 162 */
/* 163 */
/* 164 */
/* 165 */
#define TEGRA124_CLK_I2C6 166
/* 167 */
/* 168 */
/* 169 */
/* 170 */
#define TEGRA124_CLK_VIM2_CLK 171
/* 172 */
/* 173 */
/* 174 */
/* 175 */
#define TEGRA124_CLK_HDMI_AUDIO 176
#define TEGRA124_CLK_CLK72MHZ 177
#define TEGRA124_CLK_VIC03 178
/* 179 */
#define TEGRA124_CLK_ADX1 180
#define TEGRA124_CLK_DPAUX 181
#define TEGRA124_CLK_SOR0 182
/* 183 */
#define TEGRA124_CLK_GPU 184
#define TEGRA124_CLK_AMX1 185
#define TEGRA124_CLK_AFC0 186
#define TEGRA124_CLK_AFC1 187
#define TEGRA124_CLK_AFC2 188
#define TEGRA124_CLK_AFC3 189
#define TEGRA124_CLK_AFC4 190
#define TEGRA124_CLK_AFC5 191
#define TEGRA124_CLK_UARTB 192
#define TEGRA124_CLK_VFIR 193
#define TEGRA124_CLK_SPDIF_IN 194
#define TEGRA124_CLK_SPDIF_OUT 195
#define TEGRA124_CLK_VI 196
#define TEGRA124_CLK_VI_SENSOR 197
#define TEGRA124_CLK_FUSE 198
#define TEGRA124_CLK_FUSE_BURN 199
#define TEGRA124_CLK_CLK_32K 200
#define TEGRA124_CLK_CLK_M 201
#define TEGRA124_CLK_CLK_M_DIV2 202
#define TEGRA124_CLK_CLK_M_DIV4 203
#define TEGRA124_CLK_PLL_REF 204
#define TEGRA124_CLK_PLL_C 205
#define TEGRA124_CLK_PLL_C_OUT1 206
#define TEGRA124_CLK_PLL_C2 207
#define TEGRA124_CLK_PLL_C3 208
#define TEGRA124_CLK_PLL_M 209
#define TEGRA124_CLK_PLL_M_OUT1 210
#define TEGRA124_CLK_PLL_P 211
#define TEGRA124_CLK_PLL_P_OUT1 212
#define TEGRA124_CLK_PLL_P_OUT2 213
#define TEGRA124_CLK_PLL_P_OUT3 214
#define TEGRA124_CLK_PLL_P_OUT4 215
#define TEGRA124_CLK_PLL_A 216
#define TEGRA124_CLK_PLL_A_OUT0 217
#define TEGRA124_CLK_PLL_D 218
#define TEGRA124_CLK_PLL_D_OUT0 219
#define TEGRA124_CLK_PLL_D2 220
#define TEGRA124_CLK_PLL_D2_OUT0 221
#define TEGRA124_CLK_PLL_U 222
#define TEGRA124_CLK_PLL_U_480M 223
#define TEGRA124_CLK_PLL_U_60M 224
#define TEGRA124_CLK_PLL_U_48M 225
#define TEGRA124_CLK_PLL_U_12M 226
#define TEGRA124_CLK_PLL_X 227
#define TEGRA124_CLK_PLL_X_OUT0 228
#define TEGRA124_CLK_PLL_RE_VCO 229
#define TEGRA124_CLK_PLL_RE_OUT 230
#define TEGRA124_CLK_PLL_E 231
#define TEGRA124_CLK_SPDIF_IN_SYNC 232
#define TEGRA124_CLK_I2S0_SYNC 233
#define TEGRA124_CLK_I2S1_SYNC 234
#define TEGRA124_CLK_I2S2_SYNC 235
#define TEGRA124_CLK_I2S3_SYNC 236
#define TEGRA124_CLK_I2S4_SYNC 237
#define TEGRA124_CLK_VIMCLK_SYNC 238
#define TEGRA124_CLK_AUDIO0 239
#define TEGRA124_CLK_AUDIO1 240
#define TEGRA124_CLK_AUDIO2 241
#define TEGRA124_CLK_AUDIO3 242
#define TEGRA124_CLK_AUDIO4 243
#define TEGRA124_CLK_SPDIF 244
#define TEGRA124_CLK_CLK_OUT_1 245
#define TEGRA124_CLK_CLK_OUT_2 246
#define TEGRA124_CLK_CLK_OUT_3 247
#define TEGRA124_CLK_BLINK 248
/* 249 */
/* 250 */
/* 251 */
#define TEGRA124_CLK_XUSB_HOST_SRC 252
#define TEGRA124_CLK_XUSB_FALCON_SRC 253
#define TEGRA124_CLK_XUSB_FS_SRC 254
#define TEGRA124_CLK_XUSB_SS_SRC 255
#define TEGRA124_CLK_XUSB_DEV_SRC 256
#define TEGRA124_CLK_XUSB_DEV 257
#define TEGRA124_CLK_XUSB_HS_SRC 258
#define TEGRA124_CLK_SCLK 259
#define TEGRA124_CLK_HCLK 260
#define TEGRA124_CLK_PCLK 261
#define TEGRA124_CLK_CCLK_G 262
#define TEGRA124_CLK_CCLK_LP 263
#define TEGRA124_CLK_DFLL_REF 264
#define TEGRA124_CLK_DFLL_SOC 265
#define TEGRA124_CLK_VI_SENSOR2 266
#define TEGRA124_CLK_PLL_P_OUT5 267
#define TEGRA124_CLK_CML0 268
#define TEGRA124_CLK_CML1 269
#define TEGRA124_CLK_PLL_C4 270
#define TEGRA124_CLK_PLL_DP 271
#define TEGRA124_CLK_PLL_E_MUX 272
/* 273 */
/* 274 */
/* 275 */
/* 276 */
/* 277 */
/* 278 */
/* 279 */
/* 280 */
/* 281 */
/* 282 */
/* 283 */
/* 284 */
/* 285 */
/* 286 */
/* 287 */
/* 288 */
/* 289 */
/* 290 */
/* 291 */
/* 292 */
/* 293 */
/* 294 */
/* 295 */
/* 296 */
/* 297 */
/* 298 */
/* 299 */
#define TEGRA124_CLK_AUDIO0_MUX 300
#define TEGRA124_CLK_AUDIO1_MUX 301
#define TEGRA124_CLK_AUDIO2_MUX 302
#define TEGRA124_CLK_AUDIO3_MUX 303
#define TEGRA124_CLK_AUDIO4_MUX 304
#define TEGRA124_CLK_SPDIF_MUX 305
#define TEGRA124_CLK_CLK_OUT_1_MUX 306
#define TEGRA124_CLK_CLK_OUT_2_MUX 307
#define TEGRA124_CLK_CLK_OUT_3_MUX 308
#define TEGRA124_CLK_DSIA_MUX 309
#define TEGRA124_CLK_DSIB_MUX 310
#define TEGRA124_CLK_SOR0_LVDS 311
#define TEGRA124_CLK_PLL_M_UD 311
#define TEGRA124_CLK_CLK_MAX 312
#define TEGRA124_CLK_CLK_MAX 315
#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */

31
include/dt-bindings/memory/tegra124-mc.h Normal file
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@ -0,0 +1,31 @@
#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H
#define DT_BINDINGS_MEMORY_TEGRA124_MC_H
#define TEGRA_SWGROUP_PTC 0
#define TEGRA_SWGROUP_DC 1
#define TEGRA_SWGROUP_DCB 2
#define TEGRA_SWGROUP_AFI 3
#define TEGRA_SWGROUP_AVPC 4
#define TEGRA_SWGROUP_HDA 5
#define TEGRA_SWGROUP_HC 6
#define TEGRA_SWGROUP_MSENC 7
#define TEGRA_SWGROUP_PPCS 8
#define TEGRA_SWGROUP_SATA 9
#define TEGRA_SWGROUP_VDE 10
#define TEGRA_SWGROUP_MPCORELP 11
#define TEGRA_SWGROUP_MPCORE 12
#define TEGRA_SWGROUP_ISP2 13
#define TEGRA_SWGROUP_XUSB_HOST 14
#define TEGRA_SWGROUP_XUSB_DEV 15
#define TEGRA_SWGROUP_ISP2B 16
#define TEGRA_SWGROUP_TSEC 17
#define TEGRA_SWGROUP_A9AVP 18
#define TEGRA_SWGROUP_GPU 19
#define TEGRA_SWGROUP_SDMMC1A 20
#define TEGRA_SWGROUP_SDMMC2A 21
#define TEGRA_SWGROUP_SDMMC3A 22
#define TEGRA_SWGROUP_SDMMC4A 23
#define TEGRA_SWGROUP_VIC 24
#define TEGRA_SWGROUP_VI 25
#endif

12
include/dt-bindings/reset/tegra124-car.h Normal file
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@ -0,0 +1,12 @@
/*
* This header provides Tegra124-specific constants for binding
* nvidia,tegra124-car.
*/
#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H
#define _DT_BINDINGS_RESET_TEGRA124_CAR_H
#define TEGRA124_RESET(x) (6 * 32 + (x))
#define TEGRA124_RST_DFLL_DVCO TEGRA124_RESET(0)
#endif /* _DT_BINDINGS_RESET_TEGRA124_CAR_H */

13
include/dt-bindings/thermal/tegra124-soctherm.h Normal file
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@ -0,0 +1,13 @@
/*
* This header provides constants for binding nvidia,tegra124-soctherm.
*/
#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
#define TEGRA124_SOCTHERM_SENSOR_CPU 0
#define TEGRA124_SOCTHERM_SENSOR_MEM 1
#define TEGRA124_SOCTHERM_SENSOR_GPU 2
#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
#endif

1
include/fdtdec.h
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@ -120,7 +120,6 @@ enum fdt_compat_id {
COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */
COMPAT_NVIDIA_TEGRA124_DC, /* Tegra 124 Display controller */
COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */
COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */

1
lib/fdtdec.c
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@ -27,7 +27,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
COMPAT(NVIDIA_TEGRA124_DC, "nvidia,tegra124-dc"),
COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"),
COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),