leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

global: Move remaining CONFIG_SYS_NUM_* to CFG_SYS_NUM_*

Browse Source 
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini 2022-11-16 13:10:29 -05:00
parent 91092132ba
commit cdc5ed8f1f
43 changed files with 138 additions and 138 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
README
View File

@ -923,7 +923,7 @@ The following options need to be configured:
with a list of GPIO LEDs that have inverted polarity.
- I2C Support:
CONFIG_SYS_NUM_I2C_BUSES
CFG_SYS_NUM_I2C_BUSES
Hold the number of i2c buses you want to use.
CONFIG_SYS_I2C_DIRECT_BUS
@ -940,7 +940,7 @@ The following options need to be configured:
hold a list of buses you want to use, only used if
CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
CONFIG_SYS_NUM_I2C_BUSES = 9:
CFG_SYS_NUM_I2C_BUSES = 9:
CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \
{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \

12
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -209,9 +209,9 @@
/* SoC related */
#ifdef CONFIG_ARCH_LS1043A
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 7
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 7
#define CFG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
@ -255,9 +255,9 @@
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#elif defined(CONFIG_ARCH_LS1046A)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 8
#define CFG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE

2
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@ -160,7 +160,7 @@ struct sys_info {
unsigned long freq_localbus;
unsigned long freq_cga_m2;
#ifdef CONFIG_SYS_DPAA_FMAN
unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
unsigned long freq_fman[CFG_SYS_NUM_FMAN];
#endif
unsigned long freq_qman;
};

2
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@ -306,7 +306,7 @@ struct sys_info {
unsigned long freq_localbus;
unsigned long freq_qe;
#ifdef CONFIG_SYS_DPAA_FMAN
unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
unsigned long freq_fman[CFG_SYS_NUM_FMAN];
#endif
#ifdef CONFIG_SYS_DPAA_QBMAN
unsigned long freq_qman;

2
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@ -264,7 +264,7 @@ int checkcpu (void)
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
for (i = 0; i < CFG_SYS_NUM_FMAN; i++) {
printf(" FMAN%d: %s MHz\n", i + 1,
strmhz(buf1, sysinfo.freq_fman[i]));
}

6
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -162,7 +162,7 @@ void disable_cpc_sram(void)
cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) {
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
/* find and disable LAW of SRAM */
struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
@ -232,7 +232,7 @@ void enable_cpc(void)
have_hwconfig = true;
}
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) {
if (have_hwconfig) {
sprintf(cpc_subarg, "cpc%u", i + 1);
cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
@ -273,7 +273,7 @@ static void invalidate_cpc(void)
int i;
cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) {
/* skip CPC when it used as all SRAM */
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
continue;

4
arch/powerpc/cpu/mpc85xx/fdt.c
View File

@ -167,7 +167,7 @@ static inline void ft_fixup_l3cache(void *blob, int off)
cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR;
u32 cfg0 = in_be32(&cpc->cpccfg0);
size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
size = CPC_CFG0_SZ_K(cfg0) * 1024 * CFG_SYS_NUM_CPC;
num_ways = CPC_CFG0_NUM_WAYS(cfg0);
line_size = CPC_CFG0_LINE_SZ(cfg0);
num_sets = size / (line_size * num_ways);
@ -469,7 +469,7 @@ static void ft_fixup_dpaa_clks(void *blob)
ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM1_OFFSET,
sysinfo.freq_fman[0]);
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM2_OFFSET,
sysinfo.freq_fman[1]);
#endif

6
arch/powerpc/cpu/mpc85xx/liodn.c
View File

@ -104,7 +104,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev,
fm = (void *)CFG_SYS_FSL_FM1_ADDR;
break;
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
case FSL_HW_PORTAL_FMAN2:
fm = (void *)CFG_SYS_FSL_FM2_ADDR;
break;
@ -201,7 +201,7 @@ void set_liodns(void)
setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl,
fman1_liodn_tbl_sz);
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
set_fman_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz);
setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl,
fman2_liodn_tbl_sz);
@ -373,7 +373,7 @@ void fdt_fixup_liodn(void *blob)
fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz);
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_liodn_tbl_fman(blob, fman1_liodn_tbl, fman1_liodn_tbl_sz);
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
fdt_fixup_liodn_tbl_fman(blob, fman2_liodn_tbl, fman2_liodn_tbl_sz);
#endif
#endif

2
arch/powerpc/cpu/mpc85xx/p2041_ids.c
View File

@ -66,7 +66,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = {
SET_FMAN_RX_1G_LIODN(1, 2, 12),
SET_FMAN_RX_1G_LIODN(1, 3, 13),
SET_FMAN_RX_1G_LIODN(1, 4, 14),
#if (CONFIG_SYS_NUM_FM1_10GEC == 1)
#if (CFG_SYS_NUM_FM1_10GEC == 1)
SET_FMAN_RX_10G_LIODN(1, 0, 15),
#endif
};

4
arch/powerpc/cpu/mpc85xx/p4080_ids.c
View File

@ -62,7 +62,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = {
};
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
struct fman_liodn_id_table fman2_liodn_tbl[] = {
SET_FMAN_RX_1G_LIODN(2, 0, 16),
SET_FMAN_RX_1G_LIODN(2, 1, 17),
@ -101,7 +101,7 @@ struct liodn_id_table liodn_bases[] = {
[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106),
#ifdef CONFIG_SYS_DPAA_FMAN
[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64),
#endif
#endif

4
arch/powerpc/cpu/mpc85xx/p5040_ids.c
View File

@ -57,7 +57,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = {
};
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
struct fman_liodn_id_table fman2_liodn_tbl[] = {
SET_FMAN_RX_1G_LIODN(2, 0, 17),
SET_FMAN_RX_1G_LIODN(2, 1, 18),
@ -101,7 +101,7 @@ struct liodn_id_table liodn_bases[] = {
#ifdef CONFIG_SYS_DPAA_FMAN
[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
#endif
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(160),
#endif
#ifdef CONFIG_SYS_FSL_RAID_ENGINE

6
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -406,7 +406,7 @@ void get_sys_info(sys_info_t *sys_info)
sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
break;
}
#if (CONFIG_SYS_NUM_FMAN) == 2
#if (CFG_SYS_NUM_FMAN) == 2
#ifdef CONFIG_SYS_FM2_CLK
#define FM2_CLK_SEL 0x00000038
#define FM2_CLK_SHIFT 3
@ -440,7 +440,7 @@ void get_sys_info(sys_info_t *sys_info)
break;
}
#endif
#endif /* CONFIG_SYS_NUM_FMAN == 2 */
#endif /* CFG_SYS_NUM_FMAN == 2 */
#else
sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
#endif
@ -491,7 +491,7 @@ void get_sys_info(sys_info_t *sys_info)
} else {
sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
}
#if (CONFIG_SYS_NUM_FMAN) == 2
#if (CFG_SYS_NUM_FMAN) == 2
if (rcw_tmp & FM2_CLK_SEL) {
if (rcw_tmp & HWA_ASYNC_DIV)
sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;

4
arch/powerpc/cpu/mpc85xx/t4240_ids.c
View File

@ -122,7 +122,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = {
SET_FMAN_RX_10G_LIODN(1, 1, 95),
};
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
struct fman_liodn_id_table fman2_liodn_tbl[] = {
SET_FMAN_RX_1G_LIODN(2, 0, 88),
SET_FMAN_RX_1G_LIODN(2, 1, 89),
@ -175,7 +175,7 @@ struct liodn_id_table liodn_bases[] = {
[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558),
#ifdef CONFIG_SYS_DPAA_FMAN
[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(1069),
#endif
#endif

80
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -41,8 +41,8 @@
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_P1023)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 2
#define CONFIG_SYS_QMAN_NUM_PORTALS 3
#define CONFIG_SYS_BMAN_NUM_PORTALS 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
@ -65,9 +65,9 @@
#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 5
#define CFG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
@ -75,9 +75,9 @@
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P3041)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 5
#define CFG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
@ -85,11 +85,11 @@
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM2_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CFG_SYS_NUM_FMAN 2
#define CFG_SYS_NUM_FM1_DTSEC 4
#define CFG_SYS_NUM_FM2_DTSEC 4
#define CFG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_NUM_FM2_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
@ -98,11 +98,11 @@
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#elif defined(CONFIG_ARCH_P5040)
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 5
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CFG_SYS_NUM_FMAN 2
#define CFG_SYS_NUM_FM1_DTSEC 5
#define CFG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_NUM_FM2_DTSEC 5
#define CFG_SYS_NUM_FM2_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
@ -119,21 +119,21 @@
#elif defined(CONFIG_ARCH_T4240)
#ifdef CONFIG_ARCH_T4240
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 2
#define CFG_SYS_NUM_FM1_DTSEC 8
#define CFG_SYS_NUM_FM1_10GEC 2
#define CFG_SYS_NUM_FM2_DTSEC 8
#define CFG_SYS_NUM_FM2_10GEC 2
#else
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CFG_SYS_NUM_FM1_DTSEC 6
#define CFG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_NUM_FM2_DTSEC 8
#define CFG_SYS_NUM_FM2_10GEC 1
#endif
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CFG_SYS_FSL_SRDS_3
#define CFG_SYS_FSL_SRDS_4
#define CONFIG_SYS_NUM_FMAN 2
#define CFG_SYS_NUM_FMAN 2
#define CONFIG_SYS_PME_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 3
@ -146,7 +146,7 @@
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FMAN 1
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
@ -155,23 +155,23 @@
#define CONFIG_MAX_DSP_CPUS 12
#define CONFIG_NUM_DSP_CPUS 6
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CFG_SYS_NUM_FM1_DTSEC 6
#define CFG_SYS_NUM_FM1_10GEC 2
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#else
#define CONFIG_MAX_DSP_CPUS 2
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 0
#define CFG_SYS_NUM_FM1_DTSEC 4
#define CFG_SYS_NUM_FM1_10GEC 0
#endif
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_PME_PLAT_CLK_DIV 2
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
@ -186,9 +186,9 @@
#elif defined(CONFIG_ARCH_T1024)
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 4
#define CFG_SYS_NUM_FM1_10GEC 1
#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 0
@ -200,12 +200,12 @@
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 4
#define CFG_SYS_NUM_FM1_DTSEC 8
#define CFG_SYS_NUM_FM1_10GEC 4
#define CONFIG_SYS_FSL_SRDS_2
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9

2
arch/powerpc/include/asm/fsl_portals.h
View File

@ -11,7 +11,7 @@ enum fsl_dpaa_dev {
FSL_HW_PORTAL_SEC,
#ifdef CONFIG_SYS_DPAA_FMAN
FSL_HW_PORTAL_FMAN1,
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
FSL_HW_PORTAL_FMAN2,
#endif
#endif

2
board/freescale/ls1043aqds/eth.c
View File

@ -427,7 +427,7 @@ int board_eth_init(struct bd_info *bis)
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
idx = i - FM1_DTSEC1;
interface = fm_info_get_enet_if(i);
switch (interface) {

2
board/freescale/ls1043ardb/eth.c
View File

@ -62,7 +62,7 @@ int board_eth_init(struct bd_info *bis)
}
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++)
fm_info_set_mdio(i, dev);
/* 10GBase-R on lane A, MAC 9 */

2
board/freescale/ls1046aqds/eth.c
View File

@ -349,7 +349,7 @@ int board_eth_init(struct bd_info *bis)
/* SGMII on slot 4, MAC 2 */
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
idx = i - FM1_DTSEC1;
interface = fm_info_get_enet_if(i);
switch (interface) {

2
board/freescale/ls1046ardb/eth.c
View File

@ -64,7 +64,7 @@ int board_eth_init(struct bd_info *bis)
}
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++)
fm_info_set_mdio(i, dev);
/* 10GBase-R on lane A, MAC 9 */

2
board/freescale/p2041rdb/eth.c
View File

@ -162,7 +162,7 @@ int board_eth_init(struct bd_info *bis)
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {

4
board/freescale/t102xrdb/eth_t102xrdb.c
View File

@ -85,7 +85,7 @@ int board_eth_init(struct bd_info *bis)
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_RGMII:
@ -112,7 +112,7 @@ int board_eth_init(struct bd_info *bis)
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);

2
board/freescale/t104xrdb/eth.c
View File

@ -39,7 +39,7 @@ int board_eth_init(struct bd_info *bis)
/*
* Program on board RGMII, SGMII PHY addresses.
*/
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {

4
board/freescale/t208xqds/eth_t208xqds.c
View File

@ -625,7 +625,7 @@ int board_eth_init(struct bd_info *bis)
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
idx = i - FM1_DTSEC1;
interface = fm_info_get_enet_if(i);
switch (interface) {
@ -673,7 +673,7 @@ int board_eth_init(struct bd_info *bis)
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
idx = i - FM1_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:

12
board/freescale/t4rdb/eth.c
View File

@ -81,7 +81,7 @@ int board_eth_init(struct bd_info *bis)
fm_disable_port(FM1_DTSEC5);
fm_disable_port(FM1_DTSEC6);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
@ -93,7 +93,7 @@ int board_eth_init(struct bd_info *bis)
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
@ -104,7 +104,7 @@ int board_eth_init(struct bd_info *bis)
}
}
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
/* SGMII && 10GBase-R */
fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
@ -121,7 +121,7 @@ int board_eth_init(struct bd_info *bis)
fm_disable_port(FM2_DTSEC5);
fm_disable_port(FM2_DTSEC6);
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CFG_SYS_NUM_FM2_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
@ -133,7 +133,7 @@ int board_eth_init(struct bd_info *bis)
}
}
for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
for (i = FM2_10GEC1; i < FM2_10GEC1 + CFG_SYS_NUM_FM2_10GEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
@ -143,7 +143,7 @@ int board_eth_init(struct bd_info *bis)
break;
}
}
#endif /* CONFIG_SYS_NUM_FMAN */
#endif /* CFG_SYS_NUM_FMAN */
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */

8
board/freescale/t4rdb/t4rdb.h
View File

@ -6,10 +6,10 @@
#ifndef __T4RDB_H__
#define __T4RDB_H__
#undef CONFIG_SYS_NUM_FM1_DTSEC
#undef CONFIG_SYS_NUM_FM2_DTSEC
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM2_DTSEC 4
#undef CFG_SYS_NUM_FM1_DTSEC
#undef CFG_SYS_NUM_FM2_DTSEC
#define CFG_SYS_NUM_FM1_DTSEC 4
#define CFG_SYS_NUM_FM2_DTSEC 4
#define CORTINA_FW_ADDR_IFCNOR 0xefe00000
#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebf00000

6
cmd/i2c.c
View File

@ -1697,7 +1697,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc,
#else
int i;
for (i = 0; i < CONFIG_SYS_NUM_I2C_BUSES; i++) {
for (i = 0; i < CFG_SYS_NUM_I2C_BUSES; i++) {
printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
#ifndef CONFIG_SYS_I2C_DIRECT_BUS
int j;
@ -1730,7 +1730,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc,
}
show_bus(bus);
#else
if (i >= CONFIG_SYS_NUM_I2C_BUSES) {
if (i >= CFG_SYS_NUM_I2C_BUSES) {
printf("Invalid bus %d\n", i);
return -1;
}
@ -1788,7 +1788,7 @@ static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc,
} else {
bus_no = dectoul(argv[1], NULL);
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) {
if (bus_no >= CFG_SYS_NUM_I2C_BUSES) {
printf("Invalid bus %d\n", bus_no);
return -1;
}

6
drivers/i2c/i2c_core.c
View File

@ -34,7 +34,7 @@ struct i2c_adapter *i2c_get_adapter(int index)
}
#if !defined(CONFIG_SYS_I2C_DIRECT_BUS)
struct i2c_bus_hose i2c_bus[CONFIG_SYS_NUM_I2C_BUSES] =
struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] =
CONFIG_SYS_I2C_BUSES;
#endif
@ -173,7 +173,7 @@ static int i2c_mux_disconnect_all(void)
*/
static void i2c_init_bus(unsigned int bus_no, int speed, int slaveaddr)
{
if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES)
if (bus_no >= CFG_SYS_NUM_I2C_BUSES)
return;
I2C_ADAP->init(I2C_ADAP, speed, slaveaddr);
@ -238,7 +238,7 @@ int i2c_set_bus_num(unsigned int bus)
return 0;
#ifndef CONFIG_SYS_I2C_DIRECT_BUS
if (bus >= CONFIG_SYS_NUM_I2C_BUSES)
if (bus >= CFG_SYS_NUM_I2C_BUSES)
return -1;
#endif

2
drivers/misc/fsl_portals.c
View File

@ -257,7 +257,7 @@ defined(CONFIG_ARCH_LS1046A)
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
for (j = 0; j < CFG_SYS_NUM_FMAN; j++) {
char name[] = "fman@0";
name[sizeof(name) - 2] = '0' + j;

2
drivers/net/fm/fm.c
View File

@ -26,7 +26,7 @@
#include <asm/arch/cpu.h>
#endif
struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
struct fm_muram muram[CFG_SYS_NUM_FMAN];
void *fm_muram_base(int fm_idx)
{

4
drivers/net/fm/fm.h
View File

@ -15,11 +15,11 @@
#define OH_PORT_ID_BASE 0x01
#define MAX_NUM_OH_PORT 7
#define RX_PORT_1G_BASE 0x08
#define MAX_NUM_RX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC
#define MAX_NUM_RX_PORT_1G CFG_SYS_NUM_FM1_DTSEC
#define RX_PORT_10G_BASE 0x10
#define RX_PORT_10G_BASE2 0x08
#define TX_PORT_1G_BASE 0x28
#define MAX_NUM_TX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC
#define MAX_NUM_TX_PORT_1G CFG_SYS_NUM_FM1_DTSEC
#define TX_PORT_10G_BASE 0x30
#define TX_PORT_10G_BASE2 0x28
#define MIIM_TIMEOUT 0xFFFF

48
drivers/net/fm/init.c
View File

@ -19,70 +19,70 @@
#ifndef CONFIG_DM_ETH
struct fm_eth_info fm_info[] = {
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 1)
#if (CFG_SYS_NUM_FM1_DTSEC >= 1)
FM_DTSEC_INFO_INITIALIZER(1, 1),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 2)
#if (CFG_SYS_NUM_FM1_DTSEC >= 2)
FM_DTSEC_INFO_INITIALIZER(1, 2),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 3)
#if (CFG_SYS_NUM_FM1_DTSEC >= 3)
FM_DTSEC_INFO_INITIALIZER(1, 3),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 4)
#if (CFG_SYS_NUM_FM1_DTSEC >= 4)
FM_DTSEC_INFO_INITIALIZER(1, 4),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 5)
#if (CFG_SYS_NUM_FM1_DTSEC >= 5)
FM_DTSEC_INFO_INITIALIZER(1, 5),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 6)
#if (CFG_SYS_NUM_FM1_DTSEC >= 6)
FM_DTSEC_INFO_INITIALIZER(1, 6),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 7)
#if (CFG_SYS_NUM_FM1_DTSEC >= 7)
FM_DTSEC_INFO_INITIALIZER(1, 9),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 8)
#if (CFG_SYS_NUM_FM1_DTSEC >= 8)
FM_DTSEC_INFO_INITIALIZER(1, 10),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 1)
#if (CFG_SYS_NUM_FM2_DTSEC >= 1)
FM_DTSEC_INFO_INITIALIZER(2, 1),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 2)
#if (CFG_SYS_NUM_FM2_DTSEC >= 2)
FM_DTSEC_INFO_INITIALIZER(2, 2),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 3)
#if (CFG_SYS_NUM_FM2_DTSEC >= 3)
FM_DTSEC_INFO_INITIALIZER(2, 3),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4)
#if (CFG_SYS_NUM_FM2_DTSEC >= 4)
FM_DTSEC_INFO_INITIALIZER(2, 4),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
#if (CFG_SYS_NUM_FM2_DTSEC >= 5)
FM_DTSEC_INFO_INITIALIZER(2, 5),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 6)
#if (CFG_SYS_NUM_FM2_DTSEC >= 6)
FM_DTSEC_INFO_INITIALIZER(2, 6),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 7)
#if (CFG_SYS_NUM_FM2_DTSEC >= 7)
FM_DTSEC_INFO_INITIALIZER(2, 9),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 8)
#if (CFG_SYS_NUM_FM2_DTSEC >= 8)
FM_DTSEC_INFO_INITIALIZER(2, 10),
#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
#if (CFG_SYS_NUM_FM1_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(1, 1),
#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 2)
#if (CFG_SYS_NUM_FM1_10GEC >= 2)
FM_TGEC_INFO_INITIALIZER(1, 2),
#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
#if (CFG_SYS_NUM_FM1_10GEC >= 3)
FM_TGEC_INFO_INITIALIZER2(1, 3),
#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 4)
#if (CFG_SYS_NUM_FM1_10GEC >= 4)
FM_TGEC_INFO_INITIALIZER2(1, 4),
#endif
#if (CONFIG_SYS_NUM_FM2_10GEC >= 1)
#if (CFG_SYS_NUM_FM2_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(2, 1),
#endif
#if (CONFIG_SYS_NUM_FM2_10GEC >= 2)
#if (CFG_SYS_NUM_FM2_10GEC >= 2)
FM_TGEC_INFO_INITIALIZER(2, 2),
#endif
};
@ -101,7 +101,7 @@ int fm_standard_init(struct bd_info *bis)
fm_eth_initialize(reg, &fm_info[i]);
}
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
reg = (void *)CFG_SYS_FSL_FM2_ADDR;
if (fm_init_common(1, reg))
return 0;
@ -276,7 +276,7 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) ||
((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC2)))
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
||
((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1))) ||
((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2))) ||

2
include/configs/P2041RDB.h
View File

@ -30,7 +30,7 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */

2
include/configs/T102xRDB.h
View File

@ -15,7 +15,7 @@
/* High Level Configuration Options */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#ifdef CONFIG_RAMBOOT_PBL
#define RESET_VECTOR_OFFSET 0x27FFC

2
include/configs/T104xRDB.h
View File

@ -58,7 +58,7 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
/*
* These can be toggled for performance analysis, otherwise use default.

2
include/configs/T208xQDS.h
View File

@ -22,7 +22,7 @@
/* High Level Configuration Options */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#ifdef CONFIG_RAMBOOT_PBL
#define RESET_VECTOR_OFFSET 0x27FFC

2
include/configs/T208xRDB.h
View File

@ -17,7 +17,7 @@
/* High Level Configuration Options */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#ifdef CONFIG_RAMBOOT_PBL
#define RESET_VECTOR_OFFSET 0x27FFC

2
include/configs/T4240RDB.h
View File

@ -39,7 +39,7 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
/*
* These can be toggled for performance analysis, otherwise use default.

2
include/configs/km/km-mpc83xx.h
View File

@ -50,7 +50,7 @@
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
/* I2C */
#define CONFIG_SYS_NUM_I2C_BUSES 4
#define CFG_SYS_NUM_I2C_BUSES 4
#define CONFIG_SYS_I2C_MAX_HOPS 1
#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \

2
include/configs/km/pg-wcom-ls102xa.h
View File

@ -156,7 +156,7 @@
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_MAX_HOPS 1
#define CONFIG_SYS_NUM_I2C_BUSES 3
#define CFG_SYS_NUM_I2C_BUSES 3
#define I2C_MUX_PCA_ADDR 0x70
#define I2C_MUX_CH_DEFAULT 0x0
#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \

2
include/configs/kmcent2.h
View File

@ -136,7 +136,7 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
/* Environment in parallel NOR-Flash */
#define CONFIG_ENV_TOTAL_SIZE 0x040000

2
include/e500.h
View File

@ -19,7 +19,7 @@ typedef struct
unsigned long freq_localbus;
unsigned long freq_qe;
#ifdef CONFIG_SYS_DPAA_FMAN
unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
unsigned long freq_fman[CFG_SYS_NUM_FMAN];
#endif
#ifdef CONFIG_SYS_DPAA_QBMAN
unsigned long freq_qman;

6
include/fm_eth.h
View File

@ -56,7 +56,7 @@ enum fm_eth_type {
#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfc000)
#endif
#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000)
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfc000)
#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfd000)
#endif
@ -102,7 +102,7 @@ enum fm_eth_type {
offsetof(struct ccsr_fman, memac[n-1]),\
}
#else
#if (CONFIG_SYS_NUM_FMAN == 2)
#if (CFG_SYS_NUM_FMAN == 2)
#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{ \
FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
@ -131,7 +131,7 @@ enum fm_eth_type {
#endif
#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
#if (CFG_SYS_NUM_FM1_10GEC >= 3)
#define FM_TGEC_INFO_INITIALIZER2(idx, n) \
{ \
FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \

2
include/i2c.h
View File

@ -637,7 +637,7 @@ void i2c_early_init_f(void);
/* no muxes used bus = i2c adapters */
#define CONFIG_SYS_I2C_DIRECT_BUS 1
#define CONFIG_SYS_I2C_MAX_HOPS 0
#define CONFIG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c)
#define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c)
#else
/* we use i2c muxes */
#undef CONFIG_SYS_I2C_DIRECT_BUS