ARM: dts: socfpga: Add u-boot,dm-pre-reloc to necessary clock nodes
Add the pre-reloc DT markers to clock nodes needed in SPL and early U-Boot stages. This is required to let the Arria10 clock driver start early and provide clock information for UART and SDMMC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
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@ -94,29 +94,35 @@
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clkmgr@ffd04000 {
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compatible = "altr,clk-mgr";
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reg = <0xffd04000 0x1000>;
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u-boot,dm-pre-reloc;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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u-boot,dm-pre-reloc;
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cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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u-boot,dm-pre-reloc;
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};
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cb_intosc_ls_clk: cb_intosc_ls_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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u-boot,dm-pre-reloc;
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};
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f2s_free_clk: f2s_free_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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u-boot,dm-pre-reloc;
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};
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osc1: osc1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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u-boot,dm-pre-reloc;
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};
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main_pll: main_pll@40 {
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@ -127,6 +133,7 @@
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clocks = <&osc1>, <&cb_intosc_ls_clk>,
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<&f2s_free_clk>;
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reg = <0x40>;
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u-boot,dm-pre-reloc;
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main_mpu_base_clk: main_mpu_base_clk {
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#clock-cells = <0>;
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@ -215,6 +222,7 @@
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clocks = <&osc1>, <&cb_intosc_ls_clk>,
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<&f2s_free_clk>, <&main_periph_ref_clk>;
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reg = <0xC0>;
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u-boot,dm-pre-reloc;
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peri_mpu_base_clk: peri_mpu_base_clk {
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#clock-cells = <0>;
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@ -167,3 +167,28 @@
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&watchdog1 {
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status = "okay";
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};
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/* Clock available early */
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&main_noc_base_clk {
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u-boot,dm-pre-reloc;
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};
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&main_periph_ref_clk {
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u-boot,dm-pre-reloc;
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};
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&peri_noc_base_clk {
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u-boot,dm-pre-reloc;
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};
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&noc_free_clk {
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u-boot,dm-pre-reloc;
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};
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&l4_mp_clk {
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u-boot,dm-pre-reloc;
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};
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&l4_sp_clk {
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u-boot,dm-pre-reloc;
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};
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@ -38,3 +38,20 @@
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<48 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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/* Clock available early */
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&main_sdmmc_clk {
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u-boot,dm-pre-reloc;
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};
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&peri_sdmmc_clk {
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u-boot,dm-pre-reloc;
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};
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&sdmmc_free_clk {
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u-boot,dm-pre-reloc;
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};
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&sdmmc_clk {
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u-boot,dm-pre-reloc;
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};
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