Merge branch 'master' of git://git.denx.de/u-boot-mmc
This commit is contained in:
commit
ccbbada0a5
@ -10,6 +10,7 @@
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#include <command.h>
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#include <environment.h>
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#include <fdtdec.h>
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#include <linux/stddef.h>
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#include <malloc.h>
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#include <memalign.h>
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@ -36,15 +37,37 @@ DECLARE_GLOBAL_DATA_PTR;
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#define CONFIG_ENV_OFFSET 0
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#endif
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__weak int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
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#if CONFIG_IS_ENABLED(OF_CONTROL)
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static inline s64 mmc_offset(int copy)
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{
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s64 offset;
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const char *propname = "u-boot,mmc-env-offset";
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s64 defvalue = CONFIG_ENV_OFFSET;
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offset = CONFIG_ENV_OFFSET;
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#ifdef CONFIG_ENV_OFFSET_REDUND
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#if defined(CONFIG_ENV_OFFSET_REDUND)
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if (copy) {
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propname = "u-boot,mmc-env-offset-redundant";
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defvalue = CONFIG_ENV_OFFSET_REDUND;
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}
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#endif
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return fdtdec_get_config_int(gd->fdt_blob, propname, defvalue);
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}
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#else
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static inline s64 mmc_offset(int copy)
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{
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s64 offset = CONFIG_ENV_OFFSET;
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#if defined(CONFIG_ENV_OFFSET_REDUND)
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if (copy)
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offset = CONFIG_ENV_OFFSET_REDUND;
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#endif
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return offset;
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}
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#endif
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__weak int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
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{
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s64 offset = mmc_offset(copy);
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if (offset < 0)
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offset += mmc->capacity;
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@ -21,6 +21,18 @@ u-boot,efi-partition-entries-offset
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This setting will override any values configured via Kconfig.
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u-boot,mmc-env-offset
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u-boot,mmc-env-offset-redundant
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If present, the values of the 'u-boot,mmc-env-offset' and/or
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of the u-boot,mmc-env-offset-redundant' properties overrides
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CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND, respectively,
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for SD/MMC devices.
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Values are interpreted as the offset from the start of the
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device, specified in bytes. It is assumed that the setting
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will point at the beginning of a LBA and values that are not
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LBA-aligned will be rounded up to the next LBA address.
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u-boot,spl-payload-offset
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If present (and SPL is controlled by the device-tree), this allows
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to override the CONFIG_SYS_SPI_U_BOOT_OFFS setting using a value
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@ -244,7 +244,7 @@ static int meson_mmc_probe(struct udevice *dev)
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MMC_MODE_HS_52MHz | MMC_MODE_HS;
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cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
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cfg->f_max = 100000000; /* 100 MHz */
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cfg->b_max = 256; /* max 256 blocks */
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cfg->b_max = 511; /* max 512 - 1 blocks */
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cfg->name = dev->name;
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mmc->priv = pdata;
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@ -101,7 +101,7 @@ int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
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/* set voltage level */
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if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, dc_cntrl_reg, volt_sel,
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TPS65218_MASK_ALL_BITS))
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TPS65218_DCDC_VSEL_MASK))
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return 1;
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/* set GO bit to initiate voltage transition */
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@ -71,8 +71,8 @@ static const char max77686_buck_out[] = {
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static int max77686_buck_volt2hex(int buck, int uV)
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{
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unsigned int hex = 0;
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unsigned int hex_max = 0;
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int hex = 0;
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int hex_max = 0;
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switch (buck) {
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case 2:
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@ -105,7 +105,7 @@ static int max77686_buck_volt2hex(int buck, int uV)
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static int max77686_buck_hex2volt(int buck, int hex)
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{
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unsigned uV = 0;
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unsigned int hex_max = 0;
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int hex_max = 0;
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if (hex < 0)
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goto bad_hex;
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@ -140,7 +140,7 @@ bad_hex:
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static int max77686_ldo_volt2hex(int ldo, int uV)
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{
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unsigned int hex = 0;
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int hex = 0;
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switch (ldo) {
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case 1:
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@ -319,9 +319,9 @@ static int max77686_ldo_modes(int ldo, struct dm_regulator_mode **modesp,
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static int max77686_ldo_val(struct udevice *dev, int op, int *uV)
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{
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unsigned int hex, adr;
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unsigned int adr;
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unsigned char val;
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int ldo, ret;
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int hex, ldo, ret;
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if (op == PMIC_OP_GET)
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*uV = 0;
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@ -360,9 +360,9 @@ static int max77686_ldo_val(struct udevice *dev, int op, int *uV)
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static int max77686_buck_val(struct udevice *dev, int op, int *uV)
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{
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unsigned int hex, mask, adr;
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unsigned int mask, adr;
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unsigned char val;
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int buck, ret;
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int hex, buck, ret;
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buck = dev->driver_data;
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if (buck < 1 || buck > MAX77686_BUCK_NUM) {
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@ -430,7 +430,7 @@ struct mmc {
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u8 part_support;
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u8 part_attr;
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u8 wr_rel_set;
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char part_config;
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u8 part_config;
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uint tran_speed;
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uint read_bl_len;
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uint write_bl_len;
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@ -56,6 +56,8 @@ enum {
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#define TPS65218_MASK_ALL_BITS 0xFF
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#define TPS65218_DCDC_VSEL_MASK 0x3F
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#define TPS65218_DCDC_VOLT_SEL_0950MV 0x0a
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#define TPS65218_DCDC_VOLT_SEL_1100MV 0x19
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#define TPS65218_DCDC_VOLT_SEL_1200MV 0x23
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