Merge branch 'master' of git://git.denx.de/u-boot-i2c
This commit is contained in:
Tom Rini
commit
cb33bda44f
64
README
64
README
@ -2204,52 +2204,7 @@ The following options need to be configured:
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If you do not have i2c muxes on your board, omit this define.
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- Legacy I2C Support: CONFIG_HARD_I2C
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NOTE: It is intended to move drivers to CONFIG_SYS_I2C which
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provides the following compelling advantages:
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- more than one i2c adapter is usable
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- approved multibus support
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- better i2c mux support
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** Please consider updating your I2C driver now. **
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These enable legacy I2C serial bus commands. Defining
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CONFIG_HARD_I2C will include the appropriate I2C driver
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for the selected CPU.
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This will allow you to use i2c commands at the u-boot
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command line (as long as you set CONFIG_CMD_I2C in
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CONFIG_COMMANDS) and communicate with i2c based realtime
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clock chips. See common/cmd_i2c.c for a description of the
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command line interface.
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CONFIG_HARD_I2C selects a hardware I2C controller.
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There are several other quantities that must also be
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defined when you define CONFIG_HARD_I2C.
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In both cases you will need to define CONFIG_SYS_I2C_SPEED
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to be the frequency (in Hz) at which you wish your i2c bus
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to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
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the CPU's i2c node address).
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Now, the u-boot i2c code for the mpc8xx
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(arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
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and so its address should therefore be cleared to 0 (See,
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eg, MPC823e User's Manual p.16-473). So, set
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CONFIG_SYS_I2C_SLAVE to 0.
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CONFIG_SYS_I2C_INIT_MPC5XXX
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When a board is reset during an i2c bus transfer
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chips might think that the current transfer is still
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in progress. Reset the slave devices by sending start
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commands until the slave device responds.
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That's all that's required for CONFIG_HARD_I2C.
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- Legacy I2C Support:
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If you use the software i2c interface (CONFIG_SYS_I2C_SOFT)
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then the following macros need to be defined (examples are
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from include/configs/lwmon.h):
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@ -2338,23 +2293,6 @@ The following options need to be configured:
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custom i2c_init_board() routine in boards/xxx/board.c
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is run early in the boot sequence.
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CONFIG_SYS_I2C_BOARD_LATE_INIT
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An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is
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defined a custom i2c_board_late_init() routine in
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boards/xxx/board.c is run AFTER the operations in i2c_init()
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is completed. This callpoint can be used to unreset i2c bus
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using CPU i2c controller register accesses for CPUs whose i2c
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controller provide such a method. It is called at the end of
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i2c_init() to allow i2c_init operations to setup the i2c bus
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controller on the CPU (e.g. setting bus speed & slave address).
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CONFIG_I2CFAST (PPC405GP|PPC405EP only)
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This option enables configuration of bi_iic_fast[] flags
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in u-boot bd_info structure based on u-boot environment
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variable "i2cfast". (see also i2cfast)
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CONFIG_I2C_MULTI_BUS
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This option allows the use of multiple I2C buses, each of which
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@ -24,17 +24,5 @@
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#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE
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#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
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represents UART Unit Enable */
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/*
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* I2C definition
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*/
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#ifdef CONFIG_CMD_I2C
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#define CONFIG_I2C_MV 1
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#define CONFIG_MV_I2C_NUM 2
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#define CONFIG_I2C_MULTI_BUS 1
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#define CONFIG_MV_I2C_REG {0xd4011000, 0xd4025000}
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#define CONFIG_HARD_I2C 1
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#define CONFIG_SYS_I2C_SPEED 0
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#define CONFIG_SYS_I2C_SLAVE 0xfe
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#endif
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#endif /* _ARMD1_CONFIG_H */
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@ -9,7 +9,6 @@ obj-y := cpu.o
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obj-y += traps.o
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obj-y += cpu_init.o
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obj-y += fixed_sdram.o
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obj-y += i2c.o
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obj-y += interrupts.o
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obj-y += iopin.o
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obj-y += serial.o
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@ -1,386 +0,0 @@
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/*
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* (C) Copyright 2003 - 2009
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Based on the MPC5xxx code.
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*/
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#include <common.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_HARD_I2C
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#include <i2c.h>
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/* by default set I2C bus 0 active */
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static unsigned int bus_num __attribute__ ((section (".data"))) = 0;
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#define I2C_TIMEOUT 100
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#define I2C_RETRIES 3
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struct mpc512x_i2c_tap {
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int scl2tap;
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int tap2tap;
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};
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static int mpc_reg_in(volatile u32 *reg);
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static void mpc_reg_out(volatile u32 *reg, int val, int mask);
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static int wait_for_bb(void);
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static int wait_for_pin(int *status);
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static int do_address(uchar chip, char rdwr_flag);
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static int send_bytes(uchar chip, char *buf, int len);
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static int receive_bytes(uchar chip, char *buf, int len);
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static int mpc_get_fdr(int);
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static int mpc_reg_in (volatile u32 *reg)
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{
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int ret = in_be32(reg) >> 24;
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return ret;
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}
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static void mpc_reg_out (volatile u32 *reg, int val, int mask)
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{
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if (!mask) {
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out_be32(reg, val << 24);
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} else {
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clrsetbits_be32(reg, mask << 24, (val & mask) << 24);
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}
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}
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static int wait_for_bb (void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
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int timeout = I2C_TIMEOUT;
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int status;
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status = mpc_reg_in (®s->msr);
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while (timeout-- && (status & I2C_BB)) {
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mpc_reg_out (®s->mcr, I2C_STA, I2C_STA);
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(void)mpc_reg_in(®s->mdr);
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mpc_reg_out (®s->mcr, 0, I2C_STA);
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mpc_reg_out (®s->mcr, 0, 0);
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mpc_reg_out (®s->mcr, I2C_EN, 0);
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udelay (1000);
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status = mpc_reg_in (®s->msr);
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}
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return (status & I2C_BB);
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}
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static int wait_for_pin (int *status)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
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int timeout = I2C_TIMEOUT;
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*status = mpc_reg_in (®s->msr);
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while (timeout-- && !(*status & I2C_IF)) {
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udelay (1000);
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*status = mpc_reg_in (®s->msr);
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}
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if (!(*status & I2C_IF)) {
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return -1;
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}
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mpc_reg_out (®s->msr, 0, I2C_IF);
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return 0;
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}
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static int do_address (uchar chip, char rdwr_flag)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
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int status;
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chip <<= 1;
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if (rdwr_flag) {
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chip |= 1;
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}
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mpc_reg_out (®s->mcr, I2C_TX, I2C_TX);
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mpc_reg_out (®s->mdr, chip, 0);
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if (wait_for_pin (&status)) {
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return -2;
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}
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if (status & I2C_RXAK) {
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return -3;
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}
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return 0;
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}
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static int send_bytes (uchar chip, char *buf, int len)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
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int wrcount;
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int status;
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for (wrcount = 0; wrcount < len; ++wrcount) {
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mpc_reg_out (®s->mdr, buf[wrcount], 0);
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if (wait_for_pin (&status)) {
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break;
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}
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if (status & I2C_RXAK) {
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break;
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}
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}
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return !(wrcount == len);
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}
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static int receive_bytes (uchar chip, char *buf, int len)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
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int dummy = 1;
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int rdcount = 0;
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int status;
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int i;
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mpc_reg_out (®s->mcr, 0, I2C_TX);
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for (i = 0; i < len; ++i) {
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buf[rdcount] = mpc_reg_in (®s->mdr);
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if (dummy) {
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dummy = 0;
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} else {
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rdcount++;
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}
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if (wait_for_pin (&status)) {
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return -4;
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}
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}
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mpc_reg_out (®s->mcr, I2C_TXAK, I2C_TXAK);
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buf[rdcount++] = mpc_reg_in (®s->mdr);
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if (wait_for_pin (&status)) {
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return -5;
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}
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mpc_reg_out (®s->mcr, 0, I2C_TXAK);
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return 0;
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}
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/**************** I2C API ****************/
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void i2c_init (int speed, int saddr)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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int i;
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for (i = 0; i < I2C_BUS_CNT; i++){
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volatile i2c512x_dev_t *regs = &im->i2c.dev[i];
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mpc_reg_out (®s->mcr, 0, 0);
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/* Set clock */
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mpc_reg_out (®s->mfdr, mpc_get_fdr (speed), 0);
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mpc_reg_out (®s->madr, saddr << 1, 0);
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/* Enable module */
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mpc_reg_out (®s->mcr, I2C_EN, I2C_INIT_MASK);
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mpc_reg_out (®s->msr, 0, I2C_IF);
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}
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/* Disable interrupts */
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out_be32(&im->i2c.icr, 0);
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/* Turn off filters */
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||||
out_be32(&im->i2c.mifr, 0);
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||||
}
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static int mpc_get_fdr (int speed)
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{
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||||
static int fdr = -1;
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||||
|
||||
if (fdr == -1) {
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||||
ulong best_speed = 0;
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||||
ulong divider;
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ulong ips, scl;
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||||
ulong bestmatch = 0xffffffffUL;
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||||
int best_i = 0, best_j = 0, i, j;
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||||
int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8};
|
||||
struct mpc512x_i2c_tap scltap[] = {
|
||||
{4, 1},
|
||||
{4, 2},
|
||||
{6, 4},
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||||
{6, 8},
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||||
{14, 16},
|
||||
{30, 32},
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||||
{62, 64},
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||||
{126, 128}
|
||||
};
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||||
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||||
ips = gd->arch.ips_clk;
|
||||
for (i = 7; i >= 0; i--) {
|
||||
for (j = 7; j >= 0; j--) {
|
||||
scl = 2 * (scltap[j].scl2tap +
|
||||
(SCL_Tap[i] - 1) * scltap[j].tap2tap
|
||||
+ 2);
|
||||
if (ips <= speed*scl) {
|
||||
if ((speed*scl - ips) < bestmatch) {
|
||||
bestmatch = speed*scl - ips;
|
||||
best_i = i;
|
||||
best_j = j;
|
||||
best_speed = ips/scl;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2);
|
||||
if (gd->flags & GD_FLG_RELOC) {
|
||||
fdr = divider;
|
||||
} else {
|
||||
debug("%ld kHz, \n", best_speed / 1000);
|
||||
return divider;
|
||||
}
|
||||
}
|
||||
|
||||
return fdr;
|
||||
}
|
||||
|
||||
int i2c_probe (uchar chip)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
|
||||
int i;
|
||||
|
||||
for (i = 0; i < I2C_RETRIES; i++) {
|
||||
mpc_reg_out (®s->mcr, I2C_STA, I2C_STA);
|
||||
|
||||
if (! do_address (chip, 0)) {
|
||||
mpc_reg_out (®s->mcr, 0, I2C_STA);
|
||||
udelay (500);
|
||||
break;
|
||||
}
|
||||
|
||||
mpc_reg_out (®s->mcr, 0, I2C_STA);
|
||||
udelay (500);
|
||||
}
|
||||
|
||||
return (i == I2C_RETRIES);
|
||||
}
|
||||
|
||||
int i2c_read (uchar chip, uint addr, int alen, uchar *buf, int len)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
|
||||
char xaddr[4];
|
||||
int ret = -1;
|
||||
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
|
||||
if (wait_for_bb ()) {
|
||||
printf ("i2c_read: bus is busy\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
mpc_reg_out (®s->mcr, I2C_STA, I2C_STA);
|
||||
if (do_address (chip, 0)) {
|
||||
printf ("i2c_read: failed to address chip\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
if (send_bytes (chip, &xaddr[4-alen], alen)) {
|
||||
printf ("i2c_read: send_bytes failed\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
mpc_reg_out (®s->mcr, I2C_RSTA, I2C_RSTA);
|
||||
if (do_address (chip, 1)) {
|
||||
printf ("i2c_read: failed to address chip\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
if (receive_bytes (chip, (char *)buf, len)) {
|
||||
printf ("i2c_read: receive_bytes failed\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
Done:
|
||||
mpc_reg_out (®s->mcr, 0, I2C_STA);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int i2c_write (uchar chip, uint addr, int alen, uchar *buf, int len)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
|
||||
char xaddr[4];
|
||||
int ret = -1;
|
||||
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
|
||||
if (wait_for_bb ()) {
|
||||
printf ("i2c_write: bus is busy\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
mpc_reg_out (®s->mcr, I2C_STA, I2C_STA);
|
||||
if (do_address (chip, 0)) {
|
||||
printf ("i2c_write: failed to address chip\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
if (send_bytes (chip, &xaddr[4-alen], alen)) {
|
||||
printf ("i2c_write: send_bytes failed\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
if (send_bytes (chip, (char *)buf, len)) {
|
||||
printf ("i2c_write: send_bytes failed\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
Done:
|
||||
mpc_reg_out (®s->mcr, 0, I2C_STA);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int i2c_set_bus_num (unsigned int bus)
|
||||
{
|
||||
if (bus >= I2C_BUS_CNT) {
|
||||
return -1;
|
||||
}
|
||||
bus_num = bus;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int i2c_get_bus_num (void)
|
||||
{
|
||||
return bus_num;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_HARD_I2C */
|
||||
@ -9,7 +9,6 @@ extra-y = start.o
|
||||
extra-y += traps.o
|
||||
obj-y += io.o
|
||||
obj-y += firmware_sc_task_bestcomm.impl.o
|
||||
obj-y += i2c.o
|
||||
obj-y += cpu.o
|
||||
obj-y += cpu_init.o
|
||||
obj-y += ide.o
|
||||
|
||||
@ -1,456 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifdef CONFIG_HARD_I2C
|
||||
|
||||
#include <mpc5xxx.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#if !defined(CONFIG_I2C_MULTI_BUS)
|
||||
#if (CONFIG_SYS_I2C_MODULE == 2)
|
||||
#define I2C_BASE MPC5XXX_I2C2
|
||||
#elif (CONFIG_SYS_I2C_MODULE == 1)
|
||||
#define I2C_BASE MPC5XXX_I2C1
|
||||
#else
|
||||
#error CONFIG_SYS_I2C_MODULE is not properly configured
|
||||
#endif
|
||||
#else
|
||||
static unsigned int i2c_bus_num __attribute__ ((section (".data"))) =
|
||||
CONFIG_SYS_SPD_BUS_NUM;
|
||||
static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED,
|
||||
CONFIG_SYS_I2C_SPEED};
|
||||
|
||||
static const unsigned long i2c_dev[2] = {
|
||||
MPC5XXX_I2C1,
|
||||
MPC5XXX_I2C2,
|
||||
};
|
||||
|
||||
#define I2C_BASE ((struct mpc5xxx_i2c *)i2c_dev[i2c_bus_num])
|
||||
#endif
|
||||
|
||||
#define I2C_TIMEOUT 6667
|
||||
#define I2C_RETRIES 3
|
||||
|
||||
struct mpc5xxx_i2c_tap {
|
||||
int scl2tap;
|
||||
int tap2tap;
|
||||
};
|
||||
|
||||
static int mpc_reg_in (volatile u32 *reg);
|
||||
static void mpc_reg_out (volatile u32 *reg, int val, int mask);
|
||||
static int wait_for_bb (void);
|
||||
static int wait_for_pin (int *status);
|
||||
static int do_address (uchar chip, char rdwr_flag);
|
||||
static int send_bytes (uchar chip, char *buf, int len);
|
||||
static int receive_bytes (uchar chip, char *buf, int len);
|
||||
static int mpc_get_fdr (int);
|
||||
|
||||
static int mpc_reg_in(volatile u32 *reg)
|
||||
{
|
||||
int ret = *reg >> 24;
|
||||
__asm__ __volatile__ ("eieio");
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mpc_reg_out(volatile u32 *reg, int val, int mask)
|
||||
{
|
||||
int tmp;
|
||||
|
||||
if (!mask) {
|
||||
*reg = val << 24;
|
||||
} else {
|
||||
tmp = mpc_reg_in(reg);
|
||||
*reg = ((tmp & ~mask) | (val & mask)) << 24;
|
||||
}
|
||||
__asm__ __volatile__ ("eieio");
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static int wait_for_bb(void)
|
||||
{
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int timeout = I2C_TIMEOUT;
|
||||
int status;
|
||||
|
||||
status = mpc_reg_in(®s->msr);
|
||||
|
||||
while (timeout-- && (status & I2C_BB)) {
|
||||
mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
|
||||
(void)mpc_reg_in(®s->mdr);
|
||||
mpc_reg_out(®s->mcr, 0, I2C_STA);
|
||||
mpc_reg_out(®s->mcr, 0, 0);
|
||||
mpc_reg_out(®s->mcr, I2C_EN, 0);
|
||||
udelay(15);
|
||||
status = mpc_reg_in(®s->msr);
|
||||
}
|
||||
|
||||
return (status & I2C_BB);
|
||||
}
|
||||
|
||||
static int wait_for_pin(int *status)
|
||||
{
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int timeout = I2C_TIMEOUT;
|
||||
|
||||
*status = mpc_reg_in(®s->msr);
|
||||
|
||||
while (timeout-- && !(*status & I2C_IF)) {
|
||||
udelay(15);
|
||||
*status = mpc_reg_in(®s->msr);
|
||||
}
|
||||
|
||||
if (!(*status & I2C_IF)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->msr, 0, I2C_IF);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_address(uchar chip, char rdwr_flag)
|
||||
{
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int status;
|
||||
|
||||
chip <<= 1;
|
||||
|
||||
if (rdwr_flag) {
|
||||
chip |= 1;
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->mcr, I2C_TX, I2C_TX);
|
||||
mpc_reg_out(®s->mdr, chip, 0);
|
||||
|
||||
if (wait_for_pin(&status)) {
|
||||
return -2;
|
||||
}
|
||||
|
||||
if (status & I2C_RXAK) {
|
||||
return -3;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int send_bytes(uchar chip, char *buf, int len)
|
||||
{
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int wrcount;
|
||||
int status;
|
||||
|
||||
for (wrcount = 0; wrcount < len; ++wrcount) {
|
||||
|
||||
mpc_reg_out(®s->mdr, buf[wrcount], 0);
|
||||
|
||||
if (wait_for_pin(&status)) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (status & I2C_RXAK) {
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return !(wrcount == len);
|
||||
}
|
||||
|
||||
static int receive_bytes(uchar chip, char *buf, int len)
|
||||
{
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int dummy = 1;
|
||||
int rdcount = 0;
|
||||
int status;
|
||||
int i;
|
||||
|
||||
mpc_reg_out(®s->mcr, 0, I2C_TX);
|
||||
|
||||
for (i = 0; i < len; ++i) {
|
||||
buf[rdcount] = mpc_reg_in(®s->mdr);
|
||||
|
||||
if (dummy) {
|
||||
dummy = 0;
|
||||
} else {
|
||||
rdcount++;
|
||||
}
|
||||
|
||||
|
||||
if (wait_for_pin(&status)) {
|
||||
return -4;
|
||||
}
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->mcr, I2C_TXAK, I2C_TXAK);
|
||||
buf[rdcount++] = mpc_reg_in(®s->mdr);
|
||||
|
||||
if (wait_for_pin(&status)) {
|
||||
return -5;
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->mcr, 0, I2C_TXAK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SYS_I2C_INIT_MPC5XXX)
|
||||
|
||||
#define FDR510(x) (u8) (((x & 0x20) >> 3) | (x & 0x3))
|
||||
#define FDR432(x) (u8) ((x & 0x1C) >> 2)
|
||||
/*
|
||||
* Reset any i2c devices that may have been interrupted during a system reset.
|
||||
* Normally this would be accomplished by clocking the line until SCL and SDA
|
||||
* are released and then sending a start condtiion (From an Atmel datasheet).
|
||||
* There is no direct access to the i2c pins so instead create start commands
|
||||
* through the i2c interface. Send a start command then delay for the SDA Hold
|
||||
* time, repeat this by disabling/enabling the bus a total of 9 times.
|
||||
*/
|
||||
static void send_reset(void)
|
||||
{
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int i;
|
||||
u32 delay;
|
||||
u8 fdr;
|
||||
int SDA_Tap[] = { 3, 3, 4, 4, 1, 1, 2, 2};
|
||||
struct mpc5xxx_i2c_tap scltap[] = {
|
||||
{4, 1},
|
||||
{4, 2},
|
||||
{6, 4},
|
||||
{6, 8},
|
||||
{14, 16},
|
||||
{30, 32},
|
||||
{62, 64},
|
||||
{126, 128}
|
||||
};
|
||||
|
||||
fdr = (u8)mpc_reg_in(®s->mfdr);
|
||||
|
||||
delay = scltap[FDR432(fdr)].scl2tap + ((SDA_Tap[FDR510(fdr)] - 1) * \
|
||||
scltap[FDR432(fdr)].tap2tap) + 3;
|
||||
|
||||
for (i = 0; i < 9; i++) {
|
||||
mpc_reg_out(®s->mcr, I2C_EN|I2C_STA|I2C_TX, I2C_INIT_MASK);
|
||||
udelay(delay);
|
||||
mpc_reg_out(®s->mcr, 0, I2C_INIT_MASK);
|
||||
udelay(delay);
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK);
|
||||
}
|
||||
#endif /* CONFIG_SYS_I2c_INIT_MPC5XXX */
|
||||
|
||||
/**************** I2C API ****************/
|
||||
|
||||
void i2c_init(int speed, int saddr)
|
||||
{
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
|
||||
mpc_reg_out(®s->mcr, 0, 0);
|
||||
mpc_reg_out(®s->madr, saddr << 1, 0);
|
||||
|
||||
/* Set clock
|
||||
*/
|
||||
mpc_reg_out(®s->mfdr, mpc_get_fdr(speed), 0);
|
||||
|
||||
/* Enable module
|
||||
*/
|
||||
mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK);
|
||||
mpc_reg_out(®s->msr, 0, I2C_IF);
|
||||
|
||||
#if defined(CONFIG_SYS_I2C_INIT_MPC5XXX)
|
||||
send_reset();
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
|
||||
static int mpc_get_fdr(int speed)
|
||||
{
|
||||
static int fdr = -1;
|
||||
|
||||
if (fdr == -1) {
|
||||
ulong best_speed = 0;
|
||||
ulong divider;
|
||||
ulong ipb, scl;
|
||||
ulong bestmatch = 0xffffffffUL;
|
||||
int best_i = 0, best_j = 0, i, j;
|
||||
int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8};
|
||||
struct mpc5xxx_i2c_tap scltap[] = {
|
||||
{4, 1},
|
||||
{4, 2},
|
||||
{6, 4},
|
||||
{6, 8},
|
||||
{14, 16},
|
||||
{30, 32},
|
||||
{62, 64},
|
||||
{126, 128}
|
||||
};
|
||||
|
||||
ipb = gd->arch.ipb_clk;
|
||||
for (i = 7; i >= 0; i--) {
|
||||
for (j = 7; j >= 0; j--) {
|
||||
scl = 2 * (scltap[j].scl2tap +
|
||||
(SCL_Tap[i] - 1) * scltap[j].tap2tap + 2);
|
||||
if (ipb <= speed*scl) {
|
||||
if ((speed*scl - ipb) < bestmatch) {
|
||||
bestmatch = speed*scl - ipb;
|
||||
best_i = i;
|
||||
best_j = j;
|
||||
best_speed = ipb/scl;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2);
|
||||
if (gd->flags & GD_FLG_RELOC) {
|
||||
fdr = divider;
|
||||
} else {
|
||||
printf("%ld kHz, ", best_speed / 1000);
|
||||
return divider;
|
||||
}
|
||||
}
|
||||
|
||||
return fdr;
|
||||
}
|
||||
|
||||
int i2c_probe(uchar chip)
|
||||
{
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < I2C_RETRIES; i++) {
|
||||
mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
|
||||
|
||||
if (! do_address(chip, 0)) {
|
||||
mpc_reg_out(®s->mcr, 0, I2C_STA);
|
||||
udelay(500);
|
||||
break;
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->mcr, 0, I2C_STA);
|
||||
udelay(500);
|
||||
}
|
||||
|
||||
return (i == I2C_RETRIES);
|
||||
}
|
||||
|
||||
int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
|
||||
{
|
||||
char xaddr[4];
|
||||
struct mpc5xxx_i2c * regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int ret = -1;
|
||||
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
|
||||
if (wait_for_bb()) {
|
||||
printf("i2c_read: bus is busy\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
|
||||
if (do_address(chip, 0)) {
|
||||
printf("i2c_read: failed to address chip\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
if (send_bytes(chip, &xaddr[4-alen], alen)) {
|
||||
printf("i2c_read: send_bytes failed\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->mcr, I2C_RSTA, I2C_RSTA);
|
||||
if (do_address(chip, 1)) {
|
||||
printf("i2c_read: failed to address chip\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
if (receive_bytes(chip, (char *)buf, len)) {
|
||||
printf("i2c_read: receive_bytes failed\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
Done:
|
||||
mpc_reg_out(®s->mcr, 0, I2C_STA);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
|
||||
{
|
||||
char xaddr[4];
|
||||
struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
|
||||
int ret = -1;
|
||||
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
|
||||
if (wait_for_bb()) {
|
||||
printf("i2c_write: bus is busy\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
|
||||
if (do_address(chip, 0)) {
|
||||
printf("i2c_write: failed to address chip\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
if (send_bytes(chip, &xaddr[4-alen], alen)) {
|
||||
printf("i2c_write: send_bytes failed\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
if (send_bytes(chip, (char *)buf, len)) {
|
||||
printf("i2c_write: send_bytes failed\n");
|
||||
goto Done;
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
Done:
|
||||
mpc_reg_out(®s->mcr, 0, I2C_STA);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_I2C_MULTI_BUS)
|
||||
int i2c_set_bus_num(unsigned int bus)
|
||||
{
|
||||
if (bus > 1)
|
||||
return -1;
|
||||
|
||||
i2c_bus_num = bus;
|
||||
i2c_init(i2c_bus_speed[bus], CONFIG_SYS_I2C_SLAVE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_set_bus_speed(unsigned int speed)
|
||||
{
|
||||
i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int i2c_get_bus_num(void)
|
||||
{
|
||||
return i2c_bus_num;
|
||||
}
|
||||
|
||||
unsigned int i2c_get_bus_speed(void)
|
||||
{
|
||||
return i2c_bus_speed[i2c_bus_num];
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* CONFIG_HARD_I2C */
|
||||
@ -7,7 +7,7 @@
|
||||
|
||||
extra-y = start.o
|
||||
obj-y = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
|
||||
interrupts.o ether_fcc.o i2c.o commproc.o \
|
||||
interrupts.o ether_fcc.o commproc.o \
|
||||
bedbug_603e.o pci.o spi.o kgdb.o
|
||||
|
||||
obj-$(CONFIG_ETHER_ON_SCC) += ether_scc.o
|
||||
|
||||
@ -41,10 +41,6 @@ m8260_cpm_reset(void)
|
||||
do { /* Spin until command processed */
|
||||
__asm__ __volatile__ ("eieio");
|
||||
} while ((immr->im_cpm.cp_cpcr & CPM_CR_FLG) && ++count < 1000000);
|
||||
|
||||
#ifdef CONFIG_HARD_I2C
|
||||
immr->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)] = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Allocate some memory from the dual ported ram.
|
||||
|
||||
@ -1,741 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2000
|
||||
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
|
||||
*
|
||||
* (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <console.h>
|
||||
|
||||
#if defined(CONFIG_HARD_I2C)
|
||||
|
||||
#include <asm/cpm_8260.h>
|
||||
#include <i2c.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if defined(CONFIG_I2C_MULTI_BUS)
|
||||
static unsigned int i2c_bus_num __attribute__ ((section(".data"))) = 0;
|
||||
#endif /* CONFIG_I2C_MULTI_BUS */
|
||||
|
||||
/* uSec to wait between polls of the i2c */
|
||||
#define DELAY_US 100
|
||||
/* uSec to wait for the CPM to start processing the buffer */
|
||||
#define START_DELAY_US 1000
|
||||
|
||||
/*
|
||||
* tx/rx per-byte timeout: we delay DELAY_US uSec between polls so the
|
||||
* timeout will be (tx_length + rx_length) * DELAY_US * TOUT_LOOP
|
||||
*/
|
||||
#define TOUT_LOOP 5
|
||||
|
||||
/*
|
||||
* Set default values
|
||||
*/
|
||||
#ifndef CONFIG_SYS_I2C_SPEED
|
||||
#define CONFIG_SYS_I2C_SPEED 50000
|
||||
#endif
|
||||
|
||||
|
||||
typedef void (*i2c_ecb_t) (int, int, void *); /* error callback function */
|
||||
|
||||
/* This structure keeps track of the bd and buffer space usage. */
|
||||
typedef struct i2c_state {
|
||||
int rx_idx; /* index to next free Rx BD */
|
||||
int tx_idx; /* index to next free Tx BD */
|
||||
void *rxbd; /* pointer to next free Rx BD */
|
||||
void *txbd; /* pointer to next free Tx BD */
|
||||
int tx_space; /* number of Tx bytes left */
|
||||
unsigned char *tx_buf; /* pointer to free Tx area */
|
||||
i2c_ecb_t err_cb; /* error callback function */
|
||||
void *cb_data; /* private data to be passed */
|
||||
} i2c_state_t;
|
||||
|
||||
/* flags for i2c_send() and i2c_receive() */
|
||||
#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
|
||||
#define I2CF_START_COND 0x02 /* tx: generate start condition */
|
||||
#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
|
||||
|
||||
/* return codes */
|
||||
#define I2CERR_NO_BUFFERS 1 /* no more BDs or buffer space */
|
||||
#define I2CERR_MSG_TOO_LONG 2 /* tried to send/receive to much data */
|
||||
#define I2CERR_TIMEOUT 3 /* timeout in i2c_doio() */
|
||||
#define I2CERR_QUEUE_EMPTY 4 /* i2c_doio called without send/rcv */
|
||||
#define I2CERR_IO_ERROR 5 /* had an error during comms */
|
||||
|
||||
/* error callback flags */
|
||||
#define I2CECB_RX_ERR 0x10 /* this is a receive error */
|
||||
#define I2CECB_RX_OV 0x02 /* receive overrun error */
|
||||
#define I2CECB_RX_MASK 0x0f /* mask for error bits */
|
||||
#define I2CECB_TX_ERR 0x20 /* this is a transmit error */
|
||||
#define I2CECB_TX_CL 0x01 /* transmit collision error */
|
||||
#define I2CECB_TX_UN 0x02 /* transmit underflow error */
|
||||
#define I2CECB_TX_NAK 0x04 /* transmit no ack error */
|
||||
#define I2CECB_TX_MASK 0x0f /* mask for error bits */
|
||||
#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
|
||||
|
||||
#define ERROR_I2C_NONE 0
|
||||
#define ERROR_I2C_LENGTH 1
|
||||
|
||||
#define I2C_WRITE_BIT 0x00
|
||||
#define I2C_READ_BIT 0x01
|
||||
|
||||
#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
|
||||
|
||||
|
||||
#define NUM_RX_BDS 4
|
||||
#define NUM_TX_BDS 4
|
||||
#define MAX_TX_SPACE 256
|
||||
|
||||
typedef struct I2C_BD {
|
||||
unsigned short status;
|
||||
unsigned short length;
|
||||
unsigned char *addr;
|
||||
} I2C_BD;
|
||||
|
||||
#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
|
||||
|
||||
#define BD_I2C_TX_CL 0x0001 /* collision error */
|
||||
#define BD_I2C_TX_UN 0x0002 /* underflow error */
|
||||
#define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
|
||||
#define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
|
||||
|
||||
#define BD_I2C_RX_ERR BD_SC_OV
|
||||
|
||||
/*
|
||||
* Returns the best value of I2BRG to meet desired clock speed of I2C with
|
||||
* input parameters (clock speed, filter, and predivider value).
|
||||
* It returns computer speed value and the difference between it and desired
|
||||
* speed.
|
||||
*/
|
||||
static inline int
|
||||
i2c_roundrate(int hz, int speed, int filter, int modval,
|
||||
int *brgval, int *totspeed)
|
||||
{
|
||||
int moddiv = 1 << (5 - (modval & 3)), brgdiv, div;
|
||||
|
||||
debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
|
||||
hz, speed, filter, modval);
|
||||
|
||||
div = moddiv * speed;
|
||||
brgdiv = (hz + div - 1) / div;
|
||||
|
||||
debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv);
|
||||
|
||||
*brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter);
|
||||
|
||||
if ((*brgval < 0) || (*brgval > 255)) {
|
||||
debug("\t\trejected brgval=%d\n", *brgval);
|
||||
return -1;
|
||||
}
|
||||
|
||||
brgdiv = 2 * (*brgval + 3 + (2 * filter));
|
||||
div = moddiv * brgdiv;
|
||||
*totspeed = hz / div;
|
||||
|
||||
debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Sets the I2C clock predivider and divider to meet required clock speed.
|
||||
*/
|
||||
static int i2c_setrate(int hz, int speed)
|
||||
{
|
||||
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
|
||||
int brgval,
|
||||
modval, /* 0-3 */
|
||||
bestspeed_diff = speed,
|
||||
bestspeed_brgval = 0,
|
||||
bestspeed_modval = 0,
|
||||
bestspeed_filter = 0,
|
||||
totspeed,
|
||||
filter = 0; /* Use this fixed value */
|
||||
|
||||
for (modval = 0; modval < 4; modval++) {
|
||||
if (i2c_roundrate(hz, speed, filter, modval, &brgval, &totspeed)
|
||||
== 0) {
|
||||
int diff = speed - totspeed;
|
||||
|
||||
if ((diff >= 0) && (diff < bestspeed_diff)) {
|
||||
bestspeed_diff = diff;
|
||||
bestspeed_modval = modval;
|
||||
bestspeed_brgval = brgval;
|
||||
bestspeed_filter = filter;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
debug("[I2C] Best is:\n");
|
||||
debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
|
||||
hz, speed, bestspeed_filter, bestspeed_modval, bestspeed_brgval,
|
||||
bestspeed_diff);
|
||||
|
||||
i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) |
|
||||
(bestspeed_filter << 3);
|
||||
i2c->i2c_i2brg = bestspeed_brgval & 0xff;
|
||||
|
||||
debug("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod,
|
||||
i2c->i2c_i2brg);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void i2c_init(int speed, int slaveadd)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
|
||||
volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
|
||||
volatile iic_t *iip;
|
||||
ulong rbase, tbase;
|
||||
volatile I2C_BD *rxbd, *txbd;
|
||||
uint dpaddr;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_INIT_BOARD
|
||||
/*
|
||||
* call board specific i2c bus reset routine before accessing the
|
||||
* environment, which might be in a chip on that bus. For details
|
||||
* about this problem see doc/I2C_Edge_Conditions.
|
||||
*/
|
||||
i2c_init_board();
|
||||
#endif
|
||||
|
||||
dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)];
|
||||
if (dpaddr == 0) {
|
||||
/* need to allocate dual port ram */
|
||||
dpaddr = m8260_cpm_dpalloc(64 +
|
||||
(NUM_RX_BDS * sizeof(I2C_BD)) +
|
||||
(NUM_TX_BDS * sizeof(I2C_BD)) +
|
||||
MAX_TX_SPACE, 64);
|
||||
immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)] =
|
||||
dpaddr;
|
||||
}
|
||||
|
||||
/*
|
||||
* initialise data in dual port ram:
|
||||
*
|
||||
* dpaddr -> parameter ram (64 bytes)
|
||||
* rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
|
||||
* tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
|
||||
* tx buffer (MAX_TX_SPACE bytes)
|
||||
*/
|
||||
|
||||
iip = (iic_t *)&immap->im_dprambase[dpaddr];
|
||||
memset((void *)iip, 0, sizeof(iic_t));
|
||||
|
||||
rbase = dpaddr + 64;
|
||||
tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
|
||||
|
||||
/* Disable interrupts */
|
||||
i2c->i2c_i2mod = 0x00;
|
||||
i2c->i2c_i2cmr = 0x00;
|
||||
i2c->i2c_i2cer = 0xff;
|
||||
i2c->i2c_i2add = slaveadd;
|
||||
|
||||
/*
|
||||
* Set the I2C BRG Clock division factor from desired i2c rate
|
||||
* and current CPU rate (we assume sccr dfbgr field is 0;
|
||||
* divide BRGCLK by 1)
|
||||
*/
|
||||
debug("[I2C] Setting rate...\n");
|
||||
i2c_setrate(gd->arch.brg_clk, CONFIG_SYS_I2C_SPEED);
|
||||
|
||||
/* Set I2C controller in master mode */
|
||||
i2c->i2c_i2com = 0x01;
|
||||
|
||||
/* Initialize Tx/Rx parameters */
|
||||
iip->iic_rbase = rbase;
|
||||
iip->iic_tbase = tbase;
|
||||
rxbd = (I2C_BD *)((unsigned char *) &immap->
|
||||
im_dprambase[iip->iic_rbase]);
|
||||
txbd = (I2C_BD *)((unsigned char *) &immap->
|
||||
im_dprambase[iip->iic_tbase]);
|
||||
|
||||
debug("[I2C] rbase = %04x\n", iip->iic_rbase);
|
||||
debug("[I2C] tbase = %04x\n", iip->iic_tbase);
|
||||
debug("[I2C] rxbd = %08x\n", (int) rxbd);
|
||||
debug("[I2C] txbd = %08x\n", (int) txbd);
|
||||
|
||||
/* Set big endian byte order */
|
||||
iip->iic_tfcr = 0x10;
|
||||
iip->iic_rfcr = 0x10;
|
||||
|
||||
/* Set maximum receive size. */
|
||||
iip->iic_mrblr = I2C_RXTX_LEN;
|
||||
|
||||
cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE,
|
||||
CPM_CR_I2C_SBLOCK,
|
||||
0x00, CPM_CR_INIT_TRX) | CPM_CR_FLG;
|
||||
do {
|
||||
__asm__ __volatile__("eieio");
|
||||
} while (cp->cp_cpcr & CPM_CR_FLG);
|
||||
|
||||
/* Clear events and interrupts */
|
||||
i2c->i2c_i2cer = 0xff;
|
||||
i2c->i2c_i2cmr = 0x00;
|
||||
}
|
||||
|
||||
static
|
||||
void i2c_newio(i2c_state_t *state)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile iic_t *iip;
|
||||
uint dpaddr;
|
||||
|
||||
debug("[I2C] i2c_newio\n");
|
||||
|
||||
dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)];
|
||||
iip = (iic_t *)&immap->im_dprambase[dpaddr];
|
||||
state->rx_idx = 0;
|
||||
state->tx_idx = 0;
|
||||
state->rxbd = (void *)&immap->im_dprambase[iip->iic_rbase];
|
||||
state->txbd = (void *)&immap->im_dprambase[iip->iic_tbase];
|
||||
state->tx_space = MAX_TX_SPACE;
|
||||
state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
|
||||
state->err_cb = NULL;
|
||||
state->cb_data = NULL;
|
||||
|
||||
debug("[I2C] rxbd = %08x\n", (int)state->rxbd);
|
||||
debug("[I2C] txbd = %08x\n", (int)state->txbd);
|
||||
debug("[I2C] tx_buf = %08x\n", (int)state->tx_buf);
|
||||
|
||||
/* clear the buffer memory */
|
||||
memset((char *) state->tx_buf, 0, MAX_TX_SPACE);
|
||||
}
|
||||
|
||||
static
|
||||
int i2c_send(i2c_state_t *state,
|
||||
unsigned char address,
|
||||
unsigned char secondary_address,
|
||||
unsigned int flags, unsigned short size, unsigned char *dataout)
|
||||
{
|
||||
volatile I2C_BD *txbd;
|
||||
int i, j;
|
||||
|
||||
debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
|
||||
address, secondary_address, flags, size);
|
||||
|
||||
/* trying to send message larger than BD */
|
||||
if (size > I2C_RXTX_LEN)
|
||||
return I2CERR_MSG_TOO_LONG;
|
||||
|
||||
/* no more free bds */
|
||||
if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
|
||||
return I2CERR_NO_BUFFERS;
|
||||
|
||||
txbd = (I2C_BD *)state->txbd;
|
||||
txbd->addr = state->tx_buf;
|
||||
|
||||
debug("[I2C] txbd = %08x\n", (int) txbd);
|
||||
|
||||
if (flags & I2CF_START_COND) {
|
||||
debug("[I2C] Formatting addresses...\n");
|
||||
if (flags & I2CF_ENABLE_SECONDARY) {
|
||||
/* Length of message plus dest addresses */
|
||||
txbd->length = size + 2;
|
||||
txbd->addr[0] = address << 1;
|
||||
txbd->addr[1] = secondary_address;
|
||||
i = 2;
|
||||
} else {
|
||||
/* Length of message plus dest address */
|
||||
txbd->length = size + 1;
|
||||
/* Write destination address to BD */
|
||||
txbd->addr[0] = address << 1;
|
||||
i = 1;
|
||||
}
|
||||
} else {
|
||||
txbd->length = size; /* Length of message */
|
||||
i = 0;
|
||||
}
|
||||
|
||||
/* set up txbd */
|
||||
txbd->status = BD_SC_READY;
|
||||
if (flags & I2CF_START_COND)
|
||||
txbd->status |= BD_I2C_TX_START;
|
||||
if (flags & I2CF_STOP_COND)
|
||||
txbd->status |= BD_SC_LAST | BD_SC_WRAP;
|
||||
|
||||
/* Copy data to send into buffer */
|
||||
debug("[I2C] copy data...\n");
|
||||
for (j = 0; j < size; i++, j++)
|
||||
txbd->addr[i] = dataout[j];
|
||||
|
||||
debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
|
||||
txbd->length, txbd->status, txbd->addr[0], txbd->addr[1]);
|
||||
|
||||
/* advance state */
|
||||
state->tx_buf += txbd->length;
|
||||
state->tx_space -= txbd->length;
|
||||
state->tx_idx++;
|
||||
state->txbd = (void *) (txbd + 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static
|
||||
int i2c_receive(i2c_state_t *state,
|
||||
unsigned char address,
|
||||
unsigned char secondary_address,
|
||||
unsigned int flags,
|
||||
unsigned short size_to_expect, unsigned char *datain)
|
||||
{
|
||||
volatile I2C_BD *rxbd, *txbd;
|
||||
|
||||
debug("[I2C] i2c_receive %02d %02d %02d\n", address,
|
||||
secondary_address, flags);
|
||||
|
||||
/* Expected to receive too much */
|
||||
if (size_to_expect > I2C_RXTX_LEN)
|
||||
return I2CERR_MSG_TOO_LONG;
|
||||
|
||||
/* no more free bds */
|
||||
if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
|
||||
|| state->tx_space < 2)
|
||||
return I2CERR_NO_BUFFERS;
|
||||
|
||||
rxbd = (I2C_BD *) state->rxbd;
|
||||
txbd = (I2C_BD *) state->txbd;
|
||||
|
||||
debug("[I2C] rxbd = %08x\n", (int) rxbd);
|
||||
debug("[I2C] txbd = %08x\n", (int) txbd);
|
||||
|
||||
txbd->addr = state->tx_buf;
|
||||
|
||||
/* set up TXBD for destination address */
|
||||
if (flags & I2CF_ENABLE_SECONDARY) {
|
||||
txbd->length = 2;
|
||||
txbd->addr[0] = address << 1; /* Write data */
|
||||
txbd->addr[1] = secondary_address; /* Internal address */
|
||||
txbd->status = BD_SC_READY;
|
||||
} else {
|
||||
txbd->length = 1 + size_to_expect;
|
||||
txbd->addr[0] = (address << 1) | 0x01;
|
||||
txbd->status = BD_SC_READY;
|
||||
memset(&txbd->addr[1], 0, txbd->length);
|
||||
}
|
||||
|
||||
/* set up rxbd for reception */
|
||||
rxbd->status = BD_SC_EMPTY;
|
||||
rxbd->length = size_to_expect;
|
||||
rxbd->addr = datain;
|
||||
|
||||
txbd->status |= BD_I2C_TX_START;
|
||||
if (flags & I2CF_STOP_COND) {
|
||||
txbd->status |= BD_SC_LAST | BD_SC_WRAP;
|
||||
rxbd->status |= BD_SC_WRAP;
|
||||
}
|
||||
|
||||
debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
|
||||
txbd->length, txbd->status, txbd->addr[0], txbd->addr[1]);
|
||||
debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
|
||||
rxbd->length, rxbd->status, rxbd->addr[0], rxbd->addr[1]);
|
||||
|
||||
/* advance state */
|
||||
state->tx_buf += txbd->length;
|
||||
state->tx_space -= txbd->length;
|
||||
state->tx_idx++;
|
||||
state->txbd = (void *) (txbd + 1);
|
||||
state->rx_idx++;
|
||||
state->rxbd = (void *) (rxbd + 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static
|
||||
int i2c_doio(i2c_state_t *state)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile iic_t *iip;
|
||||
volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
|
||||
volatile I2C_BD *txbd, *rxbd;
|
||||
int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
|
||||
uint dpaddr;
|
||||
|
||||
debug("[I2C] i2c_doio\n");
|
||||
|
||||
if (state->tx_idx <= 0 && state->rx_idx <= 0) {
|
||||
debug("[I2C] No I/O is queued\n");
|
||||
return I2CERR_QUEUE_EMPTY;
|
||||
}
|
||||
|
||||
dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)];
|
||||
iip = (iic_t *)&immap->im_dprambase[dpaddr];
|
||||
iip->iic_rbptr = iip->iic_rbase;
|
||||
iip->iic_tbptr = iip->iic_tbase;
|
||||
|
||||
/* Enable I2C */
|
||||
debug("[I2C] Enabling I2C...\n");
|
||||
i2c->i2c_i2mod |= 0x01;
|
||||
|
||||
/* Begin transmission */
|
||||
i2c->i2c_i2com |= 0x80;
|
||||
|
||||
/* Loop until transmit & receive completed */
|
||||
|
||||
n = state->tx_idx;
|
||||
|
||||
if (n > 0) {
|
||||
|
||||
txbd = ((I2C_BD *) state->txbd) - n;
|
||||
for (i = 0; i < n; i++) {
|
||||
txtimeo += TOUT_LOOP * txbd->length;
|
||||
txbd++;
|
||||
}
|
||||
|
||||
txbd--; /* wait until last in list is done */
|
||||
|
||||
debug("[I2C] Transmitting...(txbd=0x%08lx)\n",
|
||||
(ulong) txbd);
|
||||
|
||||
udelay(START_DELAY_US); /* give it time to start */
|
||||
while ((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) {
|
||||
udelay(DELAY_US);
|
||||
if (ctrlc())
|
||||
return -1;
|
||||
__asm__ __volatile__("eieio");
|
||||
}
|
||||
}
|
||||
|
||||
n = state->rx_idx;
|
||||
|
||||
if (txcnt < txtimeo && n > 0) {
|
||||
|
||||
rxbd = ((I2C_BD *) state->rxbd) - n;
|
||||
for (i = 0; i < n; i++) {
|
||||
rxtimeo += TOUT_LOOP * rxbd->length;
|
||||
rxbd++;
|
||||
}
|
||||
|
||||
rxbd--; /* wait until last in list is done */
|
||||
|
||||
debug("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong) rxbd);
|
||||
|
||||
udelay(START_DELAY_US); /* give it time to start */
|
||||
while ((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) {
|
||||
udelay(DELAY_US);
|
||||
if (ctrlc())
|
||||
return -1;
|
||||
__asm__ __volatile__("eieio");
|
||||
}
|
||||
}
|
||||
|
||||
/* Turn off I2C */
|
||||
i2c->i2c_i2mod &= ~0x01;
|
||||
|
||||
n = state->tx_idx;
|
||||
|
||||
if (n > 0) {
|
||||
for (i = 0; i < n; i++) {
|
||||
txbd = ((I2C_BD *) state->txbd) - (n - i);
|
||||
b = txbd->status & BD_I2C_TX_ERR;
|
||||
if (b != 0) {
|
||||
if (state->err_cb != NULL)
|
||||
(*state->err_cb) (I2CECB_TX_ERR | b,
|
||||
i, state->cb_data);
|
||||
if (rc == 0)
|
||||
rc = I2CERR_IO_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
n = state->rx_idx;
|
||||
|
||||
if (n > 0) {
|
||||
for (i = 0; i < n; i++) {
|
||||
rxbd = ((I2C_BD *) state->rxbd) - (n - i);
|
||||
b = rxbd->status & BD_I2C_RX_ERR;
|
||||
if (b != 0) {
|
||||
if (state->err_cb != NULL)
|
||||
(*state->err_cb) (I2CECB_RX_ERR | b,
|
||||
i, state->cb_data);
|
||||
if (rc == 0)
|
||||
rc = I2CERR_IO_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if ((txtimeo > 0 && txcnt >= txtimeo) ||
|
||||
(rxtimeo > 0 && rxcnt >= rxtimeo)) {
|
||||
if (state->err_cb != NULL)
|
||||
(*state->err_cb) (I2CECB_TIMEOUT, -1, state->cb_data);
|
||||
if (rc == 0)
|
||||
rc = I2CERR_TIMEOUT;
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void i2c_probe_callback(int flags, int xnum, void *data)
|
||||
{
|
||||
/*
|
||||
* the only acceptable errors are a transmit NAK or a receive
|
||||
* overrun - tx NAK means the device does not exist, rx OV
|
||||
* means the device must have responded to the slave address
|
||||
* even though the transfer failed
|
||||
*/
|
||||
if (flags == (I2CECB_TX_ERR | I2CECB_TX_NAK))
|
||||
*(int *) data |= 1;
|
||||
if (flags == (I2CECB_RX_ERR | I2CECB_RX_OV))
|
||||
*(int *) data |= 2;
|
||||
}
|
||||
|
||||
int i2c_probe(uchar chip)
|
||||
{
|
||||
i2c_state_t state;
|
||||
int rc, err_flag;
|
||||
uchar buf[1];
|
||||
|
||||
i2c_newio(&state);
|
||||
|
||||
state.err_cb = i2c_probe_callback;
|
||||
state.cb_data = (void *) &err_flag;
|
||||
err_flag = 0;
|
||||
|
||||
rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1,
|
||||
buf);
|
||||
|
||||
if (rc != 0)
|
||||
return rc; /* probe failed */
|
||||
|
||||
rc = i2c_doio(&state);
|
||||
|
||||
if (rc == 0)
|
||||
return 0; /* device exists - read succeeded */
|
||||
|
||||
if (rc == I2CERR_TIMEOUT)
|
||||
return -1; /* device does not exist - timeout */
|
||||
|
||||
if (rc != I2CERR_IO_ERROR || err_flag == 0)
|
||||
return rc; /* probe failed */
|
||||
|
||||
if (err_flag & 1)
|
||||
return -1; /* device does not exist - had transmit NAK */
|
||||
|
||||
return 0; /* device exists - had receive overrun */
|
||||
}
|
||||
|
||||
|
||||
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||
{
|
||||
i2c_state_t state;
|
||||
uchar xaddr[4];
|
||||
int rc;
|
||||
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
||||
/*
|
||||
* EEPROM chips that implement "address overflow" are ones
|
||||
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
|
||||
* and the extra bits end up in the "chip address" bit slots.
|
||||
* This makes a 24WC08 (1Kbyte) chip look like four 256 byte
|
||||
* chips.
|
||||
*
|
||||
* Note that we consider the length of the address field to still
|
||||
* be one byte because the extra address bits are hidden in the
|
||||
* chip address.
|
||||
*/
|
||||
chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
#endif
|
||||
|
||||
i2c_newio(&state);
|
||||
|
||||
rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
|
||||
&xaddr[4 - alen]);
|
||||
if (rc != 0) {
|
||||
printf("i2c_read: i2c_send failed (%d)\n", rc);
|
||||
return 1;
|
||||
}
|
||||
|
||||
rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
|
||||
if (rc != 0) {
|
||||
printf("i2c_read: i2c_receive failed (%d)\n", rc);
|
||||
return 1;
|
||||
}
|
||||
|
||||
rc = i2c_doio(&state);
|
||||
if (rc != 0) {
|
||||
printf("i2c_read: i2c_doio failed (%d)\n", rc);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||
{
|
||||
i2c_state_t state;
|
||||
uchar xaddr[4];
|
||||
int rc;
|
||||
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
||||
/*
|
||||
* EEPROM chips that implement "address overflow" are ones
|
||||
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
|
||||
* and the extra bits end up in the "chip address" bit slots.
|
||||
* This makes a 24WC08 (1Kbyte) chip look like four 256 byte
|
||||
* chips.
|
||||
*
|
||||
* Note that we consider the length of the address field to still
|
||||
* be one byte because the extra address bits are hidden in the
|
||||
* chip address.
|
||||
*/
|
||||
chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
#endif
|
||||
|
||||
i2c_newio(&state);
|
||||
|
||||
rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
|
||||
&xaddr[4 - alen]);
|
||||
if (rc != 0) {
|
||||
printf("i2c_write: first i2c_send failed (%d)\n", rc);
|
||||
return 1;
|
||||
}
|
||||
|
||||
rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
|
||||
if (rc != 0) {
|
||||
printf("i2c_write: second i2c_send failed (%d)\n", rc);
|
||||
return 1;
|
||||
}
|
||||
|
||||
rc = i2c_doio(&state);
|
||||
if (rc != 0) {
|
||||
printf("i2c_write: i2c_doio failed (%d)\n", rc);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_I2C_MULTI_BUS)
|
||||
/*
|
||||
* Functions for multiple I2C bus handling
|
||||
*/
|
||||
unsigned int i2c_get_bus_num(void)
|
||||
{
|
||||
return i2c_bus_num;
|
||||
}
|
||||
|
||||
int i2c_set_bus_num(unsigned int bus)
|
||||
{
|
||||
if (bus >= CONFIG_SYS_MAX_I2C_BUS)
|
||||
return -1;
|
||||
i2c_bus_num = bus;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_I2C_MULTI_BUS */
|
||||
#endif /* CONFIG_HARD_I2C */
|
||||
@ -14,7 +14,6 @@ obj-y += cpu.o
|
||||
obj-y += cpu_init.o
|
||||
obj-y += fec.o
|
||||
obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
||||
obj-y += i2c.o
|
||||
obj-y += interrupts.o
|
||||
obj-y += scc.o
|
||||
obj-y += serial.o
|
||||
|
||||
@ -1,672 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2000
|
||||
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
|
||||
*
|
||||
* (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Back ported to the 8xx platform (from the 8260 platform) by
|
||||
* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <console.h>
|
||||
|
||||
#ifdef CONFIG_HARD_I2C
|
||||
|
||||
#include <commproc.h>
|
||||
#include <i2c.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
|
||||
#define TOUT_LOOP 1000000
|
||||
|
||||
#define NUM_RX_BDS 4
|
||||
#define NUM_TX_BDS 4
|
||||
#define MAX_TX_SPACE 256
|
||||
#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
|
||||
|
||||
typedef struct I2C_BD {
|
||||
unsigned short status;
|
||||
unsigned short length;
|
||||
unsigned char *addr;
|
||||
} I2C_BD;
|
||||
|
||||
#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
|
||||
|
||||
#define BD_I2C_TX_CL 0x0001 /* collision error */
|
||||
#define BD_I2C_TX_UN 0x0002 /* underflow error */
|
||||
#define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
|
||||
#define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
|
||||
|
||||
#define BD_I2C_RX_ERR BD_SC_OV
|
||||
|
||||
typedef void (*i2c_ecb_t) (int, int); /* error callback function */
|
||||
|
||||
/* This structure keeps track of the bd and buffer space usage. */
|
||||
typedef struct i2c_state {
|
||||
int rx_idx; /* index to next free Rx BD */
|
||||
int tx_idx; /* index to next free Tx BD */
|
||||
void *rxbd; /* pointer to next free Rx BD */
|
||||
void *txbd; /* pointer to next free Tx BD */
|
||||
int tx_space; /* number of Tx bytes left */
|
||||
unsigned char *tx_buf; /* pointer to free Tx area */
|
||||
i2c_ecb_t err_cb; /* error callback function */
|
||||
} i2c_state_t;
|
||||
|
||||
|
||||
/* flags for i2c_send() and i2c_receive() */
|
||||
#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
|
||||
#define I2CF_START_COND 0x02 /* tx: generate start condition */
|
||||
#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
|
||||
|
||||
/* return codes */
|
||||
#define I2CERR_NO_BUFFERS 0x01 /* no more BDs or buffer space */
|
||||
#define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */
|
||||
#define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */
|
||||
#define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */
|
||||
|
||||
/* error callback flags */
|
||||
#define I2CECB_RX_ERR 0x10 /* this is a receive error */
|
||||
#define I2CECB_RX_ERR_OV 0x02 /* receive overrun error */
|
||||
#define I2CECB_RX_MASK 0x0f /* mask for error bits */
|
||||
#define I2CECB_TX_ERR 0x20 /* this is a transmit error */
|
||||
#define I2CECB_TX_CL 0x01 /* transmit collision error */
|
||||
#define I2CECB_TX_UN 0x02 /* transmit underflow error */
|
||||
#define I2CECB_TX_NAK 0x04 /* transmit no ack error */
|
||||
#define I2CECB_TX_MASK 0x0f /* mask for error bits */
|
||||
#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
|
||||
|
||||
/*
|
||||
* Returns the best value of I2BRG to meet desired clock speed of I2C with
|
||||
* input parameters (clock speed, filter, and predivider value).
|
||||
* It returns computer speed value and the difference between it and desired
|
||||
* speed.
|
||||
*/
|
||||
static inline int
|
||||
i2c_roundrate(int hz, int speed, int filter, int modval,
|
||||
int *brgval, int *totspeed)
|
||||
{
|
||||
int moddiv = 1 << (5 - (modval & 3)), brgdiv, div;
|
||||
|
||||
debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
|
||||
hz, speed, filter, modval);
|
||||
|
||||
div = moddiv * speed;
|
||||
brgdiv = (hz + div - 1) / div;
|
||||
|
||||
debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv);
|
||||
|
||||
*brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter);
|
||||
|
||||
if ((*brgval < 0) || (*brgval > 255)) {
|
||||
debug("\t\trejected brgval=%d\n", *brgval);
|
||||
return -1;
|
||||
}
|
||||
|
||||
brgdiv = 2 * (*brgval + 3 + (2 * filter));
|
||||
div = moddiv * brgdiv;
|
||||
*totspeed = hz / div;
|
||||
|
||||
debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Sets the I2C clock predivider and divider to meet required clock speed.
|
||||
*/
|
||||
static int i2c_setrate(int hz, int speed)
|
||||
{
|
||||
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c;
|
||||
int brgval,
|
||||
modval, /* 0-3 */
|
||||
bestspeed_diff = speed,
|
||||
bestspeed_brgval = 0,
|
||||
bestspeed_modval = 0,
|
||||
bestspeed_filter = 0,
|
||||
totspeed,
|
||||
filter = 0; /* Use this fixed value */
|
||||
|
||||
for (modval = 0; modval < 4; modval++) {
|
||||
if (i2c_roundrate
|
||||
(hz, speed, filter, modval, &brgval, &totspeed) == 0) {
|
||||
int diff = speed - totspeed;
|
||||
|
||||
if ((diff >= 0) && (diff < bestspeed_diff)) {
|
||||
bestspeed_diff = diff;
|
||||
bestspeed_modval = modval;
|
||||
bestspeed_brgval = brgval;
|
||||
bestspeed_filter = filter;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
debug("[I2C] Best is:\n");
|
||||
debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
|
||||
hz,
|
||||
speed,
|
||||
bestspeed_filter,
|
||||
bestspeed_modval,
|
||||
bestspeed_brgval,
|
||||
bestspeed_diff);
|
||||
|
||||
i2c->i2c_i2mod |=
|
||||
((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
|
||||
i2c->i2c_i2brg = bestspeed_brgval & 0xff;
|
||||
|
||||
debug("[I2C] i2mod=%08x i2brg=%08x\n",
|
||||
i2c->i2c_i2mod,
|
||||
i2c->i2c_i2brg);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void i2c_init(int speed, int slaveaddr)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
|
||||
volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
|
||||
volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
|
||||
ulong rbase, tbase;
|
||||
volatile I2C_BD *rxbd, *txbd;
|
||||
uint dpaddr;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_INIT_BOARD
|
||||
/* call board specific i2c bus reset routine before accessing the */
|
||||
/* environment, which might be in a chip on that bus. For details */
|
||||
/* about this problem see doc/I2C_Edge_Conditions. */
|
||||
i2c_init_board();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_UCODE_PATCH
|
||||
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
|
||||
#else
|
||||
/* Disable relocation */
|
||||
iip->iic_rpbase = 0;
|
||||
#endif
|
||||
|
||||
dpaddr = CPM_I2C_BASE;
|
||||
|
||||
/*
|
||||
* initialise data in dual port ram:
|
||||
*
|
||||
* dpaddr->rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
|
||||
* tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
|
||||
* tx buffer (MAX_TX_SPACE bytes)
|
||||
*/
|
||||
|
||||
rbase = dpaddr;
|
||||
tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
|
||||
|
||||
/* Initialize Port B I2C pins. */
|
||||
cp->cp_pbpar |= 0x00000030;
|
||||
cp->cp_pbdir |= 0x00000030;
|
||||
cp->cp_pbodr |= 0x00000030;
|
||||
|
||||
/* Disable interrupts */
|
||||
i2c->i2c_i2mod = 0x00;
|
||||
i2c->i2c_i2cmr = 0x00;
|
||||
i2c->i2c_i2cer = 0xff;
|
||||
i2c->i2c_i2add = slaveaddr;
|
||||
|
||||
/*
|
||||
* Set the I2C BRG Clock division factor from desired i2c rate
|
||||
* and current CPU rate (we assume sccr dfbgr field is 0;
|
||||
* divide BRGCLK by 1)
|
||||
*/
|
||||
debug("[I2C] Setting rate...\n");
|
||||
i2c_setrate(gd->cpu_clk, CONFIG_SYS_I2C_SPEED);
|
||||
|
||||
/* Set I2C controller in master mode */
|
||||
i2c->i2c_i2com = 0x01;
|
||||
|
||||
/* Set SDMA bus arbitration level to 5 (SDCR) */
|
||||
immap->im_siu_conf.sc_sdcr = 0x0001;
|
||||
|
||||
/* Initialize Tx/Rx parameters */
|
||||
iip->iic_rbase = rbase;
|
||||
iip->iic_tbase = tbase;
|
||||
rxbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_rbase]);
|
||||
txbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_tbase]);
|
||||
|
||||
debug("[I2C] rbase = %04x\n", iip->iic_rbase);
|
||||
debug("[I2C] tbase = %04x\n", iip->iic_tbase);
|
||||
debug("[I2C] rxbd = %08x\n", (int)rxbd);
|
||||
debug("[I2C] txbd = %08x\n", (int)txbd);
|
||||
|
||||
/* Set big endian byte order */
|
||||
iip->iic_tfcr = 0x10;
|
||||
iip->iic_rfcr = 0x10;
|
||||
|
||||
/* Set maximum receive size. */
|
||||
iip->iic_mrblr = I2C_RXTX_LEN;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_UCODE_PATCH
|
||||
/*
|
||||
* Initialize required parameters if using microcode patch.
|
||||
*/
|
||||
iip->iic_rbptr = iip->iic_rbase;
|
||||
iip->iic_tbptr = iip->iic_tbase;
|
||||
iip->iic_rstate = 0;
|
||||
iip->iic_tstate = 0;
|
||||
#else
|
||||
cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
|
||||
do {
|
||||
__asm__ __volatile__("eieio");
|
||||
} while (cp->cp_cpcr & CPM_CR_FLG);
|
||||
#endif
|
||||
|
||||
/* Clear events and interrupts */
|
||||
i2c->i2c_i2cer = 0xff;
|
||||
i2c->i2c_i2cmr = 0x00;
|
||||
}
|
||||
|
||||
static void i2c_newio(i2c_state_t *state)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
|
||||
volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
|
||||
|
||||
debug("[I2C] i2c_newio\n");
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_UCODE_PATCH
|
||||
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
|
||||
#endif
|
||||
state->rx_idx = 0;
|
||||
state->tx_idx = 0;
|
||||
state->rxbd = (void *)&cp->cp_dpmem[iip->iic_rbase];
|
||||
state->txbd = (void *)&cp->cp_dpmem[iip->iic_tbase];
|
||||
state->tx_space = MAX_TX_SPACE;
|
||||
state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
|
||||
state->err_cb = NULL;
|
||||
|
||||
debug("[I2C] rxbd = %08x\n", (int)state->rxbd);
|
||||
debug("[I2C] txbd = %08x\n", (int)state->txbd);
|
||||
debug("[I2C] tx_buf = %08x\n", (int)state->tx_buf);
|
||||
|
||||
/* clear the buffer memory */
|
||||
memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
|
||||
}
|
||||
|
||||
static int
|
||||
i2c_send(i2c_state_t *state,
|
||||
unsigned char address,
|
||||
unsigned char secondary_address,
|
||||
unsigned int flags, unsigned short size, unsigned char *dataout)
|
||||
{
|
||||
volatile I2C_BD *txbd;
|
||||
int i, j;
|
||||
|
||||
debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
|
||||
address, secondary_address, flags, size);
|
||||
|
||||
/* trying to send message larger than BD */
|
||||
if (size > I2C_RXTX_LEN)
|
||||
return I2CERR_MSG_TOO_LONG;
|
||||
|
||||
/* no more free bds */
|
||||
if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
|
||||
return I2CERR_NO_BUFFERS;
|
||||
|
||||
txbd = (I2C_BD *) state->txbd;
|
||||
txbd->addr = state->tx_buf;
|
||||
|
||||
debug("[I2C] txbd = %08x\n", (int)txbd);
|
||||
|
||||
if (flags & I2CF_START_COND) {
|
||||
debug("[I2C] Formatting addresses...\n");
|
||||
if (flags & I2CF_ENABLE_SECONDARY) {
|
||||
/* Length of msg + dest addr */
|
||||
txbd->length = size + 2;
|
||||
|
||||
txbd->addr[0] = address << 1;
|
||||
txbd->addr[1] = secondary_address;
|
||||
i = 2;
|
||||
} else {
|
||||
/* Length of msg + dest addr */
|
||||
txbd->length = size + 1;
|
||||
/* Write dest addr to BD */
|
||||
txbd->addr[0] = address << 1;
|
||||
i = 1;
|
||||
}
|
||||
} else {
|
||||
txbd->length = size; /* Length of message */
|
||||
i = 0;
|
||||
}
|
||||
|
||||
/* set up txbd */
|
||||
txbd->status = BD_SC_READY;
|
||||
if (flags & I2CF_START_COND)
|
||||
txbd->status |= BD_I2C_TX_START;
|
||||
if (flags & I2CF_STOP_COND)
|
||||
txbd->status |= BD_SC_LAST | BD_SC_WRAP;
|
||||
|
||||
/* Copy data to send into buffer */
|
||||
debug("[I2C] copy data...\n");
|
||||
for(j = 0; j < size; i++, j++)
|
||||
txbd->addr[i] = dataout[j];
|
||||
|
||||
debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
|
||||
txbd->length,
|
||||
txbd->status,
|
||||
txbd->addr[0],
|
||||
txbd->addr[1]);
|
||||
|
||||
/* advance state */
|
||||
state->tx_buf += txbd->length;
|
||||
state->tx_space -= txbd->length;
|
||||
state->tx_idx++;
|
||||
state->txbd = (void *) (txbd + 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
i2c_receive(i2c_state_t *state,
|
||||
unsigned char address,
|
||||
unsigned char secondary_address,
|
||||
unsigned int flags,
|
||||
unsigned short size_to_expect, unsigned char *datain)
|
||||
{
|
||||
volatile I2C_BD *rxbd, *txbd;
|
||||
|
||||
debug("[I2C] i2c_receive %02d %02d %02d\n",
|
||||
address, secondary_address, flags);
|
||||
|
||||
/* Expected to receive too much */
|
||||
if (size_to_expect > I2C_RXTX_LEN)
|
||||
return I2CERR_MSG_TOO_LONG;
|
||||
|
||||
/* no more free bds */
|
||||
if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
|
||||
|| state->tx_space < 2)
|
||||
return I2CERR_NO_BUFFERS;
|
||||
|
||||
rxbd = (I2C_BD *) state->rxbd;
|
||||
txbd = (I2C_BD *) state->txbd;
|
||||
|
||||
debug("[I2C] rxbd = %08x\n", (int)rxbd);
|
||||
debug("[I2C] txbd = %08x\n", (int)txbd);
|
||||
|
||||
txbd->addr = state->tx_buf;
|
||||
|
||||
/* set up TXBD for destination address */
|
||||
if (flags & I2CF_ENABLE_SECONDARY) {
|
||||
txbd->length = 2;
|
||||
txbd->addr[0] = address << 1; /* Write data */
|
||||
txbd->addr[1] = secondary_address; /* Internal address */
|
||||
txbd->status = BD_SC_READY;
|
||||
} else {
|
||||
txbd->length = 1 + size_to_expect;
|
||||
txbd->addr[0] = (address << 1) | 0x01;
|
||||
txbd->status = BD_SC_READY;
|
||||
memset(&txbd->addr[1], 0, txbd->length);
|
||||
}
|
||||
|
||||
/* set up rxbd for reception */
|
||||
rxbd->status = BD_SC_EMPTY;
|
||||
rxbd->length = size_to_expect;
|
||||
rxbd->addr = datain;
|
||||
|
||||
txbd->status |= BD_I2C_TX_START;
|
||||
if (flags & I2CF_STOP_COND) {
|
||||
txbd->status |= BD_SC_LAST | BD_SC_WRAP;
|
||||
rxbd->status |= BD_SC_WRAP;
|
||||
}
|
||||
|
||||
debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
|
||||
txbd->length,
|
||||
txbd->status,
|
||||
txbd->addr[0],
|
||||
txbd->addr[1]);
|
||||
debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
|
||||
rxbd->length,
|
||||
rxbd->status,
|
||||
rxbd->addr[0],
|
||||
rxbd->addr[1]);
|
||||
|
||||
/* advance state */
|
||||
state->tx_buf += txbd->length;
|
||||
state->tx_space -= txbd->length;
|
||||
state->tx_idx++;
|
||||
state->txbd = (void *) (txbd + 1);
|
||||
state->rx_idx++;
|
||||
state->rxbd = (void *) (rxbd + 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int i2c_doio(i2c_state_t *state)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
|
||||
volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
|
||||
volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
|
||||
volatile I2C_BD *txbd, *rxbd;
|
||||
volatile int j = 0;
|
||||
|
||||
debug("[I2C] i2c_doio\n");
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_UCODE_PATCH
|
||||
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
|
||||
#endif
|
||||
|
||||
if (state->tx_idx <= 0 && state->rx_idx <= 0) {
|
||||
debug("[I2C] No I/O is queued\n");
|
||||
return I2CERR_QUEUE_EMPTY;
|
||||
}
|
||||
|
||||
iip->iic_rbptr = iip->iic_rbase;
|
||||
iip->iic_tbptr = iip->iic_tbase;
|
||||
|
||||
/* Enable I2C */
|
||||
debug("[I2C] Enabling I2C...\n");
|
||||
i2c->i2c_i2mod |= 0x01;
|
||||
|
||||
/* Begin transmission */
|
||||
i2c->i2c_i2com |= 0x80;
|
||||
|
||||
/* Loop until transmit & receive completed */
|
||||
|
||||
if (state->tx_idx > 0) {
|
||||
txbd = ((I2C_BD*)state->txbd) - 1;
|
||||
|
||||
debug("[I2C] Transmitting...(txbd=0x%08lx)\n",
|
||||
(ulong)txbd);
|
||||
|
||||
while ((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
|
||||
if (ctrlc())
|
||||
return (-1);
|
||||
|
||||
__asm__ __volatile__("eieio");
|
||||
}
|
||||
}
|
||||
|
||||
if ((state->rx_idx > 0) && (j < TOUT_LOOP)) {
|
||||
rxbd = ((I2C_BD*)state->rxbd) - 1;
|
||||
|
||||
debug("[I2C] Receiving...(rxbd=0x%08lx)\n",
|
||||
(ulong)rxbd);
|
||||
|
||||
while ((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
|
||||
if (ctrlc())
|
||||
return (-1);
|
||||
|
||||
__asm__ __volatile__("eieio");
|
||||
}
|
||||
}
|
||||
|
||||
/* Turn off I2C */
|
||||
i2c->i2c_i2mod &= ~0x01;
|
||||
|
||||
if (state->err_cb != NULL) {
|
||||
int n, i, b;
|
||||
|
||||
/*
|
||||
* if we have an error callback function, look at the
|
||||
* error bits in the bd status and pass them back
|
||||
*/
|
||||
|
||||
if ((n = state->tx_idx) > 0) {
|
||||
for (i = 0; i < n; i++) {
|
||||
txbd = ((I2C_BD *) state->txbd) - (n - i);
|
||||
if ((b = txbd->status & BD_I2C_TX_ERR) != 0)
|
||||
(*state->err_cb) (I2CECB_TX_ERR | b,
|
||||
i);
|
||||
}
|
||||
}
|
||||
|
||||
if ((n = state->rx_idx) > 0) {
|
||||
for (i = 0; i < n; i++) {
|
||||
rxbd = ((I2C_BD *) state->rxbd) - (n - i);
|
||||
if ((b = rxbd->status & BD_I2C_RX_ERR) != 0)
|
||||
(*state->err_cb) (I2CECB_RX_ERR | b,
|
||||
i);
|
||||
}
|
||||
}
|
||||
|
||||
if (j >= TOUT_LOOP)
|
||||
(*state->err_cb) (I2CECB_TIMEOUT, 0);
|
||||
}
|
||||
|
||||
return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0;
|
||||
}
|
||||
|
||||
static int had_tx_nak;
|
||||
|
||||
static void i2c_test_callback(int flags, int xnum)
|
||||
{
|
||||
if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK))
|
||||
had_tx_nak = 1;
|
||||
}
|
||||
|
||||
int i2c_probe(uchar chip)
|
||||
{
|
||||
i2c_state_t state;
|
||||
int rc;
|
||||
uchar buf[1];
|
||||
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
|
||||
i2c_newio(&state);
|
||||
|
||||
state.err_cb = i2c_test_callback;
|
||||
had_tx_nak = 0;
|
||||
|
||||
rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1,
|
||||
buf);
|
||||
|
||||
if (rc != 0)
|
||||
return (rc);
|
||||
|
||||
rc = i2c_doio(&state);
|
||||
|
||||
if ((rc != 0) && (rc != I2CERR_TIMEOUT))
|
||||
return (rc);
|
||||
|
||||
return (had_tx_nak);
|
||||
}
|
||||
|
||||
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||
{
|
||||
i2c_state_t state;
|
||||
uchar xaddr[4];
|
||||
int rc;
|
||||
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
||||
/*
|
||||
* EEPROM chips that implement "address overflow" are ones like
|
||||
* Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
|
||||
* extra bits end up in the "chip address" bit slots. This makes
|
||||
* a 24WC08 (1Kbyte) chip look like four 256 byte chips.
|
||||
*
|
||||
* Note that we consider the length of the address field to still
|
||||
* be one byte because the extra address bits are hidden in the
|
||||
* chip address.
|
||||
*/
|
||||
chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
#endif
|
||||
|
||||
i2c_newio(&state);
|
||||
|
||||
rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
|
||||
&xaddr[4 - alen]);
|
||||
if (rc != 0) {
|
||||
printf("i2c_read: i2c_send failed (%d)\n", rc);
|
||||
return 1;
|
||||
}
|
||||
|
||||
rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
|
||||
if (rc != 0) {
|
||||
printf("i2c_read: i2c_receive failed (%d)\n", rc);
|
||||
return 1;
|
||||
}
|
||||
|
||||
rc = i2c_doio(&state);
|
||||
if (rc != 0) {
|
||||
printf("i2c_read: i2c_doio failed (%d)\n", rc);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||
{
|
||||
i2c_state_t state;
|
||||
uchar xaddr[4];
|
||||
int rc;
|
||||
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
||||
/*
|
||||
* EEPROM chips that implement "address overflow" are ones like
|
||||
* Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
|
||||
* extra bits end up in the "chip address" bit slots. This makes
|
||||
* a 24WC08 (1Kbyte) chip look like four 256 byte chips.
|
||||
*
|
||||
* Note that we consider the length of the address field to still
|
||||
* be one byte because the extra address bits are hidden in the
|
||||
* chip address.
|
||||
*/
|
||||
chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
#endif
|
||||
|
||||
i2c_newio(&state);
|
||||
|
||||
rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
|
||||
&xaddr[4 - alen]);
|
||||
if (rc != 0) {
|
||||
printf("i2c_write: first i2c_send failed (%d)\n", rc);
|
||||
return 1;
|
||||
}
|
||||
|
||||
rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
|
||||
if (rc != 0) {
|
||||
printf("i2c_write: second i2c_send failed (%d)\n", rc);
|
||||
return 1;
|
||||
}
|
||||
|
||||
rc = i2c_doio(&state);
|
||||
if (rc != 0) {
|
||||
printf("i2c_write: i2c_doio failed (%d)\n", rc);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_HARD_I2C */
|
||||
@ -156,17 +156,7 @@ int board_init(void)
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
u8 mac[6];
|
||||
|
||||
/* Read Mac Address and set*/
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
i2c_set_bus_num(CONFIG_SYS_I2C_MODULE);
|
||||
|
||||
/* Read MAC address */
|
||||
i2c_read(0x50, 0x0, 0, mac, 6);
|
||||
|
||||
if (is_valid_ethaddr(mac))
|
||||
eth_setenv_enetaddr("ethaddr", mac);
|
||||
printf("Cannot use I2C to get MAC address\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -161,14 +161,7 @@ int dram_init(void)
|
||||
*/
|
||||
static void read_hw_id(hw_id_t hw_id)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < HW_ID_ELEM_COUNT; ++i)
|
||||
if (i2c_read(CONFIG_SYS_I2C_EEPROM,
|
||||
hw_id_format[i].offset,
|
||||
2,
|
||||
(uchar *)&hw_id[i][0],
|
||||
hw_id_format[i].length) != 0)
|
||||
printf("ERROR: can't read HW ID from EEPROM\n");
|
||||
printf("ERROR: can't read HW ID from EEPROM\n");
|
||||
}
|
||||
|
||||
|
||||
@ -221,7 +214,7 @@ static void compose_module_name(hw_id_t hw_id, char *buf)
|
||||
strcat(buf, tmp);
|
||||
}
|
||||
|
||||
|
||||
#if defined(CONFIG_SYS_I2C_SOFT)
|
||||
/*
|
||||
* Compose string with hostname.
|
||||
* buf is assumed to have enough space, and be null-terminated.
|
||||
@ -237,7 +230,7 @@ static void compose_hostname(hw_id_t hw_id, char *buf)
|
||||
*p = tolower(*p);
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
/*
|
||||
@ -270,15 +263,6 @@ int checkboard(void)
|
||||
hw_id_t hw_id_tmp;
|
||||
char module_name_tmp[MODULE_NAME_MAXLEN] = "";
|
||||
|
||||
/*
|
||||
* We need I2C to access HW ID data from EEPROM, so we call i2c_init()
|
||||
* here despite the fact that it will be called again later on. We
|
||||
* also use a little trick to silence I2C-related output.
|
||||
*/
|
||||
gd->flags |= GD_FLG_SILENT;
|
||||
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
gd->flags &= ~GD_FLG_SILENT;
|
||||
|
||||
read_hw_id(hw_id_tmp);
|
||||
identify_module(hw_id_tmp); /* this sets gd->board_type */
|
||||
compose_module_name(hw_id_tmp, module_name_tmp);
|
||||
@ -311,7 +295,7 @@ int board_early_init_r(void)
|
||||
#ifdef CONFIG_MISC_INIT_R
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
|
||||
#if defined(CONFIG_SYS_I2C_SOFT)
|
||||
uchar buf[6];
|
||||
char str[18];
|
||||
char hostname[MODULE_NAME_MAXLEN];
|
||||
@ -334,16 +318,16 @@ int misc_init_r(void)
|
||||
" device at address %02X:%04X\n", CONFIG_SYS_I2C_EEPROM,
|
||||
CONFIG_MAC_OFFSET);
|
||||
}
|
||||
#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) */
|
||||
hostname[0] = 0x00;
|
||||
/* set the hostname appropriate to the module we're running on */
|
||||
compose_hostname(hw_id, hostname);
|
||||
setenv("hostname", hostname);
|
||||
|
||||
#endif /* defined(CONFIG_SYS_I2C_SOFT) */
|
||||
if (!getenv("ethaddr"))
|
||||
printf(LOG_PREFIX "MAC address not set, networking is not "
|
||||
"operational\n");
|
||||
|
||||
/* set the hostname appropriate to the module we're running on */
|
||||
hostname[0] = 0x00;
|
||||
compose_hostname(hw_id, hostname);
|
||||
setenv("hostname", hostname);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_MISC_INIT_R */
|
||||
|
||||
@ -13,34 +13,6 @@
|
||||
|
||||
#ifdef CONFIG_CMD_BSP
|
||||
|
||||
static int do_i2c_test(char * const argv[])
|
||||
{
|
||||
unsigned char temp, temp1;
|
||||
|
||||
printf("Starting I2C Test\n"
|
||||
"Please set Jumper:\nI2C SDA 2-3\nI2C SCL 2-3\n\n"
|
||||
"Please press any key to start\n\n");
|
||||
getc();
|
||||
|
||||
temp = 0xf0; /* set io 0-4 as output */
|
||||
i2c_write(CONFIG_SYS_I2C_IO, 3, 1, (uchar *)&temp, 1);
|
||||
|
||||
printf("Press I2C4-7. LED I2C0-3 should have the same state\n\n"
|
||||
"Press any key to stop\n\n");
|
||||
|
||||
while (!tstc()) {
|
||||
i2c_read(CONFIG_SYS_I2C_IO, 0, 1, (uchar *)&temp, 1);
|
||||
temp1 = (temp >> 4) & 0x03;
|
||||
temp1 |= (temp >> 3) & 0x08; /* S302 -> LED303 */
|
||||
temp1 |= (temp >> 5) & 0x04; /* S303 -> LED302 */
|
||||
temp = temp1;
|
||||
i2c_write(CONFIG_SYS_I2C_IO, 1, 1, (uchar *)&temp, 1);
|
||||
}
|
||||
getc();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_usb_test(char * const argv[])
|
||||
{
|
||||
int i;
|
||||
@ -387,9 +359,7 @@ static int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
|
||||
switch (argc) {
|
||||
case 2:
|
||||
if (strncmp(argv[1], "i2c", 3) == 0)
|
||||
rcode = do_i2c_test(argv);
|
||||
else if (strncmp(argv[1], "led", 3) == 0)
|
||||
if (strncmp(argv[1], "led", 3) == 0)
|
||||
rcode = do_led_test(argv);
|
||||
else if (strncmp(argv[1], "usb", 3) == 0)
|
||||
rcode = do_usb_test(argv);
|
||||
|
||||
@ -29,9 +29,6 @@ int misc_init_r(void)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
/* we use I2C-2 for on-board eeprom */
|
||||
i2c_set_bus_num(2);
|
||||
|
||||
tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
|
||||
printf("FPGA: %u-%u.%u.%u\n",
|
||||
(tmp & 0xFF000000) >> 24,
|
||||
|
||||
@ -18,17 +18,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int eeprom_write_enable(unsigned dev_addr, int state)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
||||
|
||||
if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR)
|
||||
return -1;
|
||||
|
||||
if (state == 0)
|
||||
setbits_be32(&im->gpio.gpdat, 0x00100000);
|
||||
else
|
||||
clrbits_be32(&im->gpio.gpdat, 0x00100000);
|
||||
|
||||
return 0;
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
|
||||
@ -83,7 +83,6 @@ CONFIG_MCFTMR -- define to use DMA timer
|
||||
CONFIG_MCFPIT -- define to use PIT timer
|
||||
|
||||
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
|
||||
CONFIG_HARD_I2C -- define for I2C hardware support
|
||||
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
|
||||
CONFIG_SYS_I2C_SPEED -- define for I2C speed
|
||||
CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
|
||||
|
||||
@ -91,7 +91,6 @@ CONFIG_MCFTMR -- define to use DMA timer
|
||||
CONFIG_MCFPIT -- define to use PIT timer
|
||||
|
||||
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
|
||||
CONFIG_HARD_I2C -- define for I2C hardware support
|
||||
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
|
||||
CONFIG_SYS_I2C_SPEED -- define for I2C speed
|
||||
CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
|
||||
|
||||
@ -90,7 +90,6 @@ CONFIG_MCFTMR -- define to use DMA timer
|
||||
CONFIG_MCFPIT -- define to use PIT timer
|
||||
|
||||
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
|
||||
CONFIG_HARD_I2C -- define for I2C hardware support
|
||||
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
|
||||
CONFIG_SYS_I2C_SPEED -- define for I2C speed
|
||||
CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
|
||||
|
||||
@ -113,7 +113,6 @@ CONFIG_MCFTMR -- define to use DMA timer
|
||||
CONFIG_MCFPIT -- define to use PIT timer
|
||||
|
||||
CONFIG_SYS_FSL_I2C -- define to use FSL common I2C driver
|
||||
CONFIG_HARD_I2C -- define for I2C hardware support
|
||||
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
|
||||
CONFIG_SYS_I2C_SPEED -- define for I2C speed
|
||||
CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
|
||||
|
||||
@ -98,7 +98,6 @@ CONFIG_DOS_PARTITION -- enable DOS read/write
|
||||
CONFIG_SLTTMR -- define to use SLT timer
|
||||
|
||||
CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
|
||||
CONFIG_HARD_I2C -- define for I2C hardware support
|
||||
CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
|
||||
CONFIG_SYS_I2C_SPEED -- define for I2C speed
|
||||
CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
|
||||
|
||||
@ -174,27 +174,6 @@ int dram_init(void)
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
u8 tmp_val;
|
||||
|
||||
/* Using this for DIU init before the driver in linux takes over
|
||||
* Enable the TFP410 Encoder (I2C address 0x38)
|
||||
*/
|
||||
|
||||
i2c_set_bus_num(2);
|
||||
tmp_val = 0xBF;
|
||||
i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
|
||||
/* Verify if enabled */
|
||||
tmp_val = 0;
|
||||
i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
|
||||
debug("DVI Encoder Read: 0x%02x\n", tmp_val);
|
||||
|
||||
tmp_val = 0x10;
|
||||
i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
|
||||
/* Verify if enabled */
|
||||
tmp_val = 0;
|
||||
i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
|
||||
debug("DVI Encoder Read: 0x%02x\n", tmp_val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -17,7 +17,6 @@
|
||||
#include <i2c.h>
|
||||
#endif
|
||||
|
||||
static int eeprom_diag;
|
||||
static int mac_diag;
|
||||
static int gpio_diag;
|
||||
|
||||
@ -136,7 +135,6 @@ struct __attribute__ ((__packed__)) eeprom_layout {
|
||||
#define HW_COMP_MAINCPU 2
|
||||
|
||||
static struct eeprom_layout eeprom_content;
|
||||
static int eeprom_was_read; /* has_been_read */
|
||||
static int eeprom_is_valid;
|
||||
static int eeprom_version;
|
||||
|
||||
@ -153,53 +151,7 @@ static int eeprom_version;
|
||||
|
||||
static int read_eeprom(void)
|
||||
{
|
||||
int eeprom_datalen;
|
||||
int ret;
|
||||
|
||||
if (eeprom_was_read)
|
||||
return 0;
|
||||
|
||||
eeprom_is_valid = 0;
|
||||
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
|
||||
(uchar *)&eeprom_content, sizeof(eeprom_content));
|
||||
if (eeprom_diag) {
|
||||
printf("DIAG: %s() read rc[%d], size[%d]\n",
|
||||
__func__, ret, sizeof(eeprom_content));
|
||||
}
|
||||
|
||||
if (ret != 0)
|
||||
return -1;
|
||||
|
||||
eeprom_was_read = 1;
|
||||
|
||||
/*
|
||||
* check validity of EEPROM content
|
||||
* (check version, length, optionally checksum)
|
||||
*/
|
||||
eeprom_is_valid = 1;
|
||||
eeprom_datalen = get_eeprom_field_int(eeprom_content.len);
|
||||
eeprom_version = get_eeprom_field_int(eeprom_content.version);
|
||||
|
||||
if (eeprom_diag) {
|
||||
printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n",
|
||||
__func__, eeprom_content.magic[0],
|
||||
eeprom_content.magic[1], eeprom_content.magic[2],
|
||||
eeprom_datalen, eeprom_version, eeprom_content.type);
|
||||
}
|
||||
if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0)
|
||||
eeprom_is_valid = 0;
|
||||
if (eeprom_datalen < sizeof(struct eeprom_layout) - 5)
|
||||
eeprom_is_valid = 0;
|
||||
if ((eeprom_version != 1) && (eeprom_version != 2))
|
||||
eeprom_is_valid = 0;
|
||||
if (eeprom_content.type != HW_COMP_MAINCPU)
|
||||
eeprom_is_valid = 0;
|
||||
|
||||
if (eeprom_diag)
|
||||
printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid);
|
||||
|
||||
return ret;
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
int mac_read_from_eeprom(void)
|
||||
@ -324,9 +276,6 @@ int misc_init_r(void)
|
||||
char *s;
|
||||
int want_recovery;
|
||||
|
||||
/* we use bus I2C-0 for the on-board eeprom */
|
||||
i2c_set_bus_num(0);
|
||||
|
||||
/* setup GPIO directions and initial values */
|
||||
gpio_configure();
|
||||
|
||||
|
||||
@ -153,13 +153,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD18 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD17 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD16 */
|
||||
#if defined(CONFIG_HARD_I2C)
|
||||
{ 1, 1, 1, 0, 1, 0 }, /* PD15 I2C SDA */
|
||||
{ 1, 1, 1, 0, 1, 0 }, /* PD14 I2C SCL */
|
||||
#else
|
||||
{ 1, 0, 0, 0, 1, 1 }, /* PD15 */
|
||||
{ 1, 0, 0, 1, 1, 1 }, /* PD14 */
|
||||
#endif
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD13 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD12 */
|
||||
{ 0, 0, 0, 0, 0, 0 }, /* PD11 */
|
||||
|
||||
@ -75,10 +75,6 @@ static const u32 kwmpp_config[] = {
|
||||
#if defined(CONFIG_SYS_I2C_SOFT)
|
||||
MPP8_GPIO, /* SDA */
|
||||
MPP9_GPIO, /* SCL */
|
||||
#endif
|
||||
#if defined(CONFIG_HARD_I2C)
|
||||
MPP8_TW_SDA,
|
||||
MPP9_TW_SCK,
|
||||
#endif
|
||||
MPP10_UART0_TXD,
|
||||
MPP11_UART0_RXD,
|
||||
|
||||
@ -169,36 +169,6 @@ int misc_init_r(void)
|
||||
clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HARD_I2C)
|
||||
if (!getenv("ethaddr")) {
|
||||
uchar buf[6];
|
||||
uchar ifm_oui[3] = { 0, 2, 1, };
|
||||
int ret;
|
||||
|
||||
/* I2C-0 for on-board eeprom */
|
||||
i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
|
||||
|
||||
/* Read ethaddr from EEPROM */
|
||||
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
|
||||
CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
|
||||
if (ret != 0) {
|
||||
printf("Error: Unable to read MAC from I2C"
|
||||
" EEPROM at address %02X:%02X\n",
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR,
|
||||
CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Owned by IFM ? */
|
||||
if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
|
||||
printf("Illegal MAC address in EEPROM: %pM\n", buf);
|
||||
return 1;
|
||||
}
|
||||
|
||||
eth_setenv_enetaddr("ethaddr", buf);
|
||||
}
|
||||
#endif /* defined(CONFIG_HARD_I2C) */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -44,17 +44,7 @@ int board_init(void)
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
u8 mac[6];
|
||||
|
||||
/* Read Mac Address and set*/
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
i2c_set_bus_num(CONFIG_SYS_I2C_MODULE);
|
||||
|
||||
/* Read MAC address */
|
||||
i2c_read(0x50, 0x10, 0, mac, 6);
|
||||
|
||||
if (is_valid_ethaddr(mac))
|
||||
eth_setenv_enetaddr("ethaddr", mac);
|
||||
printf("Cannot get MAC address from I2C\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -72,7 +72,8 @@ void do_board_detect(void)
|
||||
enable_i2c0_pin_mux();
|
||||
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
|
||||
|
||||
if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
|
||||
if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
|
||||
CONFIG_EEPROM_CHIP_ADDRESS))
|
||||
printf("ti_i2c_eeprom_init failed\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -42,7 +42,8 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
#ifdef CONFIG_TI_I2C_BOARD_DETECT
|
||||
void do_board_detect(void)
|
||||
{
|
||||
if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
|
||||
if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
|
||||
CONFIG_EEPROM_CHIP_ADDRESS))
|
||||
printf("ti_i2c_eeprom_init failed\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -486,20 +486,14 @@ int board_early_init_f (void)
|
||||
|
||||
static int tfp410_read_reg(int reg, uchar *buf)
|
||||
{
|
||||
if (i2c_read(CONFIG_SYS_TFP410_ADDR, reg, 1, buf, 1) != 0) {
|
||||
puts ("Error reading the chip.\n");
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
puts("Error reading the chip.\n");
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static int tfp410_write_reg(int reg, uchar buf)
|
||||
{
|
||||
if (i2c_write(CONFIG_SYS_TFP410_ADDR, reg, 1, &buf, 1) != 0) {
|
||||
puts ("Error writing the chip.\n");
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
puts("Error writing the chip.\n");
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
typedef struct _tfp410_config {
|
||||
@ -525,12 +519,9 @@ static int charon_last_stage_init(void)
|
||||
{
|
||||
volatile struct mpc5xxx_lpb *lpb =
|
||||
(struct mpc5xxx_lpb *) MPC5XXX_LPB;
|
||||
int oldbus = i2c_get_bus_num();
|
||||
uchar buf;
|
||||
int i = 0;
|
||||
|
||||
i2c_set_bus_num(CONFIG_SYS_TFP410_BUS);
|
||||
|
||||
/* check version */
|
||||
if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
|
||||
return -1;
|
||||
@ -551,7 +542,6 @@ static int charon_last_stage_init(void)
|
||||
i++;
|
||||
}
|
||||
printf("TFP410 initialized.\n");
|
||||
i2c_set_bus_num(oldbus);
|
||||
|
||||
/* set deadcycle for cs3 to 0 */
|
||||
setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
|
||||
|
||||
@ -73,11 +73,9 @@ void eeprom_init(int bus)
|
||||
#endif
|
||||
|
||||
/* I2C EEPROM */
|
||||
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
|
||||
#if defined(CONFIG_SYS_I2C)
|
||||
if (bus >= 0)
|
||||
i2c_set_bus_num(bus);
|
||||
#endif
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -184,7 +184,7 @@ __weak int dram_init_banksize(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
|
||||
#if defined(CONFIG_SYS_I2C)
|
||||
static int init_func_i2c(void)
|
||||
{
|
||||
puts("I2C: ");
|
||||
@ -767,7 +767,7 @@ static const init_fnc_t init_sequence_f[] = {
|
||||
misc_init_f,
|
||||
#endif
|
||||
INIT_FUNC_WATCHDOG_RESET
|
||||
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
|
||||
#if defined(CONFIG_SYS_I2C)
|
||||
init_func_i2c,
|
||||
#endif
|
||||
#if defined(CONFIG_HARD_SPI)
|
||||
|
||||
@ -485,24 +485,7 @@ static int initr_env(void)
|
||||
|
||||
/* Initialize from environment */
|
||||
load_addr = getenv_ulong("loadaddr", 16, load_addr);
|
||||
#if defined(CONFIG_SYS_EXTBDINFO)
|
||||
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
|
||||
#if defined(CONFIG_I2CFAST)
|
||||
/*
|
||||
* set bi_iic_fast for linux taking environment variable
|
||||
* "i2cfast" into account
|
||||
*/
|
||||
{
|
||||
char *s = getenv("i2cfast");
|
||||
|
||||
if (s && ((*s == 'y') || (*s == 'Y'))) {
|
||||
gd->bd->bi_iic_fast[0] = 1;
|
||||
gd->bd->bi_iic_fast[1] = 1;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_I2CFAST */
|
||||
#endif /* CONFIG_405GP, CONFIG_405EP */
|
||||
#endif /* CONFIG_SYS_EXTBDINFO */
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
#include <logbuff.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
|
||||
#if defined(CONFIG_SYS_I2C)
|
||||
#include <i2c.h>
|
||||
#endif
|
||||
|
||||
@ -346,9 +346,6 @@ int stdio_add_devices(void)
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
i2c_init_all();
|
||||
#else
|
||||
#if defined(CONFIG_HARD_I2C)
|
||||
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
#endif
|
||||
#endif
|
||||
#ifdef CONFIG_DM_VIDEO
|
||||
/*
|
||||
|
||||
@ -10,7 +10,6 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
@ -19,7 +18,6 @@ CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_BSP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_DIAG=y
|
||||
|
||||
@ -4,7 +4,6 @@ CONFIG_TARGET_O2D300=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTDELAY=5
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
|
||||
@ -8,7 +8,6 @@ CONFIG_HUSH_PARSER=y
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
|
||||
CONFIG_AUTOBOOT_STOP_STR="++++++++++"
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
|
||||
@ -7,7 +7,6 @@ CONFIG_HUSH_PARSER=y
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
|
||||
CONFIG_AUTOBOOT_STOP_STR="++++++++++"
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
|
||||
@ -4,7 +4,6 @@ CONFIG_TARGET_O2D=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTDELAY=5
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
|
||||
@ -4,7 +4,6 @@ CONFIG_TARGET_O2I=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTDELAY=5
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
|
||||
@ -5,7 +5,6 @@ CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M110\""
|
||||
CONFIG_BOOTDELAY=5
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
|
||||
@ -5,7 +5,6 @@ CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M112\""
|
||||
CONFIG_BOOTDELAY=5
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
|
||||
@ -5,7 +5,6 @@ CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M113\""
|
||||
CONFIG_BOOTDELAY=5
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
|
||||
@ -4,7 +4,6 @@ CONFIG_TARGET_O2MNT=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTDELAY=5
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
|
||||
@ -4,7 +4,6 @@ CONFIG_TARGET_O3DNT=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTDELAY=5
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
|
||||
@ -7,7 +7,6 @@ CONFIG_BOOTDELAY=5
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
@ -15,7 +14,6 @@ CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_BSP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_DIAG=y
|
||||
|
||||
@ -7,7 +7,6 @@ CONFIG_BOOTDELAY=5
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
@ -15,7 +14,6 @@ CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_BSP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_DIAG=y
|
||||
|
||||
@ -10,7 +10,6 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
@ -19,7 +18,6 @@ CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_BSP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_DIAG=y
|
||||
|
||||
@ -10,7 +10,6 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
@ -19,7 +18,6 @@ CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_BSP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_DIAG=y
|
||||
|
||||
@ -10,7 +10,6 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
@ -19,7 +18,6 @@ CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_BSP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_DIAG=y
|
||||
|
||||
@ -9,7 +9,6 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
@ -18,7 +17,6 @@ CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_BSP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_DIAG=y
|
||||
|
||||
@ -7,7 +7,6 @@ CONFIG_HUSH_PARSER=y
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
|
||||
CONFIG_AUTOBOOT_DELAY_STR="asdfg"
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
|
||||
@ -5,7 +5,6 @@ CONFIG_FIT=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_PROMPT="ac14xx> "
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
|
||||
@ -13,7 +13,6 @@ CONFIG_VERSION_VARIABLE=y
|
||||
# CONFIG_CMD_ENV_EXISTS is not set
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_FPGA is not set
|
||||
# CONFIG_CMD_ECHO is not set
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
|
||||
@ -14,14 +14,12 @@ CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_UBI=y
|
||||
|
||||
@ -5,7 +5,6 @@ CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTDELAY=5
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
|
||||
@ -6,7 +6,6 @@ CONFIG_BOOTDELAY=3
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_CMD_NET is not set
|
||||
# CONFIG_CMD_NFS is not set
|
||||
|
||||
@ -7,14 +7,12 @@ CONFIG_BOOTDELAY=5
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_BSP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
CONFIG_DOS_PARTITION=y
|
||||
CONFIG_ISO_PARTITION=y
|
||||
|
||||
@ -7,14 +7,12 @@ CONFIG_BOOTDELAY=5
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_BSP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
CONFIG_DOS_PARTITION=y
|
||||
CONFIG_ISO_PARTITION=y
|
||||
|
||||
@ -9,7 +9,6 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
|
||||
@ -6,7 +6,6 @@ CONFIG_BOOTDELAY=5
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
|
||||
@ -13,7 +13,6 @@ CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
|
||||
CONFIG_AUTOBOOT_DELAY_STR="d"
|
||||
CONFIG_AUTOBOOT_STOP_STR=" "
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
@ -21,7 +20,6 @@ CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_DIAG=y
|
||||
|
||||
@ -11,7 +11,6 @@ CONFIG_AUTOBOOT_KEYED=y
|
||||
CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
|
||||
CONFIG_AUTOBOOT_DELAY_STR=" "
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
@ -19,7 +18,6 @@ CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_DIAG=y
|
||||
|
||||
@ -13,7 +13,6 @@ CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
|
||||
CONFIG_AUTOBOOT_DELAY_STR="d"
|
||||
CONFIG_AUTOBOOT_STOP_STR=" "
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
@ -21,7 +20,6 @@ CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_DIAG=y
|
||||
|
||||
@ -13,7 +13,6 @@ CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
|
||||
CONFIG_AUTOBOOT_DELAY_STR="d"
|
||||
CONFIG_AUTOBOOT_STOP_STR=" "
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
@ -21,7 +20,6 @@ CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_DIAG=y
|
||||
|
||||
@ -12,7 +12,6 @@ CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
@ -21,7 +20,6 @@ CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_BSP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_DIAG=y
|
||||
|
||||
@ -6,7 +6,6 @@ CONFIG_BOOTDELAY=3
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_FPGA is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
|
||||
@ -7,13 +7,11 @@ CONFIG_BOOTDELAY=5
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_LOOPW=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
||||
@ -22,7 +22,6 @@ CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
|
||||
@ -6,12 +6,10 @@ CONFIG_BOOTDELAY=5
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
||||
@ -8,12 +8,10 @@ CONFIG_AUTOBOOT_KEYED=y
|
||||
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
|
||||
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_BEDBUG=y
|
||||
CONFIG_LED_STATUS=y
|
||||
|
||||
@ -6,13 +6,11 @@ CONFIG_BOOTDELAY=5
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
|
||||
@ -7,13 +7,11 @@ CONFIG_BOOTDELAY=5
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
|
||||
@ -4,11 +4,9 @@ CONFIG_TARGET_PCM030=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_DATE=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_USB=y
|
||||
|
||||
@ -4,11 +4,9 @@ CONFIG_TARGET_PCM030=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_SYS_PROMPT="uboot> "
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_DATE=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_USB=y
|
||||
|
||||
@ -10,13 +10,11 @@ CONFIG_SILENT_CONSOLE=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
# CONFIG_PCI is not set
|
||||
|
||||
@ -13,7 +13,6 @@ CONFIG_VERSION_VARIABLE=y
|
||||
# CONFIG_CMD_ENV_EXISTS is not set
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
# CONFIG_CMD_FPGA is not set
|
||||
# CONFIG_CMD_ECHO is not set
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
|
||||
@ -3,13 +3,11 @@ CONFIG_MPC5xxx=y
|
||||
CONFIG_TARGET_V38B=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_DIAG=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
|
||||
@ -284,15 +284,6 @@ static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
|
||||
/* Call board specific i2c bus reset routine AFTER the bus has been
|
||||
* initialized. Use either this callpoint or i2c_init_board;
|
||||
* which is called before i2c_init operations.
|
||||
* For details about this problem see doc/I2C_Edge_Conditions.
|
||||
*/
|
||||
i2c_board_late_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
static int
|
||||
|
||||
@ -146,15 +146,6 @@ static void fti2c010_init(struct i2c_adapter *adap, int speed, int slaveaddr)
|
||||
set_i2c_bus_speed(chip, speed);
|
||||
|
||||
/* slave init, don't care */
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
|
||||
/* Call board specific i2c bus reset routine AFTER the bus has been
|
||||
* initialized. Use either this callpoint or i2c_init_board;
|
||||
* which is called before fti2c010_init operations.
|
||||
* For details about this problem see doc/I2C_Edge_Conditions.
|
||||
*/
|
||||
i2c_board_late_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -69,10 +69,6 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
#define I2SR_IIF_CLEAR (0 << 1)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
|
||||
#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
|
||||
#endif
|
||||
|
||||
#ifdef I2C_QUIRK_REG
|
||||
static u16 i2c_clk_div[60][2] = {
|
||||
{ 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
|
||||
|
||||
@ -499,9 +499,19 @@ void reset_phy (void);
|
||||
void fdc_hw_init (void);
|
||||
|
||||
/* $(BOARD)/eeprom.c */
|
||||
#ifdef CONFIG_CMD_EEPROM
|
||||
void eeprom_init (int bus);
|
||||
int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
|
||||
int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
|
||||
#else
|
||||
/*
|
||||
* Some EEPROM code is depecated because it used the legacy I2C interface. Add
|
||||
* some macros here so we don't have to touch every one of those uses
|
||||
*/
|
||||
#define eeprom_init(bus)
|
||||
#define eeprom_read(dev_addr, offset, buffer, cnt) ((void)-ENOSYS)
|
||||
#define eeprom_write(dev_addr, offset, buffer, cnt) ((void)-ENOSYS)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Set this up regardless of board
|
||||
|
||||
@ -166,7 +166,6 @@
|
||||
|
||||
/* I2c */
|
||||
#undef CONFIG_SYS_FSL_I2C
|
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
|
||||
/* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000
|
||||
|
||||
@ -124,8 +124,7 @@
|
||||
#ifndef CONFIG_CAM5200
|
||||
/* POST support */
|
||||
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
|
||||
CONFIG_SYS_POST_CPU | \
|
||||
CONFIG_SYS_POST_I2C)
|
||||
CONFIG_SYS_POST_CPU)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
@ -144,7 +143,6 @@
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
@ -278,54 +276,6 @@
|
||||
#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#ifdef CONFIG_TQM5200_REV100
|
||||
#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
|
||||
#else
|
||||
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I2C clock frequency
|
||||
*
|
||||
* Please notice, that the resulting clock frequency could differ from the
|
||||
* configured value. This is because the I2C clock is derived from system
|
||||
* clock over a frequency divider with only a few divider values. U-Boot
|
||||
* calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
|
||||
* approximation allways lies below the configured value, never above.
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
|
||||
* also). For other EEPROMs configuration should be verified. On Mini-FAP the
|
||||
* EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
|
||||
* same configuration could be used.
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
|
||||
/*
|
||||
* HW-Monitor configuration on Mini-FAP
|
||||
*/
|
||||
#if defined (CONFIG_MINIFAP)
|
||||
#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
|
||||
#endif
|
||||
|
||||
/* List of I2C addresses to be verified by POST */
|
||||
#if defined (CONFIG_MINIFAP)
|
||||
#undef CONFIG_SYS_POST_I2C_ADDRS
|
||||
#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
|
||||
CONFIG_SYS_I2C_HWMON_ADDR, \
|
||||
CONFIG_SYS_I2C_SLAVE}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Flash configuration
|
||||
*/
|
||||
@ -544,18 +494,6 @@
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
|
||||
# define CONFIG_RTC_M41T11 1
|
||||
# define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
# define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
|
||||
year */
|
||||
#else
|
||||
# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
||||
@ -81,7 +81,6 @@
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_IDE
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
@ -145,25 +144,6 @@
|
||||
*/
|
||||
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
|
||||
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
|
||||
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* EEPROM configuration
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010010x */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
#define CONFIG_SYS_EEPROM_WREN 1
|
||||
#define CONFIG_SYS_EEPROM_WP GPIO_PSC2_4
|
||||
|
||||
/*
|
||||
* Flash configuration
|
||||
*/
|
||||
|
||||
@ -336,28 +336,11 @@
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* command line history */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
|
||||
/* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* IIM - IC Identification Module
|
||||
*/
|
||||
#undef CONFIG_FSL_IIM
|
||||
|
||||
/*
|
||||
* EEPROM configuration for Atmel AT24C01:
|
||||
* 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 30
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
@ -384,7 +367,6 @@
|
||||
#define CONFIG_LOADS_ECHO 1
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
|
||||
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#undef CONFIG_CMD_FUSE
|
||||
#undef CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_JFFS2
|
||||
|
||||
@ -35,20 +35,6 @@
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SH_SH7734_I2C 1
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_I2C_MULTI_BUS 1
|
||||
#define CONFIG_SYS_MAX_I2C_BUS 2
|
||||
#define CONFIG_SYS_I2C_MODULE 0
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* 400 kHz */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x50
|
||||
#define CONFIG_SH_I2C_DATA_HIGH 4
|
||||
#define CONFIG_SH_I2C_DATA_LOW 5
|
||||
#define CONFIG_SH_I2C_CLOCK 500000000
|
||||
#define CONFIG_SH_I2C_BASE0 0xFFC70000
|
||||
#define CONFIG_SH_I2C_BASE1 0xFFC71000
|
||||
|
||||
/* undef to save memory */
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
/* Monitor Command Prompt */
|
||||
|
||||
@ -79,12 +79,6 @@
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#endif
|
||||
|
||||
/* RTC */
|
||||
#ifdef CONFIG_CMD_DATE
|
||||
#define CONFIG_RTC_PCF8563
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
|
||||
#endif
|
||||
|
||||
/* Boot Linux */
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_BOOTCOMMAND "run bootcmd_nand"
|
||||
|
||||
@ -340,31 +340,11 @@
|
||||
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
|
||||
/* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#if 0
|
||||
#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* IIM - IC Identification Module
|
||||
*/
|
||||
#undef CONFIG_FSL_IIM
|
||||
|
||||
/*
|
||||
* EEPROM configuration for Atmel AT24C32A-10TQ-2.7:
|
||||
* 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
@ -392,7 +372,6 @@
|
||||
#define CONFIG_LOADS_ECHO 1
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
|
||||
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#undef CONFIG_CMD_FUSE
|
||||
#undef CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_JFFS2
|
||||
|
||||
@ -100,7 +100,7 @@
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_EEPROM
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#define CONFIG_ENV_SIZE SZ_512
|
||||
#define CONFIG_ENV_OFFSET 0
|
||||
|
||||
|
||||
@ -44,7 +44,7 @@
|
||||
/*
|
||||
* POST support
|
||||
*/
|
||||
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
|
||||
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU)
|
||||
#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
|
||||
/* List of I2C addresses to be verified by POST */
|
||||
#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \
|
||||
@ -199,16 +199,6 @@
|
||||
"2m(kernel),27904k(rootfs)," \
|
||||
"-(config)"
|
||||
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
|
||||
#define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x0
|
||||
#define CONFIG_SYS_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */
|
||||
#define CONFIG_SYS_I2C_EEPROM 0x53 /* I2C EEPROM device address */
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
|
||||
@ -85,7 +85,6 @@
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_PCI
|
||||
@ -205,36 +204,6 @@
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run mtcb_start"
|
||||
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_MODULE 1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* EEPROM configuration
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#if defined(CONFIG_DIGSY_REV5)
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x56
|
||||
#define CONFIG_RTC_RV3029
|
||||
/* Enable 5k Ohm trickle charge resistor */
|
||||
#define CONFIG_SYS_RV3029_TCR 0x20
|
||||
#else
|
||||
#define CONFIG_RTC_DS1337
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
#define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Flash configuration
|
||||
*/
|
||||
|
||||
@ -165,7 +165,6 @@
|
||||
#define CONFIG_TSEC2
|
||||
#define CONFIG_TSEC_ENET
|
||||
#define CONFIG_HARD_SPI
|
||||
#define CONFIG_HARD_I2C
|
||||
|
||||
/*
|
||||
* NOR FLASH setup
|
||||
|
||||
@ -150,29 +150,6 @@
|
||||
#define OF_SOC "soc5200@f0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 4)
|
||||
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
|
||||
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* EEPROM configuration
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#define CONFIG_RTC_PCF8563
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFC000000
|
||||
#define CONFIG_SYS_FLASH_SIZE 0x01000000
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
|
||||
|
||||
@ -127,25 +127,6 @@
|
||||
#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
|
||||
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* EEPROM configuration
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Flash configuration
|
||||
*/
|
||||
|
||||
@ -16,7 +16,6 @@
|
||||
/* U-Boot Commands */
|
||||
#define CONFIG_FAT_WRITE
|
||||
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_NAND_TRIMFFS
|
||||
|
||||
@ -63,11 +62,6 @@
|
||||
#define CONFIG_FEC_MXC
|
||||
#endif
|
||||
|
||||
/* EEPROM */
|
||||
#ifdef CONFIG_CMD_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#endif
|
||||
|
||||
/* RTC */
|
||||
#ifdef CONFIG_CMD_DATE
|
||||
/* Use the internal RTC in the MXS chip */
|
||||
|
||||
176
include/configs/manroland/mpc5200-common.h
Normal file
176
include/configs/manroland/mpc5200-common.h
Normal file
@ -0,0 +1,176 @@
|
||||
/*
|
||||
* (C) Copyright 2009
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MANROLAND_MPC52XX__COMMON_H
|
||||
#define __MANROLAND_MPC52XX__COMMON_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_MPC5200 1 /* MPC5200 CPU */
|
||||
|
||||
/* ... running at 33.000000MHz */
|
||||
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
|
||||
|
||||
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
||||
|
||||
/*
|
||||
* Serial console configuration
|
||||
*/
|
||||
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200,\
|
||||
230400 }
|
||||
|
||||
#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
|
||||
# define CONFIG_SYS_LOWBOOT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* IPB Bus clocking configuration.
|
||||
*/
|
||||
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
|
||||
|
||||
/*
|
||||
* Flash configuration
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFF800000
|
||||
|
||||
#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
|
||||
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
|
||||
(= chip selects) */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout [ms]*/
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout [ms]*/
|
||||
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_CFI_AMD_RESET
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_SIZE 0x4000
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*/
|
||||
#define CONFIG_SYS_MBAR 0xF0000000
|
||||
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SRAM_BASE 0x80100000 /* CS 1 */
|
||||
#define CONFIG_SYS_DISPLAY_BASE 0x80600000 /* CS 3 */
|
||||
|
||||
/* Settings for XLB = 132 MHz */
|
||||
#define SDRAM_DDR 1
|
||||
#define SDRAM_MODE 0x018D0000
|
||||
#define SDRAM_EMODE 0x40090000
|
||||
#define SDRAM_CONTROL 0x714f0f00
|
||||
#define SDRAM_CONFIG1 0x73722930
|
||||
#define SDRAM_CONFIG2 0x47770000
|
||||
#define SDRAM_TAPDELAY 0x10000000
|
||||
|
||||
/* Use ON-Chip SRAM until RAM will be available */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
|
||||
#ifdef CONFIG_POST
|
||||
/* preserve space for the post_word at end of on-chip SRAM */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
# define CONFIG_SYS_RAMBOOT 1
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 << 10)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
#define CONFIG_MPC5xxx_FEC 1
|
||||
#define CONFIG_MPC5xxx_FEC_MII100
|
||||
#define CONFIG_PHY_ADDR 0x00
|
||||
#define CONFIG_MII 1
|
||||
|
||||
/*use Hardware WDT */
|
||||
#define CONFIG_HW_WATCHDOG
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Various low-level settings
|
||||
*/
|
||||
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
|
||||
#define CONFIG_SYS_HID0_FINAL HID0_ICE
|
||||
|
||||
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
|
||||
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
|
||||
|
||||
/* 8Mbit SRAM @0x80100000 */
|
||||
#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
|
||||
|
||||
#define CONFIG_SYS_CS_BURST 0x00000000
|
||||
#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff Supports IDE harddisk
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
|
||||
#define CONFIG_IDE_PREINIT 1
|
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
|
||||
|
||||
/* Interval between registers */
|
||||
#define CONFIG_SYS_ATA_STRIDE 4
|
||||
|
||||
#define CONFIG_ATAPI 1
|
||||
|
||||
#define OF_CPU "PowerPC,5200@0"
|
||||
#define OF_SOC "soc5200@f0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 4)
|
||||
#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
|
||||
#define CONFIG_OF_IDE_FIXUP
|
||||
|
||||
#endif /* __MANROLAND_MPC52XX__COMMON_H */
|
||||
@ -241,26 +241,11 @@
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
|
||||
|
||||
/*
|
||||
* IIM - IC Identification Module
|
||||
*/
|
||||
#undef CONFIG_FSL_IIM
|
||||
|
||||
/*
|
||||
* EEPROM configuration
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
|
||||
#define CONFIG_SYS_EEPROM_WREN /* Use EEPROM write protect */
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
@ -280,7 +265,7 @@
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_EEPROM /* Store env in I2C EEPROM */
|
||||
#define CONFIG_ENV_IS_NOWHERE /* Store env in I2C EEPROM */
|
||||
#define CONFIG_ENV_SIZE 0x1000
|
||||
#define CONFIG_ENV_OFFSET 0x0000 /* environment starts here */
|
||||
|
||||
@ -288,7 +273,6 @@
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
||||
|
||||
#define CONFIG_CMD_REGINFO
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#undef CONFIG_CMD_FUSE
|
||||
#undef CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_JFFS2
|
||||
|
||||
@ -34,7 +34,6 @@
|
||||
* Command line configuration.
|
||||
*/
|
||||
#define CONFIG_CMD_DTT
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_IMMAP
|
||||
#define CONFIG_CMD_JFFS2
|
||||
@ -255,21 +254,6 @@
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET CONFIG_SYS_ATA_DATA_OFFSET
|
||||
#define CONFIG_SYS_ATA_STRIDE 4
|
||||
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_MODULE 2 /* select I2C module #2 */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* EEPROM configuration
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 1 /* 2 bytes per write cycle */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 2ms/cycle + 3ms extra */
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
@ -283,12 +267,6 @@
|
||||
#define ENABLE_GPIO_OUT 0x00000024
|
||||
#define LED_ON 0x00000010
|
||||
|
||||
/*
|
||||
* Temperature sensor
|
||||
*/
|
||||
#define CONFIG_DTT_LM75 1
|
||||
#define CONFIG_DTT_SENSORS { 0x49 }
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
|
||||
@ -327,28 +327,11 @@
|
||||
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#if 0
|
||||
#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* IIM - IC Identification Module
|
||||
*/
|
||||
#undef CONFIG_FSL_IIM
|
||||
|
||||
/*
|
||||
* EEPROM configuration
|
||||
*/
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
@ -395,7 +378,6 @@
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_IDE
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue
Block a user