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powerpc: Disable flush or invalidate dcache by range for some SoCs

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Commit ac337168a unified functions to flush and invalidate dcache by
range. These two functions were no-op for SoCs other than 4xx and
MPC86xx. Adding these functions seemed to be correct but introduced
issues when the dcache is flushed. While the root cause is under
investigation, disable these functions for affected SoCs so various
drivers can work.

Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun 2016-04-07 09:56:48 -07:00
parent aeaec0e682
commit cb1629f91a
1 changed files with 4 additions and 0 deletions
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4
arch/powerpc/lib/ppccache.S
View File

@ -65,6 +65,7 @@ ppcSync:
* flush_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(flush_dcache_range)
#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
@ -77,6 +78,7 @@ _GLOBAL(flush_dcache_range)
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbst's to get to ram */
#endif
blr
/*
@ -87,6 +89,7 @@ _GLOBAL(flush_dcache_range)
* invalidate_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(invalidate_dcache_range)
#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
@ -100,5 +103,6 @@ _GLOBAL(invalidate_dcache_range)
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbi's to get to ram */
#endif
blr