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Tegra: MMC: Add DT support to MMC driver for all T20 boards

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tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc.
Tested on Seaboard, fully functional.

Tamonten boards (medcom-wide, plutux, and tec) use a different/new
dtsi file w/common settings.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Tom Warren 2013-02-21 12:31:30 +00:00 committed by Tom Warren
parent 126685ad44
commit c9aa831ee2
13 changed files with 173 additions and 208 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/include/asm/arch-tegra/mmc.h
View File

@ -22,6 +22,6 @@
#ifndef _TEGRA_MMC_H_
#define _TEGRA_MMC_H_
int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
void tegra_mmc_init(void);
#endif /* _TEGRA_MMC_H_ */

13
arch/arm/include/asm/arch-tegra/tegra_mmc.h
View File

@ -27,6 +27,8 @@
#define TEGRA_SDMMC3_BASE 0xC8000400
#define TEGRA_SDMMC4_BASE 0xC8000600
#define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */
#ifndef __ASSEMBLY__
struct tegra_mmc {
unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
@ -119,12 +121,15 @@ struct tegra_mmc {
struct mmc_host {
struct tegra_mmc *reg;
int id; /* device id/number, 0-3 */
int enabled; /* 1 to enable, 0 to disable */
int width; /* Bus Width, 1, 4 or 8 */
enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
struct fdt_gpio_state cd_gpio; /* Change Detect GPIO */
struct fdt_gpio_state pwr_gpio; /* Power GPIO */
struct fdt_gpio_state wp_gpio; /* Write Protect GPIO */
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
unsigned int base; /* Base address, SDMMC1/2/3/4 */
enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
int pwr_gpio; /* Power GPIO */
int cd_gpio; /* Change Detect GPIO */
};
#endif /* __ASSEMBLY__ */

19
board/avionic-design/common/tamonten.c
View File

@ -33,13 +33,8 @@
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/mmc.h>
#include <asm/arch-tegra/sys_proto.h>
#include <asm/arch-tegra/uart.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
void gpio_early_init(void)
@ -54,7 +49,7 @@ void gpio_early_init(void)
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
*/
static void pin_mux_mmc(void)
void pin_mux_mmc(void)
{
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
/* for write-protect GPIO PI6 */
@ -62,16 +57,4 @@ static void pin_mux_mmc(void)
/* for CD GPIO PH2 */
pinmux_tristate_disable(PINGRP_ATD);
}
/* this is a weak define that we are overriding */
int board_mmc_init(bd_t *bd)
{
/* Enable muxes, etc. for SDMMC controllers */
pin_mux_mmc();
/* init dev 0, SD slot, with 4-bit bus */
tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
return 0;
}
#endif

26
board/compal/paz00/paz00.c
View File

@ -18,19 +18,14 @@
#include <asm/io.h>
#include <asm/arch/tegra.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/mmc.h>
#include <asm/gpio.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
#ifdef CONFIG_TEGRA_MMC
/*
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
*/
static void pin_mux_mmc(void)
void pin_mux_mmc(void)
{
/* SDMMC4: config 3, x8 on 2nd set of pins */
pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
@ -51,25 +46,6 @@ static void pin_mux_mmc(void)
/* For CD GPIO PV5 */
pinmux_tristate_disable(PINGRP_GPV);
}
/* this is a weak define that we are overriding */
int board_mmc_init(bd_t *bd)
{
debug("board_mmc_init called\n");
/* Enable muxes, etc. for SDMMC controllers */
pin_mux_mmc();
debug("board_mmc_init: init eMMC\n");
/* init dev 0, eMMC chip, with 8-bit bus */
tegra_mmc_init(0, 8, -1, -1);
debug("board_mmc_init: init SD slot\n");
/* init dev 3, SD slot, with 4-bit bus */
tegra_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
return 0;
}
#endif
#ifdef CONFIG_LCD

23
board/compulab/trimslice/trimslice.c
View File

@ -27,12 +27,8 @@
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/mmc.h>
#include <asm/gpio.h>
#include <i2c.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
void pin_mux_usb(void)
{
@ -52,7 +48,7 @@ void pin_mux_spi(void)
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
*/
static void pin_mux_mmc(void)
void pin_mux_mmc(void)
{
funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT);
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
@ -60,20 +56,3 @@ static void pin_mux_mmc(void)
/* For CD GPIO PP1 */
pinmux_tristate_disable(PINGRP_DAP3);
}
/* this is a weak define that we are overriding */
int board_mmc_init(bd_t *bd)
{
debug("board_mmc_init called\n");
/* Enable muxes, etc. for SDMMC controllers */
pin_mux_mmc();
/* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */
tegra_mmc_init(0, 4, -1, GPIO_PP1);
/* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */
tegra_mmc_init(3, 4, -1, -1);
return 0;
}

25
board/nvidia/common/board.c
View File

@ -48,6 +48,9 @@
#ifdef CONFIG_USB_EHCI_TEGRA
#include <asm/arch-tegra/usb.h>
#endif
#ifdef CONFIG_TEGRA_MMC
#include <asm/arch-tegra/mmc.h>
#endif
#include <i2c.h>
#include <spi.h>
#include "emc.h"
@ -221,3 +224,25 @@ int board_late_init(void)
#endif
return 0;
}
#if defined(CONFIG_TEGRA_MMC)
void __pin_mux_mmc(void)
{
}
void pin_mux_mmc(void) __attribute__((weak, alias("__pin_mux_mmc")));
/* this is a weak define that we are overriding */
int board_mmc_init(bd_t *bd)
{
debug("%s called\n", __func__);
/* Enable muxes, etc. for SDMMC controllers */
pin_mux_mmc();
debug("%s: init MMC\n", __func__);
tegra_mmc_init();
return 0;
}
#endif

26
board/nvidia/harmony/harmony.c
View File

@ -27,19 +27,14 @@
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/mmc.h>
#include <asm/gpio.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
#ifdef CONFIG_TEGRA_MMC
/*
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
*/
static void pin_mux_mmc(void)
void pin_mux_mmc(void)
{
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT);
@ -54,25 +49,6 @@ static void pin_mux_mmc(void)
/* For CD GPIO PI5 */
pinmux_tristate_disable(PINGRP_ATC);
}
/* this is a weak define that we are overriding */
int board_mmc_init(bd_t *bd)
{
debug("board_mmc_init called\n");
/* Enable muxes, etc. for SDMMC controllers */
pin_mux_mmc();
debug("board_mmc_init: init SD slot J26\n");
/* init dev 0, SD slot J26, with 8-bit bus */
tegra_mmc_init(0, 8, GPIO_PI6, GPIO_PH2);
debug("board_mmc_init: init SD slot J5\n");
/* init dev 2, SD slot J5, with 4-bit bus */
tegra_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
return 0;
}
#endif
void pin_mux_usb(void)

25
board/nvidia/seaboard/seaboard.c
View File

@ -28,11 +28,7 @@
#include <asm/arch/funcmux.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/mmc.h>
#include <asm/gpio.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
/* TODO: Remove this code when the SPI switch is working */
#if !defined(CONFIG_SPI_UART_SWITCH) && (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
@ -51,7 +47,7 @@ void gpio_early_init_uart(void)
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
*/
static void pin_mux_mmc(void)
void pin_mux_mmc(void)
{
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
@ -61,25 +57,6 @@ static void pin_mux_mmc(void)
/* For CD GPIO PI5 */
pinmux_tristate_disable(PINGRP_ATC);
}
/* this is a weak define that we are overriding */
int board_mmc_init(bd_t *bd)
{
debug("board_mmc_init called\n");
/* Enable muxes, etc. for SDMMC controllers */
pin_mux_mmc();
debug("board_mmc_init: init eMMC\n");
/* init dev 0, eMMC chip, with 8-bit bus */
tegra_mmc_init(0, 8, -1, -1);
debug("board_mmc_init: init SD slot\n");
/* init dev 1, SD slot, with 4-bit bus */
tegra_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
return 0;
}
#endif
void pin_mux_usb(void)

30
board/nvidia/whistler/whistler.c
View File

@ -27,32 +27,19 @@
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/mmc.h>
#include <asm/gpio.h>
#include <i2c.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
/*
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
*/
static void pin_mux_mmc(void)
{
funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT);
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT);
}
/* this is a weak define that we are overriding */
int board_mmc_init(bd_t *bd)
void pin_mux_mmc(void)
{
uchar val;
int ret;
debug("board_mmc_init called\n");
/* Turn on MAX8907B LDO12 to 2.8V for J40 power */
ret = i2c_set_bus_num(0);
if (ret)
@ -70,17 +57,10 @@ int board_mmc_init(bd_t *bd)
if (ret)
printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret);
/* Enable muxes, etc. for SDMMC controllers */
pin_mux_mmc();
/* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */
tegra_mmc_init(0, 8, -1, -1);
/* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */
tegra_mmc_init(1, 8, -1, -1);
return 0;
funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT);
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT);
}
#endif
/* this is a weak define that we are overriding */
void pin_mux_usb(void)

11
board/toradex/colibri_t20_iris/colibri_t20_iris.c
View File

@ -19,7 +19,6 @@
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch-tegra/mmc.h>
#include "../colibri_t20-common/colibri_t20-common.h"
@ -34,13 +33,13 @@ void pin_mux_usb(void)
#endif
#ifdef CONFIG_TEGRA_MMC
int board_mmc_init(bd_t *bd)
/*
* Routine: pin_mux_mmc
* Description: setup the pin muxes/tristate values for the SDMMC(s)
*/
void pin_mux_mmc(void)
{
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
pinmux_tristate_disable(PINGRP_GMB);
tegra_mmc_init(0, 4, -1, GPIO_PC7);
return 0;
}
#endif

179
drivers/mmc/tegra_mmc.c
View File

@ -2,7 +2,7 @@
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Jaehoon Chung <jh80.chung@samsung.com>
* Portions Copyright 2011-2012 NVIDIA Corporation
* Portions Copyright 2011-2013 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -21,6 +21,7 @@
#include <bouncebuf.h>
#include <common.h>
#include <fdtdec.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
@ -28,44 +29,14 @@
#include <asm/arch-tegra/tegra_mmc.h>
#include <mmc.h>
/* support 4 mmc hosts */
struct mmc mmc_dev[4];
struct mmc_host mmc_host[4];
DECLARE_GLOBAL_DATA_PTR;
struct mmc mmc_dev[MAX_HOSTS];
struct mmc_host mmc_host[MAX_HOSTS];
/**
* Get the host address and peripheral ID for a device. Devices are numbered
* from 0 to 3.
*
* @param host Structure to fill in (base, reg, mmc_id)
* @param dev_index Device index (0-3)
*/
static void tegra_get_setup(struct mmc_host *host, int dev_index)
{
debug("tegra_get_setup: dev_index = %d\n", dev_index);
switch (dev_index) {
case 1:
host->base = TEGRA_SDMMC3_BASE;
host->mmc_id = PERIPH_ID_SDMMC3;
break;
case 2:
host->base = TEGRA_SDMMC2_BASE;
host->mmc_id = PERIPH_ID_SDMMC2;
break;
case 3:
host->base = TEGRA_SDMMC1_BASE;
host->mmc_id = PERIPH_ID_SDMMC1;
break;
case 0:
default:
host->base = TEGRA_SDMMC4_BASE;
host->mmc_id = PERIPH_ID_SDMMC4;
break;
}
host->reg = (struct tegra_mmc *)host->base;
}
#ifndef CONFIG_OF_CONTROL
#error "Please enable device tree support to use this driver"
#endif
static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data,
struct bounce_buffer *bbstate)
@ -518,41 +489,43 @@ int tegra_mmc_getcd(struct mmc *mmc)
debug("tegra_mmc_getcd called\n");
if (host->cd_gpio >= 0)
return !gpio_get_value(host->cd_gpio);
if (fdt_gpio_isvalid(&host->cd_gpio))
return fdtdec_get_gpio(&host->cd_gpio);
return 1;
}
int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
static int do_mmc_init(int dev_index)
{
struct mmc_host *host;
char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
struct mmc *mmc;
debug(" tegra_mmc_init: index %d, bus width %d "
"pwr_gpio %d cd_gpio %d\n",
dev_index, bus_width, pwr_gpio, cd_gpio);
/* DT should have been read & host config filled in */
host = &mmc_host[dev_index];
if (!host->enabled)
return -1;
debug(" do_mmc_init: index %d, bus width %d "
"pwr_gpio %d cd_gpio %d\n",
dev_index, host->width,
host->pwr_gpio.gpio, host->cd_gpio.gpio);
host->clock = 0;
host->pwr_gpio = pwr_gpio;
host->cd_gpio = cd_gpio;
tegra_get_setup(host, dev_index);
clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
if (host->pwr_gpio >= 0) {
if (fdt_gpio_isvalid(&host->pwr_gpio)) {
sprintf(gpusage, "SD/MMC%d PWR", dev_index);
gpio_request(host->pwr_gpio, gpusage);
gpio_direction_output(host->pwr_gpio, 1);
gpio_request(host->pwr_gpio.gpio, gpusage);
gpio_direction_output(host->pwr_gpio.gpio, 1);
debug(" Power GPIO name = %s\n", host->pwr_gpio.name);
}
if (host->cd_gpio >= 0) {
if (fdt_gpio_isvalid(&host->cd_gpio)) {
sprintf(gpusage, "SD/MMC%d CD", dev_index);
gpio_request(host->cd_gpio, gpusage);
gpio_direction_input(host->cd_gpio);
gpio_request(host->cd_gpio.gpio, gpusage);
gpio_direction_input(host->cd_gpio.gpio);
debug(" CD GPIO name = %s\n", host->cd_gpio.name);
}
mmc = &mmc_dev[dev_index];
@ -567,9 +540,9 @@ int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->host_caps = 0;
if (bus_width == 8)
if (host->width == 8)
mmc->host_caps |= MMC_MODE_8BIT;
if (bus_width >= 4)
if (host->width >= 4)
mmc->host_caps |= MMC_MODE_4BIT;
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
@ -578,8 +551,6 @@ int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
* low-speed SDIO card frequency (actually 400KHz)
* max freq is highest HS eMMC clock as per the SD/MMC spec
* (actually 52MHz)
* Both of these are the closest equivalents w/216MHz source
* clock and Tegra SDMMC divisors.
*/
mmc->f_min = 375000;
mmc->f_max = 48000000;
@ -588,3 +559,95 @@ int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
return 0;
}
/**
* Get the host address and peripheral ID for a node.
*
* @param blob fdt blob
* @param node Device index (0-3)
* @param host Structure to fill in (reg, width, mmc_id)
*/
static int mmc_get_config(const void *blob, int node, struct mmc_host *host)
{
debug("%s: node = %d\n", __func__, node);
host->enabled = fdtdec_get_is_enabled(blob, node);
host->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg");
if ((fdt_addr_t)host->reg == FDT_ADDR_T_NONE) {
debug("%s: no sdmmc base reg info found\n", __func__);
return -FDT_ERR_NOTFOUND;
}
host->mmc_id = clock_decode_periph_id(blob, node);
if (host->mmc_id == PERIPH_ID_NONE) {
debug("%s: could not decode periph id\n", __func__);
return -FDT_ERR_NOTFOUND;
}
/*
* NOTE: mmc->bus_width is determined by mmc.c dynamically.
* TBD: Override it with this value?
*/
host->width = fdtdec_get_int(blob, node, "bus-width", 0);
if (!host->width)
debug("%s: no sdmmc width found\n", __func__);
/* These GPIOs are optional */
fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio);
fdtdec_decode_gpio(blob, node, "wp-gpios", &host->wp_gpio);
fdtdec_decode_gpio(blob, node, "power-gpios", &host->pwr_gpio);
debug("%s: found controller at %p, width = %d, periph_id = %d\n",
__func__, host->reg, host->width, host->mmc_id);
return 0;
}
/*
* Process a list of nodes, adding them to our list of SDMMC ports.
*
* @param blob fdt blob
* @param node_list list of nodes to process (any <=0 are ignored)
* @param count number of nodes to process
* @return 0 if ok, -1 on error
*/
static int process_nodes(const void *blob, int node_list[], int count)
{
struct mmc_host *host;
int i, node;
debug("%s: count = %d\n", __func__, count);
/* build mmc_host[] for each controller */
for (i = 0; i < count; i++) {
node = node_list[i];
if (node <= 0)
continue;
host = &mmc_host[i];
host->id = i;
if (mmc_get_config(blob, node, host)) {
printf("%s: failed to decode dev %d\n", __func__, i);
return -1;
}
do_mmc_init(i);
}
return 0;
}
void tegra_mmc_init(void)
{
int node_list[MAX_HOSTS], count;
const void *blob = gd->fdt_blob;
debug("%s entry\n", __func__);
count = fdtdec_find_aliases_for_id(blob, "sdhci",
COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS);
debug("%s: count of sdhci nodes is %d\n", __func__, count);
if (process_nodes(blob, node_list, count)) {
printf("%s: Error processing mmc node(s)!\n", __func__);
return;
}
}

1
include/fdtdec.h
View File

@ -71,6 +71,7 @@ enum fdt_compat_id {
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra SDMMC controller */
COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */
COMPAT_NVIDIA_TEGRA20_SLINK, /* Tegra 2 SPI SLINK controller */
COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */

1
lib/fdtdec.c
View File

@ -46,6 +46,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"),
COMPAT(NVIDIA_TEGRA20_SLINK, "nvidia,tegra20-slink"),
COMPAT(SMSC_LAN9215, "smsc,lan9215"),