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riscv: move the AX25-specific implementation of flush_dcache_all

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The fence instruction is used to enforce device I/O and memory ordering
constraints in RISC-V. It can not be relied on to directly affect the
data cache on every CPU.
Andes' AX25 does not have a coherence agent. Its fence instruction
flushes the data cache and is used to keep data in the system coherent.
The implementation of flush_dcache_all in lib/cache.c is therefore
specific to the AX25. Move it into the AX25-specific cache.c in
cpu/ax25/.

This also adds a missing new line between flush_dcache_all and
flush_dcache_range in lib/cache.c.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Lukas Auer 2019-01-04 01:37:29 +01:00 committed by Andes
parent 0c85c113c4
commit c9056653ec
2 changed files with 26 additions and 6 deletions
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22
arch/riscv/cpu/ax25/cache.c
View File

@ -6,6 +6,28 @@
#include <common.h> #include <common.h>
void flush_dcache_all(void)
{
/*
* Andes' AX25 does not have a coherence agent. U-Boot must use data
* cache flush and invalidate functions to keep data in the system
* coherent.
* The implementation of the fence instruction in the AX25 flushes the
* data cache and is used for this purpose.
*/
asm volatile ("fence" ::: "memory");
}
void flush_dcache_range(unsigned long start, unsigned long end)
{
flush_dcache_all();
}
void invalidate_dcache_range(unsigned long start, unsigned long end)
{
flush_dcache_all();
}
void icache_enable(void) void icache_enable(void)
{ {
#ifndef CONFIG_SYS_ICACHE_OFF #ifndef CONFIG_SYS_ICACHE_OFF

10
arch/riscv/lib/cache.c
View File

@ -11,13 +11,12 @@ void invalidate_icache_all(void)
asm volatile ("fence.i" ::: "memory"); asm volatile ("fence.i" ::: "memory");
} }
void flush_dcache_all(void) __weak void flush_dcache_all(void)
{ {
asm volatile ("fence" :::"memory");
} }
void flush_dcache_range(unsigned long start, unsigned long end)
__weak void flush_dcache_range(unsigned long start, unsigned long end)
{ {
flush_dcache_all();
} }
void invalidate_icache_range(unsigned long start, unsigned long end) void invalidate_icache_range(unsigned long start, unsigned long end)
@ -29,9 +28,8 @@ void invalidate_icache_range(unsigned long start, unsigned long end)
invalidate_icache_all(); invalidate_icache_all();
} }
void invalidate_dcache_range(unsigned long start, unsigned long end) __weak void invalidate_dcache_range(unsigned long start, unsigned long end)
{ {
flush_dcache_all();
} }
void cache_flush(void) void cache_flush(void)